Abstract: This invention generally relates to a patterned substrate for an electronic device and to electronic devices, device arrays, field effect transistors and transistor arrays comprising the patterned substrate. The invention also relates to a logic circuit, display, memory or sensor device comprising the patterned substrate. Further the invention relates to a method of patterning a substrate for an electronic device. In an embodiment, a patterned substrate for an electronic device comprises: a first body having an edge; a second body comprising an elongate plurality of printed droplets having an edge adjacent to and substantially aligned to said first body edge; and a separation between said first body edge and said second body edge, wherein said elongate plurality of printed droplets is at an angle of about 5 degrees to about 90 degrees to said first body edge.

Abstract: Disclosed is a damascene method for forming a semiconductor structure and the resulting semiconductor structure having multiple fin-shaped channel regions with different widths. In the method, fin-shaped channel regions are etched using differently configured isolating caps as masks to define the different widths. For example, a wide width isolating cap can comprise a dielectric body positioned laterally between dielectric spacers and can be used as a mask to define a relatively wide width channel region; a medium width isolating cap can comprise a dielectric body alone and can be used as a mask to define a medium width channel region and/or a narrow width isolating cap can comprise a dielectric spacer alone and can be used as a mask to define a relatively narrow width channel region. These multiple fin-shaped channel regions with different widths can be incorporated into either multiple multi-gate field effect transistors (MUGFETs) or a single MUGFET.

Abstract: Bottom sides of two semiconductor substrates are brought together with at least one bonding material layer therebetween and bonded to form a bonded substrate. A cavity with two openings and a contiguous path therebetween is provided within the at least one bonding layer. At least one through substrate via and other metal interconnect structures are formed within the bonded substrate. The cavity is employed as a cooling channel through which a cooling fluid flows to cool the bonded semiconductor substrate during the operation of the semiconductor devices in the bonded substrate. Alternatively, a conductive cooling fin with two end portions and a contiguous path therebetween is formed within the at least one bonding layer. The two end portions of the conductive cooling fin are connected to heat sinks to cool the bonded semiconductor substrate during the operation of the semiconductor devices in the bonded substrate.

Abstract: A semiconductor chip has an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. A bottom, or floor, of the independently voltage controlled silicon region is a deep implant of opposite doping to a doping of a substrate of the independently voltage controlled silicon region. A top, or ceiling, of the independently voltage controlled silicon region is a buried oxide implant in the substrate. Sides of the independently voltage controlled silicon region are deep trench isolation. Voltage of the independently voltage controlled silicon region is applied through a contact structure formed through the buried oxide.

Abstract: A peripheral circuit area is formed around a memory cell array area. The peripheral circuit area has element regions, an element isolation region isolating the element regions, and field-effect transistor formed in each of the element regions and including a gate electrode extending in a channel width direction, on a semiconductor substrate. An end portion and a corner portion of the gate electrode are on the element isolation region. A radius of curvature of the corner portion of the gate electrode is smaller than a length from the end portion of the element region in the channel width direction to the end portion of the gate electrode in the channel width direction, and is less than 85 nm.

Abstract: Devices and methods for forming a self-aligned airgap interconnect structure includes etching a conductive layer to a substrate to form conductive structures with patterned gaps and filling the gaps with a sacrificial material. The sacrificial material is planarized to expose a top surface of the conductive layer. A permeable cap layer is deposited over the conductive structure and the sacrificial material. Self-aligned airgaps are formed by removing the sacrificial material through the permeable layer.

Abstract: In one embodiment, a method of forming an insulating spacer includes providing a base layer, providing an intermediate layer above an upper surface of the base layer, etching a first trench in the intermediate layer, depositing a first insulating material portion within the first trench, depositing a second insulating material portion above an upper surface of the intermediate layer, forming an upper layer above an upper surface of the second insulating material portion, etching a second trench in the upper layer, and depositing a third insulating material portion within the second trench and on the upper surface of the second insulating material portion.

Abstract: A semiconductor structure such as a power converter with an integrated capacitor is provided, and comprises a semiconductor substrate, a high-side output power device over the substrate at a first location, and a low-side output power device over the substrate at a second location adjacent to the first location. A first metal layer is over the high-side output power device and electrically coupled to the high-side output power device, and a second metal layer is over the low-side output power device and electrically coupled to the low-side output power device. A dielectric layer is over a portion of the first metal layer and a portion of the second metal layer, and a top metal layer is over the dielectric layer.

Abstract: A method of preparing a patterned film on a substrate includes applying a silicone composition onto a substrate to form a film of the silicone composition. A portion of the film is exposed to radiation to produce a partially exposed film having an exposed region and a non-exposed region. The partially exposed film is heated for a sufficient amount of time and at a sufficient temperature to substantially insolubilize the exposed region in a developing solvent that includes a siloxane component. The non-exposed region of the partially exposed film is removed with the developing solvent to reveal a film-free region on the substrate and to form the patterned film including the exposed region that remains on the substrate. The film-free regions is substantially free of residual silicone due to the presence of the siloxane component in the developing solvent.

Abstract: An isolation structure, such as a trench isolation structure, may be formed by forming an aperture in a semiconductor substrate and then filling the aperture with boron. In some embodiments, the aperture filling may use atomic layer deposition. In some cases, the boron may be amorphous boron. The aperture may be a high aspect ratio aperture, such as a trench, in some embodiments.

Abstract: A method of forming a field effect transistor includes forming trench isolation material within a semiconductor substrate and on opposing sides of a semiconductor material channel region along a length of the channel region. The trench isolation material is formed to comprise opposing insulative projections extending toward one another partially under the channel region along the channel length and with semiconductor material being received over the projections. The trench isolation material is etched to expose opposing sides of the semiconductor material along the channel length. The exposed opposing sides of the semiconductor material are etched along the channel length to form a channel fin projecting upwardly relative to the projections. A gate is formed over a top and opposing sides of the fin along the channel length. Other methods and structures are disclosed.

Abstract: Electronic elements having an active device region and integrated passive device (IPD) region on a common substrate preferably include a composite dielectric region in the IPD region underlying the IPD to reduce electro-magnetic (E-M) coupling to the substrate. Mechanical stress created by plain dielectric regions and its deleterious affect on performance, manufacturing yield and occupied area may be avoided by providing electrically isolated inclusions in the composite dielectric region of a material having a thermal expansion coefficient (TEC) less than that of the dielectric material in the composite dielectric region. For silicon substrates, non-single crystal silicon is suitable for the inclusions and silicon oxide for the dielectric material. The inclusions preferably have a blade-like shape separated by and enclosed within the dielectric material.

Abstract: The first electrode of the transistor may include a first electrically conductive region provided within the semiconductor substrate. The second electrode may include a second electrically conductive region provided within the semiconductor substrate. The first and second regions may be separated by the substrate region, and the control electrode may include a third electrically conductive region provided within the substrate. The third electrically conductive region may be both separated from the substrate region by an insulating region and electrically coupled to the substrate region by a junction diode intended to be reverse-biased.

Abstract: A resistive random access memory (RRAM) devices and resistive random access memory (RRAM) arrays are provided, the RRAM devices include a first electrode layer, a variable resistance material layer formed of an oxide of a metallic material having a plurality of oxidation states, an intermediate electrode layer on the variable resistance material layer and formed of a conductive material having a lower reactivity with oxygen than the metallic material, and a second electrode layer on the intermediate electrode layer. The RRAM arrays include at least one of the aforementioned RRAM devices.

Abstract: An object of the present invention is to provide a semiconductor device including an insulating layer with a high dielectric strength voltage, a low dielectric constant, and low hygroscopicity. Another object of the present invention is to provide an electronic appliance with high performance and high reliability, which uses the semiconductor device. An insulator containing nitrogen, such as silicon oxynitride or silicon nitride oxide, and an insulator containing nitrogen and fluorine, such as silicon oxynitride added with fluorine or silicon nitride oxide added with fluorine, are alternately deposited so that an insulating layer is formed. By sandwiching an insulator containing nitrogen and fluorine between insulators containing nitrogen, the insulator containing nitrogen and fluorine can be prevented from absorbing moisture and thus a dielectric strength voltage can be increased. Further, an insulator contains fluorine so that a dielectric constant can be reduced.

Abstract: A semiconductor memory device includes a semiconductor substrate, a plurality of element isolations, a plurality of first stacked bodies, a second stacked body, and an interlayer insulating film. Distance between each of the first stacked bodies and the second stacked body is longer than distance between adjacent ones of the first stacked bodies. A first void is formed in the interlayer insulating film between the first stacked bodies. A second void is formed in the interlayer insulating film between one of the first stacked bodies and the second stacked body. And, a lower end of the second void is located above a lower end of the first void.

Abstract: FDSOI devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a device includes the following steps. A wafer is provided having a substrate, a BOX and a SOI layer. A hardmask layer is deposited over the SOI layer. A photoresist layer is deposited over the hardmask layer and patterned into groups of segments. A tilted implant is performed to damage all but those portions of the hardmask layer covered or shadowed by the segments. Portions of the hardmask layer damaged by the implant are removed. A first etch is performed through the hardmask layer to form a deep trench in the SOI layer, the BOX and at least a portion of the substrate. The hardmask layer is patterned using the patterned photoresist layer. A second etch is performed through the hardmask layer to form shallow trenches in the SOI layer.

Abstract: The disclosure relates generally to a metal-oxide-semiconductor field effect transistor (MOSFET) structures and methods of forming the same. The MOSFET structure includes at least one semiconductor body on a substrate; a dielectric cap on a top surface of the at least one semiconductor body, wherein a width of the at least one semiconductor body is less than a width of the dielectric cap; a gate dielectric layer conformally coating the at least one semiconductor body; and at least one electrically conductive gate on the gate dielectric layer.

Abstract: A method of forming a shallow trench isolation region is provided. The method includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; performing a conformal deposition method to fill a dielectric material into the opening; performing a first treatment on the dielectric material, wherein the first treatment provides an energy high enough for breaking bonds in the dielectric material; and performing a steam anneal on the dielectric material.

Abstract: A method for fabricating a structure for use in fabrication of a PiN heterojunction tunnel field effect transistor (TFET) includes forming an alignment trench in a silicon wafer; forming a silicon germanium (SiGe) growth trench in the silicon wafer; growing a p-type SiGe region in the SiGe growth trench; forming a first oxide layer over the alignment trench and the p-type SiGe region; forming a hydrogen implantation region in the silicon wafer, the hydrogen implantation region dividing the silicon wafer into a upper silicon region and a lower silicon region; bonding the first oxide layer to a second oxide layer located on a handle wafer, forming a bonded oxide layer comprising the first oxide layer and the second oxide layer; and separating the lower silicon region from the upper silicon region at the hydrogen implantation region.

Abstract: A region-divided substrate includes: a substrate having a first surface and a second surface opposite to the first surface and having a plurality of partial regions, which are divided by a plurality of trenches, wherein each trench penetrates the substrate from the first surface to the second surface; a conductive layer having an electrical conductivity higher than the substrate and disposed on a sidewall of one of the plurality of partial regions from the first surface to the second surface; and an insulator embedded in each trench.

Abstract: A method for fabricating a semiconductor device includes: providing a substrate; forming a plurality of trenches by etching the substrate; forming a first isolation layer by filling the plurality of the trenches with a first insulation layer; recessing the first insulation layer filling a first group of the plurality of the trenches to a predetermined depth; forming a liner layer over the first group of the trenches with the first insulation layer recessed to the predetermined depth; and forming a second isolation layer by filling the first group of the trenches, where the liner layer is formed, with a second insulation layer.

Abstract: A device includes a top metal layer; a UTM line over the top metal layer and having a first thickness; and a passivation layer over the UTM line and having a second thickness. A ratio of the second thickness to the first thickness is less than about 0.33.

Abstract: A semiconductor structure and a method for forming the structure are provided. The semiconductor structure has a STI structure which has a top surface higher than or as high as that of source/drain stressors. A dummy gate and a spacer are added on the STI structure. The method comprises: providing a semiconductor substrate; embedding a STI structure in the semiconductor substrate in order to form isolated active areas; forming a gate stack on the active area, and forming a dummy gate on the STI structure; forming a first spacer on sidewalls of the dummy gate, wherein a part of the first spacer lands on the active area; and embedding source/drain stressors in the semiconductor substrate and at opposite sides of the gate stack, wherein the top surface of the STI structure is higher than or as high as that of the source/drain stressor.

Abstract: A semiconductor device comprises a memory area including floating body transistors in the form of pillar structures, which are formed in a bulk architecture. The pillar structures may be appropriately addressed on the basis of a buried word line and a buried sense region or sense lines in combination with an appropriate bit line contact regime.

Abstract: A method for making a semiconductor device by reshaping a silicon surface with a sacrificial layer is presented. In the present invention the steps of forming a sacrificial dielectric layer and removing the sacrificial dielectric layer are repeated multiple times in order to remove sharp edges from the silicon surface near the field oxides. Another aspect of the present invention includes making a MOSFET transistor that incorporates the forming and removing of multiple sacrificial layers into the process.

Abstract: A semiconductor structure includes a semiconductor substrate with a substrate region and a trench extending into the surface region of the semiconductor substrate. The trench includes sidewalls, a bottom and a depth. The semiconductor structure further includes a trench liner overlying the bottom and the sidewalls of the trench. The semiconductor structure also includes a shallow trench isolation structure filling at least the depth of the trench. The shallow trench isolation structure is formed from alternating layers of silicon nitride and high-density plasma oxide.

Abstract: The method for manufacturing an SOI substrate includes the following steps: forming an insulating film on a semiconductor substrate; exposing the semiconductor substrate to accelerated ions so that an embrittlement region is formed in the semiconductor substrate; bonding the semiconductor substrate to a base substrate with the insulating film interposed therebetween; separating the semiconductor substrate along the embrittlement region so that a semiconductor film is provided over the base substrate with the insulating film interposed therebetween; and forming a mask over the semiconductor film to etch part of the semiconductor film and part of the insulating film so that the periphery of the semiconductor film is on the inner side than the periphery of the insulating film.

Abstract: Provided is a method of fabricating a semiconductor device that includes providing a semiconductor substrate having a front side and a back side, forming a first circuit and a second circuit at the front side of the semiconductor substrate, bonding the front side of the semiconductor substrate to a carrier substrate, thinning the semiconductor substrate from the back side, and forming an trench from the back side to the front side of the semiconductor substrate to isolate the first circuit from the second circuit.

Abstract: The invention relates to a semiconductor structures and methods of manufacture and, more particularly, to a dual contact trench resistor in shallow trench isolation (STI) and methods of manufacture. In a first aspect of the invention, a method comprises forming a trench in a substrate; forming a first insulator layer within the trench; forming a first electrode within the trench, on the first insulator layer, and isolated from the substrate by the first insulator layer; forming a second insulator layer within the trench and on the first electrode; and forming a second electrode within the trench, on the second insulator layer, and isolated from the substrate by the first insulator layer and the second insulator layer.

Abstract: An trench isolation structure and method for manufacturing the trench isolation structure are disclosed. An exemplary trench isolation structure includes a first portion and a second portion. The first portion extends from a surface of a semiconductor substrate to a first depth in the semiconductor substrate, and has a width that tapers from a first width at the surface of the semiconductor substrate to a second width at the first depth, the first width being greater than the second width. The second portion extends from the first depth to a second depth in the semiconductor substrate, and has substantially the second width from the first depth to the second depth.

Abstract: A semiconductor device includes a trench formed in a substrate and defining a plurality of active regions, a punch-through prevention layer filling a part of the trench and coupled to a ground, and an isolation layer formed over the punch-through prevention layer and filling the other part of the trench.

Abstract: A semiconductor device is provided that in one embodiment includes at least one semiconductor fin structure atop a dielectric surface, the semiconductor fin structure including a channel region of a first conductivity type and source and drain regions of a second conductivity type, in which the source and drain regions are present at opposing ends of the semiconductor fin structure. A high-k gate dielectric layer having a thickness ranging from 1.0 nm to 5.0 nm is in direct contact with the channel of the semiconductor fin structure. At least one gate conductor layer is in direct contact with the high-k gate dielectric layer. A method of forming the aforementioned device is also provided.

Abstract: An integrated circuit (IC) chip is provided comprising at least one trench including a stress-inducing material which imparts a stress on a channel region of a device, such as a junction gate field-effect transistor (JFET) or a metal-oxide-semiconductor field-effect transistor (MOSFET). A related method is also disclosed.

Abstract: There are provided a semiconductor device and a method of forming the same. The semiconductor device may include a semiconductor substrate including a digital circuit region and an analog circuit region, a device isolation layer on the boundary between the digital circuit region and the analog circuit region, a conductive region adjacent to the side surface and the bottom surface of the isolation layer, and a ground pad which is electrically connected to the conductive region and to which a ground voltage is applied.

Abstract: A method of making a semi-insulating epitaxial layer includes implanting a substrate or a first epitaxial layer formed on the substrate with boron ions to form a boron implanted region on a surface of the substrate or on a surface of the first epitaxial layer, and growing a second epitaxial layer on the boron implanted region of the substrate or on the boron implanted region of the first epitaxial layer to form a semi-insulating epitaxial layer.

Abstract: A semiconductor memory device includes a semiconductor substrate defining active regions partitioned by an isolation region, conductive lines spaced apart from each other and crossing the active regions over the semiconductor substrate, a thin film pattern formed on a top portion of the conductive lines having opening portions exposing part of the conductive lines in a width wider than a width of the conductive lines, an insulating layer filling the opening portions and formed over the thin film pattern, and an air gap formed between the conductive lines below the insulating layer and the thin film pattern.

Abstract: A method of fabricating an integrated circuit and an integrated circuit having silicon on a stress liner are disclosed. In one embodiment, the method comprises providing a semiconductor substrate comprising an embedded disposable layer, and removing at least a portion of the disposable layer to form a void within the substrate. This method further comprises depositing a material in that void to form a stress liner, and forming a transistor on an outside semiconductor layer of the substrate. This semiconductor layer separates the transistor from the stress liner. In one embodiment, the substrate includes isolation regions; and the removing includes forming recesses in the isolation regions, and removing at least a portion of the disposable layer via these recesses. In one embodiment, the depositing includes depositing a material in the void via the recesses. End caps may be formed in the recesses at ends of the stress liner.

Abstract: A MEMS device and method of making same is disclosed. In one embodiment, a micro-switch includes a base assembly comprising a movable structure bearing a contact pad. The base assembly is wafer-scale bonded to a lid assembly comprising an activator and a signal path. The movable structure moves within a sealed cavity formed during the bonding process. The signal path includes an input line and an output line separated by a gap, which prevents signals from propagating through the micro-switch when the switch is deactivated. In operation, a signal is launched into the signal path. When the micro-switch is activated, a force is established by the actuator, which pulls a portion of the movable structure upwards towards the gap in the signal path, until the contact pad bridges the gap between the input line and output line, allowing the signal to propagate through the micro-switch.

Abstract: Methods for producing silicon on insulator structures with a reduced metal content in the device layer thereof are disclosed. Silicon on insulator structures with a reduced metal content are also disclosed.

Abstract: Methods of making fins and semiconductor structures containing fins are provided. The methods involve forming a multi-layer structure over a semiconductor substrate. The multi-layer structure comprises a first layer over the semiconductor substrate, a second layer over the first layer, and a third layer over the second layer. The method also comprises removing upper portions of the semiconductor substrate and portions of the multi-layer structure to form fins of the semiconductor substrate and portions of the multi-layer structure. Further, the method comprises selectively oxidizing the first layer while oxidization of the second layer and the third layer is less than the oxidization of the first layer. The oxidation can be performed before gap fill recess or after gap fill recess.

Abstract: The embodiments described provide methods and structures for doping oxide in the STIs with carbon to make etch rate in the narrow and wide structures equal and also to make corners of wide STIs strong. Such carbon doping can be performed by ion beam (ion implant) or by plasma doping. The hard mask layer can be used to protect the silicon underneath from doping. By using the doping mechanism, the even surface topography of silicon and STI enables patterning of gate structures and ILD0 gapfill for advanced processing technology.

Abstract: A shallow trench isolation region is provided in which void formation is substantially or totally eliminated therefrom. The shallow trench isolation mitigates active shorts between two active regions of a semiconductor substrate. The shallow trench isolation region includes a bilayer liner which is present on sidewalls and a bottom wall of a trench that is formed in a semiconductor substrate. The bilayer liner of the present disclosure includes, from bottom to top, a shallow trench isolation liner, e.g., a semiconductor oxide and/or nitride, and a high k liner, e.g., a dielectric material having a dielectric constant that is greater than silicon oxide.

Abstract: A method and structure provide for customizing STI, shallow trench isolation, structures in various parts of a system-on-chip, SOC, or other semiconductor integrated circuit device. Within an individual chip, STI structures are formed to include different dielectric thicknesses that are particularly advantageous for the particular device portion of the SOC chip in which the STI structure is formed.

Abstract: Technology is described herein for manufacturing a three-dimensional 3D stacked memory structure having multiple layers of single crystal silicon or other semiconductor. The multiple layers of single crystal semiconductor are suitable for implementing multiple levels of high performance memory cells.

Abstract: Methods of isolating gates in a semiconductor structure. In one embodiment, isolation is achieved using a spacer material in combination with fins. In another embodiment, etch characteristics of various materials utilized in fabrication of the semiconductor structure are used to increase an effective gate length (“Leffective”) and a field gate oxide. Semiconductor structures formed by these methods are also disclosed.

Abstract: An integrated circuit and a production method is disclosed. One embodiment forms reverse-current complexes in a semiconductor well, so that the charge carriers, forming a damaging reverse current, cannot flow into the substrate.

Abstract: Fin-FET (fin field effect transistor) devices and methods of fabrication are disclosed. The Fin-FET devices include dual fin structures that may form a channel region between a source region and a drain region. In some embodiments, the dual fin structures are formed by forming shallow trench isolation structures, using a pair of shallow trench isolation (STI) structures as a mask to define a recess in a portion of the substrate between the pair of STI structures, and recessing the pair of STI structures so that the resulting dual fin structure protrudes from an active surface of the substrate. The dual fin structure may be used to form single-gate, double-gate, or triple-gate fin-FET devices. Electronic systems including such fin-FET devices are also disclosed.

Abstract: A discrete semiconductor device has a substrate with a first conductivity type of semiconductor material. A first semiconductor layer is formed over the substrate. The first semiconductor layer having the first conductivity type of semiconductor material. A second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second conductivity type of semiconductor material. A trench is formed through the second semiconductor layer and extends into the second semiconductor layer. The trench has a rounded or polygonal shape and vertical sidewalls. The trench is lined with an insulating layer and filled with an insulating material. A boundary between the first and second semiconductor layers forms a p-n junction. The trench surrounds the p-n junction to terminate the electric field of a voltage imposed on the second semiconductor layer. The discrete semiconductor device can also be a transistor, thyristor, triac, or transient voltage suppressor.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed. The method comprises: forming at least one trench in a first semiconductor layer, wherein at least lower portions of respective sidewalls of the trench tilt toward outside of the trench; filling a dielectric material in the trench, thinning the first semiconductor layer so that the first semiconductor layer is recessed with respect to the dielectric material, and epitaxially growing a second semiconductor layer on the first semiconductor layer, wherein the first semiconductor layer and the semiconductor layer comprise different materials from each other. According to embodiments of the disclosure, defects occurring during the heteroepitaxial growth can be effectively suppressed.