Abstract: Methods and structures are provided for implementing independently voltage controlled isolated silicon regions under a buried oxide layer for biasing field effect transistors above the buried oxide layer on Silicon-on-Insulator (SOI) wafers. Using a bonded-wafer technique, a first bulk substrate wafer is bonded with a second wafer providing a buried oxide (BOX) layer under a transistor silicon layer creating an SOI wafer. An independently voltage controlled isolated silicon region is created in the created SOI wafer beneath the BOX layer. The transistor silicon layer is polished to a desired thickness, and normal processing is continued with transistors and desired circuits placed over the isolated silicon region. A contact is formed through the transistor silicon layer and BOX layer to the isolated silicon region for connecting the independently voltage controlled isolated silicon region to a voltage.

Abstract: A semiconductor body of a semiconductor device includes a doped layer of a first conductivity type and one or more doped zones of a second conductivity type. The one or more doped zones are formed between the doped layer and the first surface of a semiconductor body. Trench structures extend from one of the first and the second opposing surface into the semiconductor body. The trench structures are arranged between portions of the semiconductor body which are electrically connected to each other. The trench structures may be arranged for mitigating mechanical stress, locally controlling charge carrier mobility, locally controlling a charge carrier recombination rate and/or shaping buried diffusion zones.

Abstract: An SOI or PSOI device including a device structure having a plurality of doped semiconductor regions. One or more of the doped semiconductor regions is in electrical communication with one or more electrical terminals. The device further includes an insulator layer located between a bottom surface of the device structure and a handle wafer. The device has an insulator trench structure located between a side surface of the device structure and a lateral semiconductor region located laterally with respect to the device structure. The insulator layer and the insulator trench structure are configured to insulate the device structure from the handle wafer and the lateral semiconductor region, and the insulator trench structure includes a plurality of insulator trenches.

Abstract: FDSOI devices and methods for the fabrication thereof are provided. In one aspect, a method for fabricating a device includes the following steps. A wafer is provided having a substrate, a BOX and a SOI layer. A hardmask layer is deposited over the SOI layer. A photoresist layer is deposited over the hardmask layer and patterned into groups of segments. A tilted implant is performed to damage all but those portions of the hardmask layer covered or shadowed by the segments. Portions of the hardmask layer damaged by the implant are removed. A first etch is performed through the hardmask layer to form a deep trench in the SOI layer, the BOX and at least a portion of the substrate. The hardmask layer is patterned using the patterned photoresist layer. A second etch is performed through the hardmask layer to form shallow trenches in the SOI layer.

Abstract: In order to prevent formation of voids in STI film, after a second buried insulating layer is filled and planarized, a high density cap is formed embedded in the center region of the second buried insulating layer of the STI trench. The high density cap shields and protects the weaker center region of the second buried insulating layer of the STI trench from the subsequent processing steps and prevents formation of voids in the second buried insulating layer.

Abstract: A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.

Abstract: A method of forming memory array and peripheral circuitry isolation includes chemical vapor depositing a silicon dioxide-comprising liner over sidewalls of memory array circuitry isolation trenches and peripheral circuitry isolation trenches formed in semiconductor material. Dielectric material is flowed over the silicon dioxide-comprising liner to fill remaining volume of the array isolation trenches and to form a dielectric liner over the silicon dioxide-comprising liner in at least some of the peripheral isolation trenches. The dielectric material is furnace annealed at a temperature no greater than about 500° C. The annealed dielectric material is rapid thermal processed to a temperature no less than about 800° C. A silicon dioxide-comprising material is chemical vapor deposited over the rapid thermal processed dielectric material to fill remaining volume of said at least some peripheral isolation trenches.

Abstract: Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low temperature to chemically modify the polysilazane material to a silicon oxide layer.

Abstract: To provide a semiconductor device that can be manufactured using a simple process without ensuring a high embedding property; and a manufacturing method of the device. In the manufacturing method of the semiconductor device according to the invention, a semiconductor substrate having a configuration obtained by stacking a support substrate, a buried insulating film, and a semiconductor layer in order of mention is prepared first. Then, an element having a conductive portion is completed over the main surface of the semiconductor layer. A trench encompassing the element in a planar view and reaching the buried insulating film from the main surface of the semiconductor layer is formed. A first insulating film (interlayer insulating film) is formed over the element and in the trench to cover the element and form an air gap in the trench, respectively. Then, a contact hole reaching the conductive portion of the element is formed in the first insulating film.

Abstract: A device includes a semiconductor substrate, and a plurality of semiconductor fins parallel to each other, wherein the plurality of semiconductor fins is a portion of the semiconductor substrate. A Shallow Trench Isolation (STI) region is on a side of the plurality of semiconductor fins. The STI region has a top surface and a non-flat bottom surface, wherein the plurality of semiconductor fins is over the top surface of the STI region.

Abstract: A semiconductor device includes a semiconductor substrate having a plurality of isolation regions, a plurality of trenches, where each of the plurality of trenches is formed in a corresponding isolation region, of the plurality of isolation regions, and where the plurality of trenches are arranged, in parallel, along a first direction, a plurality of gate lines formed on the semiconductor substrate in a second direction crossing the plurality of trenches, an insulating layer formed between each of the plurality of gate lines, a first air gap formed in at least one of the plurality of trenches, the first air gap extending in the first direction, and a second air gap formed in at least one of the insulating layers, the second air gap extending in the second direction.

Abstract: The presented principles describe an apparatus and method of making the same, the apparatus being a semiconductor circuit device, having shallow trench isolation features bounding an active area and a periphery area on a semiconductor substrate to electrically isolate structures in the active area from structures in the periphery area. The shallow trench isolation feature bounding the active area is shallower than the shallow trench isolation feature bounding the periphery area, with the periphery area shallow trench isolation structure being formed through two or more etching steps.

Abstract: A semiconductor device includes a trench isolation region provided on a substrate and defining first and second active regions separated from each other. A first semiconductor pillar protruding upward from the first active region is provided. A second semiconductor pillar protruding upward from the second active region is provided. A first gate mask extending to cross over the first and second active regions is provided. The first gate mask surrounds upper sidewalls of the first and second semiconductor pillars. A first gate line formed below the first gate mask, separated from the first and second active regions, and surrounding parts of sidewalls of the first and second semiconductor pillars is provided.

Abstract: A method for fabricating a memory device with U-shaped trap layers over rounded active region corners is disclosed. In the present invention, an STI process is performed before the charge-trapping layer is formed. Immediately after the STI process, the sharp corners of the active regions are exposed, making them available for rounding. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, a bottom oxide layer, nitride layer, and sacrificial top oxide layer are formed. An organic bottom antireflective coating applied to the charge trapping layer is planarized. Now the organic bottom antireflective coating, sacrificial top oxide layer, and nitride layer are etched, without etching the sacrificial top oxide layer and nitride layer over the active regions. After the etching the charge trapping layer has a cross-sectional U-shape appearance.

Abstract: Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer.

Abstract: The present invention discloses a semiconductor device, which comprises: a substrate, and a shallow trench isolation in the substrate, characterized in that, the semiconductor device further comprises a stress release layer between the substrate and the shallow trench isolation. In the semiconductor device and the method for manufacturing the same according to the present invention, the stresses accumulated during the formation of the STI can be released by interposing the stress release layer made of a softer material between the substrate and the STI, thereby reducing the leakage current of the substrate of the device and improving the device reliability.

Abstract: Method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. Low quality nitride and high quality nitride are formed on the semiconductor structure. The high quality nitride in the NFET portion is damaged by ion implantation to facilitate its removal. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The high quality nitride in the PFET portion is damaged by ion implantation to facilitate its removal. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.

Abstract: Methods and apparatus are provided. An isolation region is formed by lining a trench formed in a substrate with a first dielectric layer by forming the first dielectric layer adjoining exposed substrate surfaces within the trench using a high-density plasma process, forming a layer of spin-on dielectric material on the first dielectric layer so as to fill a remaining portion of the trench, and densifying the layer of spin-on dielectric material.

Abstract: A method of forming a shallow trench isolation region is provided. The method includes providing a semiconductor substrate comprising a top surface; forming an opening extending from the top surface into the semiconductor substrate; performing a conformal deposition method to fill a dielectric material into the opening; performing a first treatment on the dielectric material, wherein the first treatment provides an energy high enough for breaking bonds in the dielectric material; and performing a steam anneal on the dielectric material.

Abstract: A through silicon via structure is provided, including a substrate, an isolation layer, a conductive layer and a dielectric layer. The substrate has a through-hole therein. The isolation layer is disposed on two sidewalls of the through-hole. The conductive layer is disposed in the through-hole and covers the isolation layer, and the conductive layer includes a first portion and a second portion, wherein the first portion fills a portion of the through-hole, and the second portion is located on the sidewalls in the other portion of the through-hole, such that the conductive layer has a concave part. The dielectric layer is disposed in the concave part and fills the concave part.

Abstract: A method of forming a semiconductor structure includes forming a resistor on an insulator layer over a substrate, and forming at least one dielectric layer over the resistor. The method also includes forming a substrate contact through the at least one dielectric layer, through the resistor, through the insulator layer, and into the substrate. The substrate contact comprises a high thermal conductivity material.

Abstract: An electrically programmable read only memory (EPROM) BIT cell structure formed on a semiconductor substrate comprises an N-type epitaxial layer formed on the semiconductor substrate, an N-type well region formed in the epitaxial layer, LOCOS field oxide formed at the periphery of the well region to define an active device region in the well region, a field oxide ring formed in the active region and space-apart from the LOCOS field oxide to define an EPROM BIT cell region, and an EPROM BIT cell formed in the EPROM BIT cell region.

Abstract: A manufacturing method of STI in DRAM includes the following steps. Step 1 is providing a substrate and step 2 is forming at least one trench in the substrate. Step 3 is doping at least one of side portions and bottom portions of the trench with a dopant. Step 4 is forming an oxidation inside the trench and step 5 is providing a planarization step to remove the oxidation. The stress of the corners of STI is reduced so as to modify the defect of the substrate and improve the DRAM variability in retention time.

Abstract: A semiconductor component with straight insulation trenches formed in a semiconductor material providing semiconductor areas laterally insulated from each other. Each insulation trench has a uniform width along its longitudinal direction represented by a central line. The semiconductor component has an intersecting area into which at least three of the straight insulation trenches lead. A center of the intersecting area is defined as a point of intersection of the continuations of the center lines. A central semiconductor area disposed in the intersecting area is connected with one of the semiconductor areas and contains the center of the intersecting area.

Abstract: A semiconductor chip has an embedded dynamic random access memory (eDRAM) in an independently voltage controlled silicon region that is a circuit element useful for controlling capacitor values of eDRAM deep trench capacitors and threshold voltages of field effect transistors overlying the independently voltage controlled silicon region. Retention time and performance of the eDRAM is controlled by applying a voltage to the independently voltage controlled silicon region.

Abstract: Phase change memory elements, devices and systems using the same and methods of forming the same are disclosed. A memory element includes first and second electrodes, and a phase change material layer between the first and second electrodes. The phase change material layer has a first portion with a width less than a width of a second portion of the phase change material layer. The first electrode, second electrode and phase change material layer may be oriented at least partially along a same horizontal plane.

Abstract: An apparatus is provided. In the apparatus, there is comprises a substrate with a first region of a first conductivity type, a second region of a second conductivity type that is substantially surrounded by the first region, and a third region of the second conductivity type that is substantially surrounded by the second region. A first dielectric layer is formed over the substrate, and a first conductive layer is formed over the first dielectric layer, which is configured to form a first electrode of a capacitor. A second dielectric layer is formed over the first conductive layer. A plate is formed over the second dielectric layer so as to form a second electrode of the capacitor. A cap is formed over the second dielectric layer, being spaced apart from the plate. A via is electrically coupled to the cap and the third region, extending through the first and second dielectric layers.

Abstract: Disclosed herein are various methods of forming isolation structures, such as trench isolation structures, for semiconductor devices using a spin-on glass material or a flowable oxide material. In one example, the method includes forming a trench in a semiconducting substrate, forming a lower isolation structure comprised of an insulating material in at least the trench, wherein the lower isolation structure has an upper surface that is below an upper surface of the substrate, and forming an upper isolation structure above the lower isolation structure, wherein a portion of the upper isolation structure is positioned within the trench.

Abstract: A method of forming an accumulation-mode field effect transistor includes forming a channel region of a first conductivity type in a semiconductor region of the first conductivity type. The channel region may extend from a top surface of the semiconductor region to a first depth within the semiconductor region. The method also includes forming gate trenches in the semiconductor region. The gate trenches may extend from the top surface of the semiconductor region to a second depth within the semiconductor region below the first depth. The method also includes forming a first plurality of silicon regions of a second conductivity type in the semiconductor region such that the first plurality of silicon regions form P-N junctions with the channel region along vertical walls of the first plurality of silicon regions.

Abstract: Disclosed herein are various methods of forming stepped isolation structures for semiconductor devices using a spacer technique. In one example, the method includes forming a first trench in a semiconducting substrate, wherein the first trench has a bottom surface, a width and a depth, the depth of the first trench being less than a target final depth for a stepped trench isolation structure, performing an etching process through the first trench on an exposed portion of the bottom surface of the first trench to form a second trench in the substrate, wherein the second trench has a width and a depth, and wherein the width of the second trench is less than the width of the first trench, and forming the stepped isolation structure in the first and second trenches.

Abstract: Disclosed herein are various methods of forming isolation structures, such as trench isolation structures, for semiconductor devices. In one example, the method includes forming a trench in a semiconducting substrate, forming a lower isolation structure in the trench, wherein the lower isolation structure has an upper surface that is below an upper surface of the substrate, and forming an upper isolation structure above the lower isolation structure, wherein a portion of the upper isolation structure is positioned within the trench.

Abstract: A method, in one embodiment, can include forming a core trench and a termination trench in a substrate. The termination trench is wider than the core trench. In addition, a first oxide can be deposited that fills the core trench and lines the sidewalls and bottom of the termination trench. A first polysilicon can be deposited into the termination trench. A second oxide can be deposited above the first polysilicon. A mask can be deposited above the second oxide and the termination trench. The first oxide can be removed from the core trench. A third oxide can be deposited that lines the sidewalls and bottom of the core trench. The first oxide within the termination trench is thicker than the third oxide within the core trench.

Abstract: A chip structure includes a substrate and a stress buffer layer. The substrate has a first surface and a second surface opposite to the first surface. The stress buffer layer is disposed on the periphery of the substrate and located in at least one of the first surface and the second surface of the substrate.

Abstract: Semiconductor devices including a trench isolation layer are provided. The semiconductor device includes a substrate having a trench therein, a liner insulation layer that covers a bottom surface and sidewalls of the trench and includes micro trenches located at bottom inner corners of the liner insulation layer, a first isolating insulation layer filling the micro trenches and a lower region of the trench that are surrounded by the liner insulation layer, and a second isolating insulation layer filling the trench on the first isolating insulation layer. The liner insulation layer on sidewalls of an upper region of the trench having a thickness that gradually increases toward a bottom surface of the trench, and the liner insulation layer on sidewalls of the lower region of the trench having a thickness that is uniform. Related methods are also provided.

Abstract: An integrated circuit includes a first trench disposed in a semiconductor material, wherein a width of the first trench in an upper portion of the first trench adjacent to a surface of the semiconductor material is smaller than a width of the first trench in a lower portion of the first trench, the lower portion being disposed within the semiconductor material, each width being measured in a plane parallel to a surface of the semiconductor material, each width denoting a distance between inner faces of remaining semiconductor material portions or between outer faces of a filling disposed in the first trench, or between an inner face of a remaining semiconductor material portion and an outer face of a filling disposed in the first trench.

Abstract: A method of forming an electrical device is provided that includes forming at least one semiconductor device on a first semiconductor layer of the SOI substrate. A handling structure is formed contacting the at least one semiconductor device and the first semiconductor layer. A second semiconductor layer and at least a portion of the dielectric layer of the SOI substrate are removed to provide a substantially exposed surface of the first semiconductor layer. A retrograded well may be formed by implanting dopant through the substantially exposed surface of the first semiconductor layer into a first thickness of the semiconductor layer that extends from the substantially exposed surface of the semiconductor layer, wherein a remaining thickness of the semiconductor layer is substantially free of the retrograded well dopant. The retrograded well may be laser annealed.

Abstract: Disclosed are a structure for electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure includes a trench extending through the top semiconductor layer and into a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a void is disposed in the handle wafer below the trench. A bottom opening of the trench connects the main body of the trench with the void forming a continuous cavity including the main body, the bottom opening of the trench, and the void such that the void improves electrical signal isolation between the adjacent devices situated in the top semiconductor layer. Unetched portions of the handle wafer are then available to provide mechanical support to the top semiconductor layer.

Abstract: Disclosed is a structure for improved electrical signal isolation between adjacent devices situated in a top semiconductor layer of the structure and an associated method for the structure's fabrication. The structure comprises a first portion of a trench extending through the top semiconductor layer and through a base oxide layer below the top semiconductor layer. A handle wafer is situated below the base oxide layer and a second portion of the trench, having sloped sidewalls, extends into the handle wafer. The sloped sidewalls are amorphized by an implant, for example, Xenon or Argon, to reduce carrier mobility in the handle wafer and improve electrical signal isolation between the adjacent devices situated in the top semiconductor layer.

Abstract: A semiconductor device includes an isolated p-type well, wherein the isolated p-type well is a first electrode of a capacitor device; a capacitor dielectric on the isolated p-type well; a p-type polysilicon electrode over the capacitor dielectric, wherein the p-type polysilicon electrode is a second electrode of the capacitor device; a first p-type contact region in the isolated p-type well, laterally extending from a first sidewall of the p-type polysilicon electrode; a second p-type contact region in the isolated p-type well, laterally extending from a second sidewall of the p-type polysilicon electrode, opposite the first sidewall of the p-type polysilicon electrode, wherein a portion of the isolated p-type well between the first and second p-type contact regions is under the p-type polysilicon electrode and the capacitor dielectric; and an n-type isolation region surrounding the isolated p-type well. This device may be conveniently coupled to a fringe capacitor.

Abstract: A semiconductor device, including a semiconductor substrate including isolations defining active regions of the semiconductor substrate, and a plurality of buried gate electrodes between a pair of the isolations, wherein each of the buried gate electrodes and the isolations includes a conductive layer and a capping layer.

Abstract: A structure includes a silicon substrate; at least two wells in the silicon substrate; and a deep trench isolation (DTI) separating the two wells. The DTI has a top portion and a bottom portion having a width that is larger than a width of the top portion. The structure further includes at least two semiconductor devices disposed over one of the wells, where the at least two semiconductor devices are separated by a shallow trench isolation (STI). In the structure sidewalls of the top portion of the DTI and sidewalls of the STI are comprised of doped, re-crystallized silicon. The doped, re-crystallized silicon can be formed by an angled ion implant that uses, for example, one of Xe, In, BF2, B18H22, C16H10, Si, Ge or As as an implant species to amorphize the silicon, and by annealing the amorphized silicon to re-crystallize the amorphized silicon.

Abstract: A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.

Abstract: The instant disclosure relates to a method of forming an isolation area. The method includes the steps of: providing a substrate having a first type of ion dopants, where the substrate has a plurality of trenches formed on the cell areas and the isolation area between the cell areas of the substrate, with the side walls of the trenches having an oxidation layer formed thereon and the trenches are filled with a metallic structure; removing the metallic structure from the trenches of the isolation area; implanting a second type of ions into the substrate under the trenches of the isolation area; and filling all the trenches with an insulating structure, where the trenches of the isolation area are filled up fully by the insulating structure to form a non-metallic isolation area.

Abstract: A semiconductor device includes an isolation trench formed in a semiconductor substrate; an isolation layer filling the isolation trench; and a first epitaxial layer interposed between the isolation layer and the semiconductor substrate, wherein a lattice structure of the semiconductor substrate has an angle difference from a lattice structure of the first epitaxial layer adjacent to the semiconductor substrate.

Abstract: A semiconductor device includes a buried layer and a deep contact for providing a low resistive connection to the buried layer. The deep contact is formed by doped polycrystalline silicon. A method of manufacturing a semiconductor device and a deep contact for providing a low resistive connection to the buried layer, with the steps of forming a buried layer, providing an active region adjacent the buried layer and forming a deep contact for providing a low resistive connection to the buried layer by patterning a contact shape for the deep contact on an upper surface of the active region, removing part of the active region underneath the contact shape to create a deep contact cavity. Subsequently a polycrystalline silicon layer for filling the deep contact cavity is deposited and doped.

Abstract: Two trenches having different widths are formed in a semiconductor-on-insulator (SOI) substrate. An oxygen-impermeable layer and a fill material layer are formed in the trenches. The fill material layer and the oxygen-impermeable layer are removed from within a first trench. A thermal oxidation is performed to convert semiconductor materials underneath sidewalls of the first trench into an upper thermal oxide portion and a lower thermal oxide portion, while the remaining oxygen-impermeable layer on sidewalls of a second trench prevents oxidation of the semiconductor materials. After formation of a node dielectric on sidewalls of the second trench, a conductive material is deposited to fill the trenches, thereby forming a conductive trench fill portion and an inner electrode, respectively. The upper and lower thermal oxide portions function as components of dielectric material portions that electrically isolate two device regions.

Abstract: Provided are a semiconductor device and a method of forming the semiconductor device. The semiconductor device includes an active region of which an edge is curved. The semiconductor device includes a gate insulating layer, a floating gate, a gate interlayer dielectric layer and a control gate line on the active region. The semiconductor device includes an oxide pattern having a concave top surface between adjacent floating gates. The control gate may be sufficiently spaced apart from the active region by the oxide pattern. The method can provide a semiconductor device that includes a reoxidation process, an active region having a curved edge and an oxide pattern having a top surface of a curved concave shape.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type, including a first main surface and a second main surface opposite to each other. A power semiconductor element includes a first electrode in a first region at the first main surface of the semiconductor substrate, and a second electrode at the second main surface. A current flows between the first electrode and the second electrode. The semiconductor device also includes a guard ring of a second conductivity type, in a second region at the first main surface, at a more outer circumference than the first region. A semi-insulating insulation film covers the second region. A dielectric film in the second region covers the semi-insulating insulation film. A flow block portion in a third region at the first main surface, at a more outer circumference than the second region, prevents a flow out of the dielectric film.

Abstract: High Efficiency Diode (HED) rectifiers with improved performance including reduced reverse leakage current, reliable solderability properties, and higher manufacturing yields are fabricated by minimizing topography variation at various stages of fabrication. Variations in the topography are minimized by using a CMP process to planarize the HED rectifier after the field oxide, polysilicon and/or solderable top metal are formed.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor substrate having a first surface and a second surface, and having a LSI on the first surface of the semiconductor substrate, a first insulating layer with an opening, the first insulating layer provided on the first surface of the semiconductor substrate, a conductive layer on the opening, the conductive layer being connected to the LSI, and a via extending from a second surface of the semiconductor substrate to the conductive layer through the opening, the via having a size larger than a size of the opening in a range from the second surface to a first interface between the semiconductor substrate and the first insulating layer, and having a size equal to the size of the opening in the opening.