Abstract: A power amplifier that includes a substrate, and an emitter layer, a base layer, and a collector layer laminated in this order on a major surface of the substrate includes an electrical insulator provided adjacent to the emitter layer, an emitter electrode provided between the substrate and both the emitter layer and the electrical insulator, a base electrode electrically connected to the base layer, and a collector electrode electrically connected to the collector layer. The emitter electrode, the electrical insulator, and the base layer are provided between the substrate and the base electrode in a direction perpendicular to the major surface of the substrate.

Abstract: A semiconductor device may include a semiconductor layer, and a superlattice adjacent the semiconductor layer and including stacked groups of layers. Each group of layers may include stacked base semiconductor monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one oxygen monolayer of a given group of layers may include an atomic percentage of 18O greater than 10 percent.

Abstract: An emitter contact layer, an emitter layer, a base layer, a p-type base layer, a collector layer, and a sub-collector layer are crystal-grown over a first substrate in this order with the main surface as the Group III polar surface. The emitter contact layer includes a nitride semiconductor that is made n-type at a relatively high concentration. The emitter layer includes a nitride semiconductor having a bandgap larger than that of the nitride semiconductor constituting the emitter contact layer. The base layer includes an undoped nitride semiconductor having a bandgap smaller than that of the nitride semiconductor constituting the emitter layer. The p-type base layer includes the same nitride semiconductor as the base layer and made p-type.

Abstract: A semiconductor device includes a compound substrate, at least one front side pattern, at least one backside pattern and at least one through-wafer via structure. The compound substrate includes a front side and a backside. The at least one front side pattern is arranged on the front side of the compound substrate. The at least one backside pattern is arranged on the backside of the compound substrate. The least one through-wafer via structure penetrates the compound substrate from the front side to the backside. The at least one front side pattern, the at least one backside pattern and the at least one through-wafer form a three-dimensional inductor structure.

Abstract: An electronic circuit having a semiconductor device is provided that includes a heterostructure, the heterostructure including a first layer of a compound semiconductor to which a second layer of a compound semiconductor adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), wherein the 2-dimensional electron gas is not present. In aspects, an electronic circuit having a semiconductor device is provided that includes a III-V heterostructure, the III-V heterostructure including a first layer including GaN to which a second layer adjoins in order to form a channel for a 2-dimensional electron gas (2DEG), and having a purity such that the 2-dimensional electron gas is not present. It is therefore advantageous for the present electronic circuit to be enclosed such that, in operation, no light of wavelengths of less than 400 nm may reach the III-V heterostructure and free charge carriers may be generated by these wavelengths.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to bipolar transistors and methods of manufacture. The structure includes: a base region composed of a semiconductor on insulator material; an emitter region above the base region; and a collector region under the base region and within a cavity of a buried insulator layer.

Abstract: Flexible transistors and electronic circuits incorporating the transistors are provided. The flexible transistors promote heat dissipation from the active regions of the transistors while preserving their mechanical flexibility and high-frequency performance. The transistor designs utilize thru-substrate vias (TSVs) beneath the active regions of thin-film type transistors on thin flexible substrates. To promote rapid heat dissipation, the TSVs are coated with a material having a high thermal conductivity that transfers heat from the active region of the transistor to a large-area ground.

Abstract: A heterojunction bipolar transistor includes: a substrate; a base mesa disposed on the substrate, wherein the base mesa includes a collector layer and a base layer disposed on the collector layer, and wherein in a top view, the base layer includes a first edge and a second edge opposite to the first edge; an emitter layer disposed on the base layer; a base electrode disposed on the substrate and connected to the base layer; a dielectric layer disposed on the base electrode, wherein a first via hole is formed in the dielectric layer at the first edge of the base layer, and a second via hole is formed in the dielectric layer at the second edge of the base layer; and a conductive feature disposed on the dielectric layer, wherein the conductive feature is connected to the base electrode through the first via hole and the second via hole.

Abstract: The invention relates to saRNA targeting an HNF4a transcript and therapeutic compositions comprising said saRNA. Methods of using the therapeutic compositions are also provided.

Abstract: A method for making a bipolar junction transistor (BJT) may include forming a first superlattice on a substrate defining a collector region therein. The first superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming a base on the first superlattice, and forming a second superlattice on the base comprising a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may also include forming an emitter on the second superlattice.

Abstract: Provided is a high ruggedness heterojunction bipolar transistor (HBT), including a collector layer. The collector layer includes a InGaP layer or a wide bandgap layer. The bandgap of the InGaP layer is greater than 1.86 eV.

Abstract: A bipolar junction transistor (BJT) may include a substrate defining a collector region therein. A first superlattice may be on the substrate including a plurality of stacked groups of first layers, with each group of first layers including a first plurality of stacked base semiconductor monolayers defining a first base semiconductor portion, and at least one first non-semiconductor monolayer constrained within a crystal lattice of adjacent first base semiconductor portions. Furthermore, a base may be on the first superlattice, and a second superlattice may be on the base including a second plurality of stacked groups of second layers, with each group of second layers including a plurality of stacked base semiconductor monolayers defining a second base semiconductor portion, and at least one second non-semiconductor monolayer constrained within a crystal lattice of adjacent second base semiconductor portions. An emitter may be on the second superlattice.

Abstract: A semiconductor device is provided. The semiconductor device comprises an output circuit configured to be electrically connected between a driving circuit and an external load circuit, and a protection circuit electrically connected to the output circuit and the driving circuit. The protection circuit comprises a first transistor having a base electrode, a collector electrode and an emitter electrode and a second transistor having a base electrode, a collector electrode and an emitter electrode. The base electrode of the first transistor is electrically connected to the collector electrode of the second transistor.

Abstract: A collector layer, a base layer, an emitter layer, and an emitter mesa layer are placed above a substrate in this order. A base electrode and an emitter electrode are further placed above the substrate. The emitter mesa layer has a long shape in a first direction in plan view. The base electrode includes a base electrode pad portion spaced from the emitter mesa layer in the first direction. An emitter wiring line and a base wiring line are placed on the emitter electrode and the base electrode, respectively. The emitter wiring line is connected to the emitter electrode via an emitter contact hole. In the first direction, the spacing between the edges of the emitter mesa layer and the emitter contact hole on the side of the base wiring line is smaller than that between the emitter mesa layer and the base wiring line.

Abstract: Provided is a semiconductor epitaxial wafer, including a substrate, a first epitaxial structure, a first ohmic contact layer and a second epitaxial stack structure. It is characterized in that the ohmic contact layer includes a compound with low nitrogen content, and the ohmic contact layer does not induce significant stress during the crystal growth process. Accordingly, the second epitaxial stack structure formed on the ohmic contact layer can have good epitaxial quality, thereby providing a high-quality semiconductor epitaxial wafer for fabricating a GaAs integrated circuit or a InP integrated circuit. At the same time, the ohmic contact properties of ohmic contact layers are not affected, and the reactants generated during each dry etching process are reduced.

Abstract: An electronic device includes a semiconductor body of silicon carbide, and a body region at a first surface of the semiconductor body. A source region is disposed in the body region. A drain region is disposed at a second surface of the semiconductor body. A doped region extends seamlessly at the entire first surface of the semiconductor body and includes one or more first sub-regions having a first doping concentration and one or more second sub-regions having a second doping concentration lower than the first doping concentration. Thus, the device has zones alternated to each other having different conduction threshold voltage and different saturation current.

Abstract: A target element to be protected and a protrusion are arranged on a substrate. An insulating film arranged on the substrate covers the target element and at least a side surface of the protrusion. An electrode pad for external connection is arranged on the insulating film. The electrode pad at least partially overlaps the target element and the protrusion as seen in plan view. A maximum distance between the upper surface of the protrusion and the electrode pad in the height direction is shorter than a maximum distance between the upper surface of the target element and the electrode pad in the height direction.

Abstract: A semiconductor device may include a semiconductor layer, and a superlattice adjacent the semiconductor layer and including stacked groups of layers. Each group of layers may include stacked base semiconductor monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one oxygen monolayer of a given group of layers may include an atomic percentage of 18O greater than 10 percent.

Abstract: A method for making a semiconductor device may include forming a semiconductor layer, and forming a superlattice adjacent the semiconductor layer and including stacked groups of layers. Each group of layers may include stacked base semiconductor monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one oxygen monolayer of a given group of layers may comprise an atomic percentage of 18O greater than 10 percent.

Abstract: A semiconductor device has a semiconductor substrate, and multiple first bipolar transistors on the first primary surface side of the semiconductor substrate. The first bipolar transistors have a first height between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. The semiconductor device further has at least one second bipolar transistor on the first primary surface side of the semiconductor substrate. The second bipolar transistor have a second height, greater than the first height, between an emitter layer and an emitter electrode in the direction perpendicular to the first primary surface. Also, the semiconductor has a first bump stretching over the multiple first bipolar transistors and the at least one second bipolar transistor.

Abstract: An ESD protection device may include a substrate having first and second substrate layers, and first and second bridged regions. Each substrate layer may include first and second border regions and a middle region laterally therebetween. Each bridged region may be arranged within the middle region and a respective border region of the second substrate layer. The middle region of the second substrate layer may be laterally narrower than the middle region of the first substrate layer. Each border region of the second substrate layer may be partially arranged over the middle region of the first substrate layer and partially arranged over a respective border region of the first substrate layer. The border regions of the substrate layers, and the bridged regions may have a first conductivity type, and the middle regions of the substrate layers may have a second conductivity type different from the first conductivity type.

Abstract: Provided herein are tapered nanowires that comprise germanium and gallium, as well as methods of forming the same. The described nanowires may also include one or more sections of a second semiconductor material. Methods of the disclosure may include vapor-liquid-solid epitaxy with a gallium catalyst. The described methods may also include depositing a gallium seed on a surface of a substrate by charging an area of the substrate using an electron beam, and directing a gallium ion beam across the surface of the substrate.

Abstract: A method for processing a substrate includes positioning a silicon substrate in a deposition chamber. One or more intermediate layers are deposited on a surface of the silicon. The one or more intermediate layers can include strontium, which combines with the silicon to form strontium silicide. Alternatively, the one or more intermediate layers comprise germanium. A layer of amorphous strontium titanate is deposited on the one or more intermediate layers in a transient environment in which oxygen pressure is reduced while temperature is increased. The substrate is then exposed to an oxidizing and annealing atmosphere that oxidizes the one or more intermediate layers and converts the layer of amorphous strontium titanate to crystalline strontium titanate.

Abstract: A semiconductor device includes a plurality of unit transistors that are arranged on a surface of a substrate in a first direction. Input capacitive elements are arranged so as to correspond to the unit transistors. An emitter common wiring line is connected to emitter layers of the unit transistors. A via-hole extending from the emitter common wiring line to a back surface of the substrate is disposed at a position overlapping the emitter common wiring line. A collector common wiring line is connected to collector layers of the unit transistors. The input capacitive elements, the emitter common wiring line, the unit transistors, and the collector common wiring line are arranged in this order in a second direction. Base wiring lines that connect the input capacitive elements to base layers of the corresponding unit transistors intersect the emitter common wiring line without physical contact.

Abstract: Solder bumps are placed in direct contact with the silicon substrate of an amplifier integrated circuit having a flip chip configuration. A plurality of amplifier transistor arrays generate waste heat that promotes thermal run away of the amplifier if not directed out of the integrated circuit. The waste heat flows through the thermally conductive silicon substrate and out the solder bump to a heat-sinking plane of an interposer connected to the amplifier integrated circuit via the solder bumps.

Abstract: A bipolar junction transistor (BJT) may include a substrate defining a collector region therein. A first superlattice may be on the substrate including a plurality of stacked groups of first layers, with each group of first layers including a first plurality of stacked base semiconductor monolayers defining a first base semiconductor portion, and at least one first non-semiconductor monolayer constrained within a crystal lattice of adjacent first base semiconductor portions. Furthermore, a base may be on the first superlattice, and a second superlattice may be on the base including a second plurality of stacked groups of second layers, with each group of second layers including a plurality of stacked base semiconductor monolayers defining a second base semiconductor portion, and at least one second non-semiconductor monolayer constrained within a crystal lattice of adjacent second base semiconductor portions. An emitter may be on the second superlattice.

Abstract: A heterojunction bipolar transistor includes a bottom sub-collector layer formed over a substrate. The heterojunction bipolar transistor also includes an upper sub-collector layer formed over the bottom sub-collector layer. The heterojunction bipolar transistor also includes a collector layer formed over the upper sub-collector layer. The heterojunction bipolar transistor also includes a base layer formed over the collector layer. The heterojunction bipolar transistor also includes an emitter layer formed over the base layer. The heterojunction bipolar transistor also includes a passivation layer covering the bottom sub-collector layer, the upper sub-collector layer, the collector layer, the base layer, and the emitter layer. The heterojunction bipolar transistor also includes a collector electrode that covers the portion of the passivation layer that is over the sidewall of the upper sub-collector layer.

Abstract: A semiconductor device, including: a substrate; a first source/drain layer, a channel layer, and a second source/drain layer sequentially stacked on the substrate and adjacent to each other, and a gate stack formed around an outer circumference of the channel layer; wherein at least one interface structure is formed in at least one of the first source/drain layer and the second source/drain layer, the conduction band energy levels at both sides of the interface structure are different and/or the valence band energy levels are different.

Abstract: A surface emitting laser includes a substrate, a mesa of semiconductor layers including a lower reflector layer, an active layer, an upper reflector layer, and an upper contact layer that are successively laminated on the substrate, and an electrode provided on the upper contact layer. The upper contact layer includes GaAs. The electrode includes an alloy layer including Pt, in contact with the upper contact layer.

Abstract: According to one embodiment, a device includes a first fin structure having first to n-th semiconductor layers (n is a natural number equal to or more than 2) stacked in a first direction perpendicular to a surface of a semiconductor substrate, and extending in a second direction parallel to the surface of the semiconductor substrate, first to n-th memory cells provided on surfaces of the first to n-th semiconductor layers in a third direction perpendicular to the first and second directions respectively, and first to n-th select transistors connected in series to the first to n-th memory cells respectively.

Abstract: A semiconductor device includes a first island and a first electrode. The first island includes a first semiconductor region, a first insulation region, and a first insulating film. The first semiconductor region has first and second side surfaces adjacent to the first insulation region and the first insulating film, respectively. The first electrode is adjacent to the first insulation region and the first insulating film. The first insulating film is between the first electrode and the first semiconductor region.

Abstract: A solar cell may include an electrically conducting substrate, a plurality of nanowhiskers extending from the substrate and a transparent electrode extending over free ends of the nanowhiskers and making electrical contact with them. Each nanowhisker may have a column with a diameter of nanometer dimension. The column may include a first p-doped semiconductor lengthwise segment and a second n-doped semiconductor lengthwise segment. The first and second semiconductor segments may have an interface between them, which forms a p-n junction. The nanowhiskers may be encapsulated in a transparent material.

Abstract: A double heterojunction bipolar transistor on a substrate comprises a collector formed of InGaAsP, a base in contact with the collector, an emitter in contact with the base, and electrodes forming separate electrical contacts with each of the collector, base, and emitter, respectively. A device incorporates this transistor and an opto-electronic device optically coupled with the collector of the transistor to interact with light transmitted therethrough.

Abstract: To provide a transistor device, which is composed of a compound semiconductor, having a multilayer structure in which a high electron mobility transistor (HEMT) and a heterojunction bipolar transistor (HBT) are overlapped on the same substrate and epitaxial-grown thereon, wherein a band gap energy of an indium gallium phosphide layer (InGaP) included in an epitaxial layer, is set to 1.91 eV or more.

Abstract: A semiconductor device includes a drift layer and a body region that forms a p-n junction with the drift layer. A contactor region is in the body region, and a shunt channel region extends through the body region from the contactor region to the drift layer. The shunt channel region has a length, thickness and doping concentration selected such that: 1) the shunt channel region is fully depleted when zero voltage is applied across the first and second terminals, 2) the shunt channel becomes conductive at a voltages less than the built-in potential of the drift layer to body region p-n junction, and/or 3) the shunt channel is not conductive for voltages that reverse bias the p-n junction between the drift region and the body region.

Abstract: A bipolar transistor includes: a substrate; a collector and a base layer with a p-conductive-type, an emitter layer with an n-conductive-type. The collector layer is formed above the substrate and includes a first nitride semiconductor. The base layer with the p-conductive-type is formed on the collector layer and includes a second nit ride semiconductor. The emitter layer with the n-conductive-type is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed so that crystal growing directions with respect to a surface of the substrate are in parallel to a [0001] direction of the substrate. The first nitride semiconductor includes: InycAlxcGa1-xc-ycN (0?xc?1, 0?yc?1, 0<xc+yc?1). In the first nitride semiconductor, a length of an a-axis on a surface side is longer than a length of an a-axis on a substrate side.

Abstract: A semiconductor device 1 includes: a base 2 mainly formed of a semiconductor material; a gate electrode 5; and a gate insulating film 3 provided between the base 2 and the gate electrode 5. The gate insulating film 3 is formed of an insulative inorganic material containing silicon, oxygen and element X other than silicon and oxygen as a main material. The gate insulating film 3 is provided in contact with the base 2, and contains hydrogen atoms. The gate insulating film 3 has a region where A and B satisfy the relation: B/A is 10 or less in the case where the total concentration of the element X in the region is defined as A and the total concentration of hydrogen in the region is defined as B. Further, the region is at least apart of the gate insulating film 3 in the thickness direction thereof.

Abstract: In an embodiment, a bipolar transistor structure is formed on a silicon-on-insulator (SOI) structure that includes a semiconductor substrate, a buried oxide layer formed on the semiconductor substrate and a top silicon layer formed on the buried oxide layer.

Abstract: Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening.

Abstract: A III-V compound semiconductor structure comprises epitaxial structures that include an integrated pair of different types of active devices. The semiconductor structure includes a semi-insulating substrate of a compound semiconductor III-V material and a first compound semiconductor III-V epitaxial structure disposed on the substrate. A concentration profile of dopant material in the semiconductor structure decreases substantially smoothly across an interface between the substrate and the first epitaxial structure in a direction from the first epitaxial structure toward the substrate, and continues to decrease substantially smoothly from the interface with increasing depth into the substrate despite the presence of silicon or oxygen contaminant at the interface. The interface is substantially free of a second contaminant that was present, during formation of the first epitaxial structure, in a chamber in which the first epitaxial structure was formed.

Abstract: A semiconductor-device fabrication method includes forming a second semiconductor region of a second conductivity on a surface layer of a first semiconductor region of a first conductivity, the second semiconductor region having an impurity concentration higher than the first semiconductor region; forming a trench penetrating the second semiconductor region, to the first semiconductor region; embedding a first electrode inside the trench via an insulating film, at a height lower than a surface of the second semiconductor region; forming an interlayer insulating film inside the trench, covering the first electrode; leaving the interlayer insulating film on only a surface of the first electrode; removing the second semiconductor region such that the surface thereof is positioned lower than an interface between the first electrode and the interlayer insulating film; and forming a second electrode contacting the second semiconductor region and adjacent to the first electrode via the insulating film in the trench.

Abstract: A method of fabricating an integrated circuit on a compound semiconductor III-V wafer including at least two different types of active devices by providing a substrate; growing a first epitaxial structure on the substrate; growing a second epitaxial structure on the first epitaxial structure; and processing the epitaxial structures to form different types of active devices, such as HBTs and FETs.

Abstract: A vertical parasitic PNP device in a SiGe HBT process is disclosed which comprises a collector region, a base region, an emitter region, P-type pseudo buried layers and N-type polysilicons. The pseudo buried layers are formed at bottom of shallow trench field oxide regions around the collector region and contact with the collector region; deep hole contacts are formed on top of the pseudo buried layers to pick up collector electrodes. The N-type polysilicons are formed on top of the base region and are used to pick up base electrodes. The emitter region comprises a P-type SiGe epitaxial layer and a P-type polysilicon both of which are formed on top of the base region. A manufacturing method of a vertical parasitic PNP device in a SiGe HBT process is also disclosed.

Abstract: Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening.

Abstract: A heterojunction bipolar transistor comprising a substrate; a collector on the substrate; a base layer on the collector; an emitter layer on the base layer; the emitter layer comprising an upper emitter layer and a lower emitter layer between the upper emitter layer and base; the collector, base and emitter layers being npn or pnp doped respectively; characterized in that the lower emitter layer has a larger bandgap than the base layer and is AlxIn1-xP or GaxAl1-xP, x being in the range 0+ to 1.

Abstract: A semiconductor device includes a drift layer having a first conductivity type and a body region adjacent the drift layer. The body region has a second conductivity type opposite the first conductivity type and forms a p-n junction with the drift layer. The device further includes a contactor region in the body region and having the first conductivity type, and a shunt channel region extending through the body region from the contactor region to the drift layer. The shunt channel region has the first conductivity type. The device further includes a first terminal in electrical contact with the body region and the contactor region, and a second terminal in electrical contact with the drift layer.

Abstract: An n-layer is arranged above a substrate, which can be GaAs, and a p-layer (4) is arranged on the n-layer. The p-layer is separated by a gate electrode into two separate portions forming source and drain. The gate electrode is insulated from the semiconductor material by a gate dielectric. Source/drain contacts are electrically conductively connected with the portions of the p-layer.

Abstract: The invention relates to a semiconductor device with a substrate (11) and a semiconductor body (12) with a heterojunction bipolar, in particular npn, transistor with an emitter region (1), a base region (2) and a collector region (3), which are provided with, respectively, a first, a second and a third connection conductor (4, 5, 6), and wherein the bandgap of the base region (2) is smaller than that of the collector region (3) or of the emitter region (1), for example by the use of a silicon-germanium mixed crystal instead of pure silicon in the base region (2). Such a device is characterized by a very high speed, but its transistor shows a relatively low BVeeo. In a device (10) according to the invention the doping flux of the emitter region (1) is locally reduced by a further semiconductor region (20) of the second conductivity type which is embedded in the emitter region (1).

Abstract: A semiconductor device includes: a semiconductor substrate; a lateral MOSFET formed in an upper portion of a first region of the semiconductor substrate; a vertical MOSFET formed in a second region of the semiconductor substrate; a backside electrode formed on a lower surface of the semiconductor substrate and connected to a lower region of source/drain regions of the vertical MOSFET; and a connecting member penetrating the semiconductor substrate and connecting one of source/drain regions of the lateral MOSFET to the backside electrode.

Abstract: An integrated pair of HBT and FET transistors shares a common compound semiconductor III-V epitaxial layer. The integrated pair of transistors includes a semi-insulating substrate of a compound semiconductor III-V material, a first epitaxial structure disposed on top of the substrate, a second epitaxial structure on top of the first epitaxial structure, and a third epitaxial structure disposed on top of the second epitaxial structure. The first epitaxial structure forms a portion of the HBT transistor. A concentration profile of a first contaminant, which contributes electrical charge, decreases substantially smoothly across an interface between the semi-insulating substrate and the first epitaxial structure. In some cases, the interface is free of a second contaminant that was present, during formation of the epitaxial structures, in a chamber in which the epitaxial structures were formed.