Vertical Transistors (epo) Patents (Class 257/E29.189)
  • Patent number: 8952441
    Abstract: According to one embodiment, a device includes a first fin structure having first to n-th semiconductor layers (n is a natural number equal to or more than 2) stacked in a first direction perpendicular to a surface of a semiconductor substrate, and extending in a second direction parallel to the surface of the semiconductor substrate, first to n-th memory cells provided on surfaces of the first to n-th semiconductor layers in a third direction perpendicular to the first and second directions respectively, and first to n-th select transistors connected in series to the first to n-th memory cells respectively.
    Type: Grant
    Filed: May 16, 2013
    Date of Patent: February 10, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kiwamu Sakuma, Haruka Kusai, Yasuhito Yoshimizu, Masahiro Kiyotoshi
  • Patent number: 8779492
    Abstract: A semiconductor device includes a first island and a first electrode. The first island includes a first semiconductor region, a first insulation region, and a first insulating film. The first semiconductor region has first and second side surfaces adjacent to the first insulation region and the first insulating film, respectively. The first electrode is adjacent to the first insulation region and the first insulating film. The first insulating film is between the first electrode and the first semiconductor region.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: July 15, 2014
    Assignee: PS4 Luxco S.A.R.L.
    Inventors: Yoshihiro Takaishi, Kazuhiro Nojima
  • Patent number: 8772626
    Abstract: A solar cell may include an electrically conducting substrate, a plurality of nanowhiskers extending from the substrate and a transparent electrode extending over free ends of the nanowhiskers and making electrical contact with them. Each nanowhisker may have a column with a diameter of nanometer dimension. The column may include a first p-doped semiconductor lengthwise segment and a second n-doped semiconductor lengthwise segment. The first and second semiconductor segments may have an interface between them, which forms a p-n junction. The nanowhiskers may be encapsulated in a transparent material.
    Type: Grant
    Filed: December 31, 2007
    Date of Patent: July 8, 2014
    Assignee: QuNano AB
    Inventors: Lars Ivar Samuelson, Bjorn Jonas Ohlsson
  • Patent number: 8692295
    Abstract: A double heterojunction bipolar transistor on a substrate comprises a collector formed of InGaAsP, a base in contact with the collector, an emitter in contact with the base, and electrodes forming separate electrical contacts with each of the collector, base, and emitter, respectively. A device incorporates this transistor and an opto-electronic device optically coupled with the collector of the transistor to interact with light transmitted therethrough.
    Type: Grant
    Filed: September 25, 2009
    Date of Patent: April 8, 2014
    Assignee: HRL Laboratories, LLC
    Inventors: Rajesh D. Rajavel, Stephen Thomas, III
  • Patent number: 8664697
    Abstract: To provide a transistor device, which is composed of a compound semiconductor, having a multilayer structure in which a high electron mobility transistor (HEMT) and a heterojunction bipolar transistor (HBT) are overlapped on the same substrate and epitaxial-grown thereon, wherein a band gap energy of an indium gallium phosphide layer (InGaP) included in an epitaxial layer, is set to 1.91 eV or more.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: March 4, 2014
    Assignee: Hitachi Cable, Ltd.
    Inventors: Takeshi Meguro, Jiro Wada, Yoshihiko Moriya
  • Patent number: 8546874
    Abstract: A semiconductor device includes a drift layer and a body region that forms a p-n junction with the drift layer. A contactor region is in the body region, and a shunt channel region extends through the body region from the contactor region to the drift layer. The shunt channel region has a length, thickness and doping concentration selected such that: 1) the shunt channel region is fully depleted when zero voltage is applied across the first and second terminals, 2) the shunt channel becomes conductive at a voltages less than the built-in potential of the drift layer to body region p-n junction, and/or 3) the shunt channel is not conductive for voltages that reverse bias the p-n junction between the drift region and the body region.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: October 1, 2013
    Assignee: Cree, Inc.
    Inventors: Allen Hefner, Sei-Hyung Ryu, Anant Agarwal
  • Patent number: 8395237
    Abstract: A bipolar transistor includes: a substrate; a collector and a base layer with a p-conductive-type, an emitter layer with an n-conductive-type. The collector layer is formed above the substrate and includes a first nitride semiconductor. The base layer with the p-conductive-type is formed on the collector layer and includes a second nit ride semiconductor. The emitter layer with the n-conductive-type is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed so that crystal growing directions with respect to a surface of the substrate are in parallel to a [0001] direction of the substrate. The first nitride semiconductor includes: InycAlxcGa1-xc-ycN (0?xc?1, 0?yc?1, 0<xc+yc?1). In the first nitride semiconductor, a length of an a-axis on a surface side is longer than a length of an a-axis on a substrate side.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: March 12, 2013
    Assignee: NEC Corporation
    Inventors: Yuji Ando, Hironobu Miyamoto, Tatsuo Nakayama, Yasuhiro Okamoto, Takashi Inoue, Kazuki Ota
  • Patent number: 8395225
    Abstract: A semiconductor device 1 includes: a base 2 mainly formed of a semiconductor material; a gate electrode 5; and a gate insulating film 3 provided between the base 2 and the gate electrode 5. The gate insulating film 3 is formed of an insulative inorganic material containing silicon, oxygen and element X other than silicon and oxygen as a main material. The gate insulating film 3 is provided in contact with the base 2, and contains hydrogen atoms. The gate insulating film 3 has a region where A and B satisfy the relation: B/A is 10 or less in the case where the total concentration of the element X in the region is defined as A and the total concentration of hydrogen in the region is defined as B. Further, the region is at least apart of the gate insulating film 3 in the thickness direction thereof.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: March 12, 2013
    Assignee: Seiko Epson Corporation
    Inventor: Masayasu Miyata
  • Publication number: 20130001647
    Abstract: In an embodiment, a bipolar transistor structure is formed on a silicon-on-insulator (SOI) structure that includes a semiconductor substrate, a buried oxide layer formed on the semiconductor substrate and a top silicon layer formed on the buried oxide layer.
    Type: Application
    Filed: June 28, 2011
    Publication date: January 3, 2013
    Inventor: Steven J. Adler
  • Patent number: 8338863
    Abstract: Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening.
    Type: Grant
    Filed: May 9, 2012
    Date of Patent: December 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Renata Camillo-Castillo, Erik M. Dahlstrom, Qizhi Liu
  • Patent number: 8309409
    Abstract: A semiconductor-device fabrication method includes forming a second semiconductor region of a second conductivity on a surface layer of a first semiconductor region of a first conductivity, the second semiconductor region having an impurity concentration higher than the first semiconductor region; forming a trench penetrating the second semiconductor region, to the first semiconductor region; embedding a first electrode inside the trench via an insulating film, at a height lower than a surface of the second semiconductor region; forming an interlayer insulating film inside the trench, covering the first electrode; leaving the interlayer insulating film on only a surface of the first electrode; removing the second semiconductor region such that the surface thereof is positioned lower than an interface between the first electrode and the interlayer insulating film; and forming a second electrode contacting the second semiconductor region and adjacent to the first electrode via the insulating film in the trench.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: November 13, 2012
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Seiji Momota
  • Patent number: 8309990
    Abstract: A III-V compound semiconductor structure comprises epitaxial structures that include an integrated pair of different types of active devices. The semiconductor structure includes a semi-insulating substrate of a compound semiconductor III-V material and a first compound semiconductor III-V epitaxial structure disposed on the substrate. A concentration profile of dopant material in the semiconductor structure decreases substantially smoothly across an interface between the substrate and the first epitaxial structure in a direction from the first epitaxial structure toward the substrate, and continues to decrease substantially smoothly from the interface with increasing depth into the substrate despite the presence of silicon or oxygen contaminant at the interface. The interface is substantially free of a second contaminant that was present, during formation of the first epitaxial structure, in a chamber in which the first epitaxial structure was formed.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: November 13, 2012
    Assignee: Emcore Corporation
    Inventors: Paul Cooke, Richard W. Hoffman, Jr., Victor Labyuk, Sherry Qianwen Ye
  • Patent number: 8288797
    Abstract: A method of fabricating an integrated circuit on a compound semiconductor III-V wafer including at least two different types of active devices by providing a substrate; growing a first epitaxial structure on the substrate; growing a second epitaxial structure on the first epitaxial structure; and processing the epitaxial structures to form different types of active devices, such as HBTs and FETs.
    Type: Grant
    Filed: December 9, 2010
    Date of Patent: October 16, 2012
    Assignee: Emcore Corporation
    Inventors: Paul Cooke, Richard W. Hoffman, Victor Labyuk, Sherry Qianwen Ye
  • Publication number: 20120181579
    Abstract: A vertical parasitic PNP device in a SiGe HBT process is disclosed which comprises a collector region, a base region, an emitter region, P-type pseudo buried layers and N-type polysilicons. The pseudo buried layers are formed at bottom of shallow trench field oxide regions around the collector region and contact with the collector region; deep hole contacts are formed on top of the pseudo buried layers to pick up collector electrodes. The N-type polysilicons are formed on top of the base region and are used to pick up base electrodes. The emitter region comprises a P-type SiGe epitaxial layer and a P-type polysilicon both of which are formed on top of the base region. A manufacturing method of a vertical parasitic PNP device in a SiGe HBT process is also disclosed.
    Type: Application
    Filed: December 19, 2011
    Publication date: July 19, 2012
    Inventors: Fan Chen, Xiongbin Chen
  • Publication number: 20120112244
    Abstract: Vertical heterojunction bipolar transistors with reduced base-collector junction capacitance, as well as fabrication methods for vertical heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The vertical heterojunction bipolar transistor includes a barrier layer between the intrinsic base and the extrinsic base that blocks or reduces diffusion of a dopant from the extrinsic base to the intrinsic base. The barrier layer has at least one opening that permits direct contact between the intrinsic base and a portion of the extrinsic base disposed in the opening.
    Type: Application
    Filed: November 4, 2010
    Publication date: May 10, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Renata Camillo-Castillo, Erik M. Dahlstrom, Qizhi Liu
  • Patent number: 8101973
    Abstract: A heterojunction bipolar transistor comprising a substrate; a collector on the substrate; a base layer on the collector; an emitter layer on the base layer; the emitter layer comprising an upper emitter layer and a lower emitter layer between the upper emitter layer and base; the collector, base and emitter layers being npn or pnp doped respectively; characterized in that the lower emitter layer has a larger bandgap than the base layer and is AlxIn1-xP or GaxAl1-xP, x being in the range 0+ to 1.
    Type: Grant
    Filed: March 27, 2008
    Date of Patent: January 24, 2012
    Assignee: RFMD (UK) Limited
    Inventors: Matthew Francis O'Keefe, Robert Grey, Michael Charles Clausen, Richard Alun Davies
  • Patent number: 8034688
    Abstract: A semiconductor device includes a drift layer having a first conductivity type and a body region adjacent the drift layer. The body region has a second conductivity type opposite the first conductivity type and forms a p-n junction with the drift layer. The device further includes a contactor region in the body region and having the first conductivity type, and a shunt channel region extending through the body region from the contactor region to the drift layer. The shunt channel region has the first conductivity type. The device further includes a first terminal in electrical contact with the body region and the contactor region, and a second terminal in electrical contact with the drift layer.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: October 11, 2011
    Assignee: Cree, Inc.
    Inventors: Allen Hefner, Sei-Hyung Ryu, Anant Agarwal
  • Publication number: 20110241076
    Abstract: An n-layer is arranged above a substrate, which can be GaAs, and a p-layer (4) is arranged on the n-layer. The p-layer is separated by a gate electrode into two separate portions forming source and drain. The gate electrode is insulated from the semiconductor material by a gate dielectric. Source/drain contacts are electrically conductively connected with the portions of the p-layer.
    Type: Application
    Filed: November 12, 2009
    Publication date: October 6, 2011
    Applicant: EPCOS AG
    Inventor: Léon C. M. van den Oever
  • Patent number: 7989844
    Abstract: The invention relates to a semiconductor device with a substrate (11) and a semiconductor body (12) with a heterojunction bipolar, in particular npn, transistor with an emitter region (1), a base region (2) and a collector region (3), which are provided with, respectively, a first, a second and a third connection conductor (4, 5, 6), and wherein the bandgap of the base region (2) is smaller than that of the collector region (3) or of the emitter region (1), for example by the use of a silicon-germanium mixed crystal instead of pure silicon in the base region (2). Such a device is characterized by a very high speed, but its transistor shows a relatively low BVeeo. In a device (10) according to the invention the doping flux of the emitter region (1) is locally reduced by a further semiconductor region (20) of the second conductivity type which is embedded in the emitter region (1).
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: August 2, 2011
    Assignee: NXP B.V.
    Inventors: Rob Van Dalen, Prabhat Agarwal, Jan Willem Slotboom, Gerrit Elbert Johannes Koops
  • Patent number: 7910984
    Abstract: A semiconductor device includes: a semiconductor substrate; a lateral MOSFET formed in an upper portion of a first region of the semiconductor substrate; a vertical MOSFET formed in a second region of the semiconductor substrate; a backside electrode formed on a lower surface of the semiconductor substrate and connected to a lower region of source/drain regions of the vertical MOSFET; and a connecting member penetrating the semiconductor substrate and connecting one of source/drain regions of the lateral MOSFET to the backside electrode.
    Type: Grant
    Filed: January 16, 2009
    Date of Patent: March 22, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiro Yamaguchi, Yusuke Kawaguchi, Miwako Akiyama
  • Patent number: 7893463
    Abstract: An integrated pair of HBT and FET transistors shares a common compound semiconductor III-V epitaxial layer. The integrated pair of transistors includes a semi-insulating substrate of a compound semiconductor III-V material, a first epitaxial structure disposed on top of the substrate, a second epitaxial structure on top of the first epitaxial structure, and a third epitaxial structure disposed on top of the second epitaxial structure. The first epitaxial structure forms a portion of the HBT transistor. A concentration profile of a first contaminant, which contributes electrical charge, decreases substantially smoothly across an interface between the semi-insulating substrate and the first epitaxial structure. In some cases, the interface is free of a second contaminant that was present, during formation of the epitaxial structures, in a chamber in which the epitaxial structures were formed.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: February 22, 2011
    Assignee: Emcore Corporation
    Inventors: Paul Cooke, Richard W. Hoffman, Jr., Victor Labyuk, Sherry Qianwen Ye
  • Patent number: 7868335
    Abstract: A bipolar junction transistor having an emitter, a base, and a collector includes a stack of one or more layer sets adjacent the collector. Each layer set includes a first material having a first band gap, wherein the first material is highly doped, and a second material having a second band gap narrower than the first band gap, wherein the second material is at most lightly doped.
    Type: Grant
    Filed: August 18, 2008
    Date of Patent: January 11, 2011
    Assignee: HRL Laboratories, LLC
    Inventors: James Chingwei Li, Marko Sokolich, Tahir Hussain, David H. Chow
  • Patent number: 7863174
    Abstract: A vertical pillar transistor may include a plurality of lower pillars, a plurality of upper pillars, a first insulation part, a second insulation part and a word line. The plurality of lower pillars protrudes substantially perpendicular to a substrate and is defined by a plurality of trenches. The plurality of lower pillars extends along a second direction and may be separated from each other along a first direction substantially perpendicular to the second direction. The plurality of upper pillars may be formed on the plurality of lower pillars. The plurality of upper pillars has a width substantially smaller than that of the plurality of lower pillars. The first insulation part has a substantially uniform thickness on a sidewall of each of the plurality of lower pillars. The second insulation part may be formed on the first insulation part to fill a gap between the adjacent upper pillars.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: January 4, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hui-Jung Kim, Yong-Chul Oh, Jae-Man Yoon, Hyun-Woo Chung, Hyun-Gi Kim, Kang-Uk Kim
  • Patent number: 7843004
    Abstract: A trench MOSFET contains a recessed field plate (RFP) trench adjacent the gate trench. The RFP trench contains an RFP electrode insulated from the die by a dielectric layer along the walls of the RFP trench. The gate trench has a thick bottom oxide layer, and the gate and RFP trenches are preferably formed in the same processing step and are of substantially the same depth. When the MOSFET operates in the third quadrant (with the source/body-to-drain junction forward-biased), the combined effect of the RFP and gate electrodes significantly reduces in the minority carrier diffusion current and reverse-recovery charge. The RFP electrode also functions as a recessed field plates to reduce the electric field in the channel regions when the MOSFET source/body to-drain junction reverse-biased.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: November 30, 2010
    Assignee: MaxPower Semiconductor Inc.
    Inventor: Mohamed N. Darwish
  • Patent number: 7842591
    Abstract: A method of fabricating short-gate-length electrodes for integrated III-V compound semiconductor devices, particularly for integrated HBT/HEMT devices on a common substrate is disclosed. The method is based on dual-resist processes, wherein a first thin photo-resist layer is utilized for defining the gate dimension, while a second thicker photo-resist layer is used to obtain a better coverage on the surface for facilitating gate metal lift-off. The dual-resist method not only reduces the final gate length, but also mitigates the gate recess undercuts, as compared with those fabricated by the conventional single-resist processes. Furthermore, the dual-resist method of the present invention is also beneficial for the fabrication of multi-gate device with good gate-length uniformity.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: November 30, 2010
    Assignee: WIN Semiconductors Corp.
    Inventors: Cheng-Kuo Lin, Chia-Liang Chao, Ming-Chang Tu, Tsung-Chi Tsai, Yu-Chi Wang
  • Patent number: 7842973
    Abstract: A semiconductor device capable of avoiding generation of a barrier in a conduction band while maintaining high withstanding voltage and enabling high speed transistor operation at high current in a double hetero bipolar transistor, as well as a manufacturing method thereof, wherein a portion of the base and the collector is formed of a material with a forbidden band width narrower than that of a semiconductor substrate, a region where the forbidden band increases stepwise and continuously from the emitter side to the collector side is disposed in the inside of the base and the forbidden band width at the base-collector interface is designed so as to be larger than the minimum forbidden band width in the base, whereby the forbidden band width at the base layer edge on the collector side can be made closer to the forbidden band width of the semiconductor substrate than usual while sufficiently maintaining the hetero effect near the emitter-base thereby capable of decreasing the height of the energy barrier gene
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: November 30, 2010
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Miura, Katsuyoshi Washio, Hiromi Shimamoto
  • Patent number: 7821037
    Abstract: A heterojunction bipolar transistor includes a first conductivity type subcollector layer, a first collector layer containing a first conductivity type impurity, a third collector layer containing a higher concentration of the first conductivity type impurity than the first collector layer, a second collector layer containing a lower concentration of the first conductivity type impurity than the first collector layer, a second conductivity type base layer, a first conductivity type emitter layer containing a semiconductor with a wider bandgap than the base layer, and a first conductivity type emitter cap layer.
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: October 26, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Takaki Niwa, Naoto Kurosawa
  • Patent number: 7709889
    Abstract: The present invention provides a semiconductor device (20) comprising a trench (5) formed in a semiconductor substrate formed of a stack (4) of layers (1,2,3), a layer (6) of a first, grown dielectric material covering sidewalls and bottom of the trench (5), the layer (6) including one or more notches (13) at the bottom of the trench (5) and one or more spacers (14) formed of a second, deposited dielectric material to fill the one or more notches (13) in the layer (6) formed of the first, grown dielectric material. The semiconductor device (20) according to the present invention shows improved breakdown voltage and on-resistance. The present invention furthermore provides a method for the manufacturing of such semiconductor devices (20).
    Type: Grant
    Filed: July 26, 2007
    Date of Patent: May 4, 2010
    Assignee: Semiconductor Components Industries, L.L.C.
    Inventors: Peter Moens, Filip Bauwens, Joris Baele, Marnix Tack
  • Patent number: 7670911
    Abstract: A method for manufacturing a vertical MOS transistor comprising forming a protrusion-like region, forming a silicon oxide film on an exposed surface of the protrusion-like region and a surface of the silicon semiconductor substrate, increasing a film thickness of at least the silicon oxide film on the silicon semiconductor substrate by thermal oxidation to form a first insulating film, forming a lower impurity diffusion region, removing the silicon oxide film to expose a silicon side of the protrusion-like region, thermally oxidizing the silicon side to form a second insulating film having a thinner film thickness than a film thickness of the first insulating film, forming a gate electrode over a side of the protrusion-like region, and forming an upper impurity diffusion region.
    Type: Grant
    Filed: July 31, 2008
    Date of Patent: March 2, 2010
    Assignee: Elpida Memory, Inc.
    Inventor: Kiyonori Oyu
  • Publication number: 20090321788
    Abstract: High frequency performance of (e.g., silicon) bipolar devices (40, 100, 100?) is improved by reducing the capacitive coupling (Cbc) between the extrinsic base contact (46) and the collector (44, 44?, 44?). A dielectric ledge (453, 453?) is created during fabrication to separate the extrinsic base contract (46) from the collector (44, 44?, 44?) periphery (441). The dielectric ledge (453, 453?) underlies the transition region (461) where the extrinsic base contact (46) is coupled to the intrinsic base. (472) During device fabrication, a multi layer dielectric stack (45) is formed adjacent the intrinsic base (472) that allows the simultaneous creation of an undercut region (457, 457?) in which the intrinsic base (472) to extrinsic base contact (46) transition region (461) can be formed.
    Type: Application
    Filed: June 26, 2008
    Publication date: December 31, 2009
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jay P. John, James A. Kirchgessner
  • Patent number: 7598567
    Abstract: A semiconductor device includes a drift layer having a first conductivity type and a body region adjacent the drift layer. The body region has a second conductivity type opposite the first conductivity type and forms a p-n junction with the drift layer. The device further includes a contactor region in the body region and having the first conductivity type, and a shunt channel region extending through the body region from the contactor region to the drift layer. The shunt channel region has the first conductivity type. The device further includes a first terminal in electrical contact with the body region and the contactor region, and a second terminal in electrical contact with the drift layer.
    Type: Grant
    Filed: November 3, 2006
    Date of Patent: October 6, 2009
    Assignee: Cree, Inc.
    Inventors: Allen Hefner, Sei-Hyung Ryu, Anant Agarwal
  • Patent number: 7586130
    Abstract: A vertical field effect transistor includes: an active region with a bundle of linear structures functioning as a channel region; a lower electrode, functioning as one of source and drain regions; an upper electrode, functioning as the other of the source and drain regions; a gate electrode for controlling the electric conductivity of at least a portion of the bundle of linear structures included in the active region; and a gate insulating film arranged between the active region and the gate electrode to electrically isolate the gate electrode from the bundle of linear structures. The transistor further includes a dielectric portion between the upper and lower electrodes. The upper electrode is located over the lower electrode with the dielectric portion interposed and includes an overhanging portion sticking out laterally from over the dielectric portion. The active region is located right under the overhanging portion of the upper electrode.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: September 8, 2009
    Assignee: Panasonic Corporation
    Inventors: Takahiro Kawashima, Tohru Saitoh, Takeshi Takagi
  • Publication number: 20090179228
    Abstract: Disclosed are embodiments of a hetero-junction bipolar transistor (HBT) structure and method of forming the structure that provides substantially lower collector-to-base parasitic capacitance and collector resistance, while also lowering or maintaining base-to-emitter capacitance, emitter resistance and base resistance in order to achieve frequency capabilities in the THz range. The HBT is a collector-up HBT in which a dielectric layer and optional sidewall spacers separate the raised extrinsic base and the collector so as to reduce collector-to-base capacitance. A lower portion of the collector is single crystalline semiconductor so as to reduce collector resistance. The raised extrinsic base and the intrinsic base are stacked single crystalline epitaxial layers, where link-up is automatic and self-aligned, so as to reduce base resistance. The emitter is a heavily doped region below the top surface of a single crystalline semiconductor substrate so as to reduce emitter resistance.
    Type: Application
    Filed: January 14, 2008
    Publication date: July 16, 2009
    Inventors: Alvin J. Joseph, Andreas D. Stricker
  • Publication number: 20090173970
    Abstract: A method of fabricating a hetero-junction bipolar transistor (HBT) is disclosed, where the HBT has a structure incorporating a hetero-junction bipolar structure disposed on a substrate including of silicon crystalline orientation <110>. The hetero-junction bipolar structure may include an emitter, a base and a collector. The substrate may include a shallow-trench-isolation (STI) region and a deep trench region on which the collector is disposed. The substrate may include of a region of silicon crystalline orientation <100> in addition to silicon crystalline orientation <110> to form a composite substrate by using hybrid orientation technology (HOT). The region of crystalline orientation <100> may be disposed on crystalline orientation <110>. Alternatively, the region of silicon crystalline orientation <110> may be disposed on crystalline orientation <100>.
    Type: Application
    Filed: January 4, 2008
    Publication date: July 9, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Thomas N. Adam, Rajendran Krishnasamy
  • Publication number: 20090166747
    Abstract: Semiconductor devices and fabrication methods are provided, in which metal transistor gates are provided for MOS transistors. A rare earth-rare earth alloy incorporated metal nitride layer is formed above a gate dielectric. This process provides adjustment of the gate electrode work function, thereby tuning the threshold voltage of the resulting NMOS transistors.
    Type: Application
    Filed: September 8, 2008
    Publication date: July 2, 2009
    Applicant: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, Manuel Angel Quevedo-Lopez
  • Publication number: 20090039385
    Abstract: A device comprises a first sub-collector formed in an upper portion of a substrate and a lower portion of a first epitaxial layer and a second sub-collector formed in an upper portion of the first epitaxial layer and a lower portion of a second epitaxial layer. The device further comprises a reach-through structure connecting the first and second sub-collectors and an N-well formed in a portion of the second epitaxial layer and in contact with the second sub-collector and the reach-through structure. The device further comprises N+ diffusion regions in contact with the N-well, a P+ diffusion region in contact with the N-well, and shallow trench isolation structures between the N+ and P+ diffusion regions.
    Type: Application
    Filed: September 24, 2008
    Publication date: February 12, 2009
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Xuefeng LIU, Robert M. Rassel, Steven H. Voldman
  • Patent number: 7482643
    Abstract: A semiconductor device is provided. In one example, a semiconductor device has a D-HBT structure which include a base layer formed from InGaAs and an emitter layer and a collector layer both formed from InGaP in such a way as to hold said base layer between them, wherein said InGaAs has a composition such that the content of In is smaller than 53% and said InGaP has a composition such that the content of In is just enough to make the lattice constant of said emitter layer and collector layer equal to the lattice constant of said base layer. This semiconductor device realizes a large current gain while keeping the high-speed operation owing to the base layer of InGaAs having good carrier mobility. In addition, it can be formed on a large wafer as the substrate.
    Type: Grant
    Filed: January 20, 2006
    Date of Patent: January 27, 2009
    Assignee: Sony Corporation
    Inventor: Ken Sawada
  • Patent number: 7462892
    Abstract: A semiconductor device includes an emitter layer: a base layer; and a collector layer, wherein the collector layer and the emitter layer each include a heavily doped thin sublayer having a high impurity concentration, and each of the heavily doped thin sublayers has an impurity concentration higher than those of semiconductor layers adjacent to each heavily doped thin sublayer.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: December 9, 2008
    Assignee: Sony Corporation
    Inventors: Ichiro Hase, Ken Sawada, Masaya Uemura
  • Publication number: 20080265283
    Abstract: A hetero-junction bipolar transistor includes a sub-collector layer formed on a substrate and having conductivity, a first collector layer formed on the sub-collector layer and a second collector layer formed on the first collector layer and having the same conductive type as a conductive type of the sub-collector layer. In the first collector layer, a delta-doped layer is provided.
    Type: Application
    Filed: June 25, 2008
    Publication date: October 30, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Masanobu Nogome
  • Publication number: 20080237643
    Abstract: A heterojunction bipolar transistor comprising a substrate; a collector on the substrate; a base layer on the collector; an emitter layer on the base layer; the emitter layer comprising an upper emitter layer and a lower emitter layer between the upper emitter layer and base; the collector, base and emitter layers being npn or pnp doped respectively; characterised in that the lower emitter layer has a larger bandgap than the base layer and is AlxIn1-xP or GaxAl1-xP, x being in the range 0+ to 1.
    Type: Application
    Filed: March 27, 2008
    Publication date: October 2, 2008
    Applicant: FITRONIC COMPOUND SEMICONDUCTORS LIMITED
    Inventors: Matthew Francis O'Keefe, Robert Grey, Michael Charles Clausen, Richard Alun Davies
  • Publication number: 20080224175
    Abstract: Semiconductor device structures for use with bipolar junction transistors and methods of fabricating such semiconductor device structures. The semiconductor device structure includes a semiconductor body having a top surface and sidewalls extending from the top surface to an insulating layer, a first region including a first semiconductor material with a first conductivity type, and a second region including a second semiconductor material with a second conductivity type. The first and second regions each extend across the top surface and the sidewalls of the semiconductor body. The device structure further includes a junction defined between the first and second regions and extending across the top surface and the sidewalls of the semiconductor body.
    Type: Application
    Filed: May 30, 2008
    Publication date: September 18, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Louis Lu-Chen Hsu, Jack Allan Mandelman
  • Publication number: 20080179632
    Abstract: Bipolar transistors and methods of forming the bipolar transistors. The method including forming a P-type collector in a silicon substrate; forming an intrinsic base on the collector, the intrinsic base including a first N-type dopant species, germanium and carbon; forming an N-type extrinsic base over a first region and a second region of the intrinsic base, the first region over the collector and the second region over a dielectric adjacent to the collector, the N-type extrinsic base containing or not containing carbon; and forming a P-type emitter on the first region of the intrinsic base.
    Type: Application
    Filed: April 1, 2008
    Publication date: July 31, 2008
    Inventors: Thomas N. Adam, Rajendran Krishnasamy
  • Publication number: 20080116489
    Abstract: A heterojunction bipolar transistor includes a first conductivity type subcollector layer, a first collector layer containing a first conductivity type impurity, a third collector layer containing a higher concentration of the first conductivity type impurity than the first collector layer, a second collector layer containing a lower concentration of the first conductivity type impurity than the first collector layer, a second conductivity type base layer, a first conductivity type emitter layer containing a semiconductor with a wider bandgap than the base layer, and a first conductivity type emitter cap layer.
    Type: Application
    Filed: November 16, 2007
    Publication date: May 22, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Takaki Niwa, Naoto Kurosawa
  • Patent number: 7345327
    Abstract: A semiconductor material which has a high carbon dopant concentration includes gallium, indium, arsenic and nitrogen. The disclosed semiconductor materials have a low sheet resistivity because of the high carbon dopant concentrations obtained. The material can be the base layer of gallium arsenide-based heterojunction bipolar transistors and can be lattice-matched to gallium arsenide emitter and/or collector layers by controlling concentrations of indium and nitrogen in the base layer. The base layer can have a graded band gap that is formed by changing the flow rates during deposition of III and V additive elements employed to reduce band gap relative to different III-V elements that represent the bulk of the layer. The flow rates of the III and V additive elements maintain an essentially constant doping-mobility product value during deposition and can be regulated to obtain pre-selected base-emitter voltages at junctions within a resulting transistor.
    Type: Grant
    Filed: October 20, 2004
    Date of Patent: March 18, 2008
    Assignee: Kopin Corporation
    Inventors: Roger E. Welser, Paul M. DeLuca, Charles R. Lutz, Kevin S. Stevens, Noren Pan
  • Patent number: 7297993
    Abstract: A bipolar transistor having a base electrode of an air bridge structure is simplified in structure and enhanced in the degree of freedom of a contact position of a base wiring line with the base electrode. The bipolar transistor has a semiconductor mesa portion having a base layer formed on an upper face thereof, and a base electrode contacts with the base layer and has a floating extension which extends from the semiconductor mesa portion to a space on the outer side with respect to the semiconductor mesa portion. The floating extension is used as a contact portion for a base wiring line to the base electrode.
    Type: Grant
    Filed: July 12, 2005
    Date of Patent: November 20, 2007
    Assignee: Sony Corporation
    Inventor: Junichiro Kobayashi
  • Patent number: 7282753
    Abstract: The Invention Is A Method For Making Power Device On A Semiconductor Wafer, Where The Backside Of The Wafer Has Been Thinned In Selected Regions To A Thickness Of About 25 Um By Reactive Ion Etching.
    Type: Grant
    Filed: September 22, 2006
    Date of Patent: October 16, 2007
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Karl D. Hobart
  • Patent number: 7276754
    Abstract: A memory structure having a vertically oriented access transistor with an annular gate region and a method for fabricating the structure. More specifically, a transistor is fabricated such that the channel of the transistor extends outward with respect to the surface of the substrate. An annular gate is fabricated around the vertical channel such that it partially or completely surrounds the channel. A buried annular bitline may also be implemented. After the vertically oriented transistor is fabricated with the annular gate, a storage device may be fabricated over the transistor to provide a memory cell.
    Type: Grant
    Filed: August 4, 2005
    Date of Patent: October 2, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Lucien J. Bissey, Kevin G. Duesman
  • Patent number: 7091553
    Abstract: A process and intermediate DRAM structure formed by providing a substrate having an array of trenches containing trench capacitors underlying vertical transistors in an array area separated by isolation trenches residing in both array and support areas. A top oxide nitride (TON) liner is deposited over array and support areas so as to directly contact the fill in the isolation trenches. An array top oxide (ATO) is then deposited directly over the TON liner such that during subsequent processing, the TON protects the isolation trench oxide from any divot opening etches while maintaining the isolation trench oxide height fixed during the ATO process. In further processing the intermediate structure, ATO and TON are removed from the support area only, leaving remaining portions of both ATO and TON only in the array area, such that the TON liner separates the ATO from the isolation trench fill.
    Type: Grant
    Filed: April 19, 2005
    Date of Patent: August 15, 2006
    Assignees: International Business Machines Corporation, Infineon Technologies North America Corp.
    Inventors: Ramachandra Divakaruni, Klaus Hummler