Hetero-junction Transistor (epo) Patents (Class 257/E29.188)
  • Patent number: 9012958
    Abstract: A semiconductor device of the invention includes an n-GaN layer provided on a substrate, a channel layer provided in contact with the upper surface of the n-GaN layer, an electron supply layer which is provided on the channel layer, and a gate electrode, a source electrode, and a drain electrode which are provided on the electron supply layer. The gate electrode is in contact with an underlying layer made from a nitride semiconductor. The semiconductor device has a ratio defined by the equation L/d1?7, where L is the width of the gate electrode in contact with the underlying layer in a direction between the source electrode and drain electrode; and d1 is the distance between a surface of the n-type gallium nitride layer and a boundary between the gate electrode and the underlying layer.
    Type: Grant
    Filed: April 17, 2014
    Date of Patent: April 21, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventor: Kazutaka Inoue
  • Patent number: 8994075
    Abstract: A heterojunction bipolar transistor includes a base mesa, an emitter assembly formed over the base mesa, and a base contact. The emitter assembly includes multiple circular sectors. Each circular sector is spaced apart from one another such that a sector gap is formed between radial sides of adjacent circular sectors. The base contact, which is formed over the base mesa, has a central portion and multiple radial members. Each radial member extends outward from the central portion of the base contact along a corresponding sector gap. As such, each of the circular sectors of the emitter assembly is separated by a radial member of the base contact. The number of circular sectors may vary from one embodiment to another. For example, the emitter assembly may have three, four, six, or more circular sectors.
    Type: Grant
    Filed: October 11, 2013
    Date of Patent: March 31, 2015
    Assignee: RF Micro Devices, Inc.
    Inventors: Brian G. Moser, Robert Saxer, Jing Zhang
  • Patent number: 8987785
    Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor includes a base situated on a substrate. The heterojunction bipolar transistor can be an NPN silicon-germanium heterojunction bipolar transistor, for example. The heterojunction bipolar transistor further includes a cap layer situated on the base, where the cap layer includes a barrier region. The barrier region can comprises carbon and has a thickness, where the thickness of the barrier region determines a depth of an emitter-junction of the heterojunction bipolar transistor. An increase in the thickness of the barrier region can cause a decrease in the depth of the emitter-base junction. According to this exemplary embodiment, the heterojunction bipolar transistor further includes an emitter situated over the cap layer, where the emitter comprises an emitter dopant, which can be phosphorus. A diffusion retardant in the barrier region of the cap layer impedes diffusion of the emitter dopant.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: March 24, 2015
    Assignee: Newport Fab, LLC
    Inventor: Greg D. U'ren
  • Patent number: 8946861
    Abstract: Disclosed are bipolar devices, which incorporate an entirely monocrystalline link-up region between the intrinsic and extrinsic base layers, and methods of forming the devices. In the methods, a selective epitaxial deposition process grows monocrystalline semiconductor material for the extrinsic base layer on an exposed edge portion of a monocrystalline section of an intrinsic base layer. This deposition process is continued to intentionally overgrow the monocrystalline semiconductor material until it grows laterally and essentially covers a dielectric landing pad on a center portion of that same monocrystalline section of the intrinsic base layer. Subsequently, an opening is formed through the extrinsic base layer to the dielectric landing pad and the dielectric landing pad is selectively removed, thereby exposing monocrystalline surfaces only of the intrinsic and extrinsic base layers.
    Type: Grant
    Filed: June 11, 2013
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Renata A. Camillo-Castillo, Vibhor Jain, Vikas K. Kaushal, Marwan H. Khater
  • Patent number: 8878244
    Abstract: Gases for film formation are introduced from a plurality of holes provided at a gas nozzle into a processing chamber of a batch-type CVD film-forming apparatus to cause a turbulence of the gases within the processing chamber. In the state where the chamber is kept at a pressure within an atmospheric and quasi-atmospheric pressure region, a silicon-germanium film is epitaxially grown on a semiconductor wafer placed within the processing chamber. Subsequently, a strained silicon film is epitaxially grown on the silicon-germanium film. Thereafter, a semiconductor element is formed in the semiconductor wafer on which the silicon-germanium film and the strained silicon film have been formed, respectively.
    Type: Grant
    Filed: January 3, 2008
    Date of Patent: November 4, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuichi Kondo, Wataru Hirasawa, Nobuyuki Sugii
  • Patent number: 8878250
    Abstract: Electronic device is provided, including: a base wafer whose surface is made of silicon crystal; a Group 3-5 compound semiconductor crystal formed directly or indirectly on partial region of the silicon crystal; an electronic element including a portion of the Group 3-5 compound semiconductor crystal as active layer; an insulating film formed directly or indirectly on the base wafer and covering the electronic element; an electrode formed directly or indirectly on the insulating film; a first coupling wiring extending through the insulating film, having at least a portion thereof formed directly or indirectly on the insulating film, and electrically coupling the electronic element with the electrode; a passive element formed directly or indirectly on the insulating film; a second coupling wiring extending through the insulating film, having at least a portion thereof formed directly or indirectly on the insulating film, and electrically coupling the electronic element with the passive element.
    Type: Grant
    Filed: August 24, 2012
    Date of Patent: November 4, 2014
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Masahiko Hata, Sadanori Yamanaka, Tomoyuki Takada, Kazuhiko Honjo
  • Patent number: 8816400
    Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) having a deep pseudo buried layer is disclosed. The SiGe HBT includes isolation structures formed in trenches, first pseudo buried layers and second pseudo buried layers, and a collector region. The first pseudo buried layers are formed under the respective trenches and the second pseudo buried layers are formed under the first pseudo buried layers, with each first pseudo buried layer vertically contacting with a second pseudo buried layer. The second pseudo buried layers are laterally connected to each other, and the collector region is surrounded by the trenches, the first pseudo buried layers and the second pseudo buried layers. The cross section of each of the trenches has a regular trapezoidal shape, namely, each trench's width of its top is smaller than that of its bottom. A manufacturing method of the SiGe HBT is also disclosed.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: August 26, 2014
    Assignee: Shanghai Hua Hong Nec Electronics Co., Ltd.
    Inventor: Wensheng Qian
  • Patent number: 8742538
    Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, which includes: two isolation structures each being formed in a trench; a set of three or more pseudo buried layers formed under each trench with every adjacent two pseudo buried layers of the set being vertically contacted with each other; and a collector region. In this design, the lowermost pseudo buried layers of the two sets are laterally in contact with each other, and the collector region is surrounded by the two isolation structures and the two sets of pseudo buried layers. As the breakdown voltage of a SiGe HBT according to the present invention is determined by the distance between an uppermost pseudo buried layer and the edge of an active region, SiGe HBTs having different breakdown voltages can be achieved. A manufacturing method of the SiGe HBT is also disclosed.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: June 3, 2014
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventor: Wensheng Qian
  • Publication number: 20140124838
    Abstract: A high-speed SiGe HBT is disclosed, which includes: a substrate; STIs formed in the substrate; a collector region formed beneath the substrate surface and located between the STIs; an epitaxial dielectric layer including two portions, one being located on the collector region, the other being located on one of the STIs; a base region formed both in a region between and on surfaces of the two portions of the epitaxial dielectric layer; an emitter dielectric layer including two portions, both portions being formed on the base region; an emitter region formed both in a region between and on surfaces of the two portions of the emitter dielectric layer; a contact hole formed on a surface of each of the base region, the emitter region and the collector region. A method of manufacturing high-speed SiGe HBT is also disclosed.
    Type: Application
    Filed: November 8, 2012
    Publication date: May 8, 2014
    Applicant: SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD.
    Inventors: Donghua Liu, Wenting Duan, Wensheng Qian, Jun Hu, Jing Shi
  • Patent number: 8716836
    Abstract: A high-quality GaAs-type crystal thin film using an inexpensive Si wafer with good thermal release characteristics is achieved. Provided is a semiconductor wafer comprising an Si wafer; an inhibiting layer that is formed on the wafer and that inhibits crystal growth, the inhibiting layer including a covering region that covers a portion of the wafer and an open region that does not cover a portion of the wafer within the covering region; a Ge layer that is crystal-grown in the open region; and a functional layer that is crystal-grown on the Ge layer. The Ge layer may be formed by annealing with a temperature and duration that enables movement of crystal defects, and the annealing is repeated a plurality of times.
    Type: Grant
    Filed: December 26, 2008
    Date of Patent: May 6, 2014
    Assignees: Sumitomo Chemical Company, Limited, The University of Tokyo
    Inventors: Tomoyuki Takada, Sadanori Yamanaka, Masahiko Hata, Taketsugu Yamamoto, Kazumi Wada
  • Publication number: 20140110761
    Abstract: A semiconductor device having a tunable capacitance is disclosed, comprising a substrate, a semiconductor base layer comprising a first semiconductor material having a first band-gap, and a plurality of successive semiconductor layers positioned between the substrate and the semiconductor base layer. The plurality of successive semiconductor layers includes a tuning layer comprising a second semiconductor material having a second band-gap larger than the first band-gap. Furthermore, the tuning layer has a non-uniform doping profile with doping concentration that varies in accordance with distance from a surface of the tuning layer proximal to the semiconductor base layer. The tunable capacitance of the semiconductor device varies in accordance with an applied voltage between the base layer and one of the successive semiconductor layers.
    Type: Application
    Filed: October 31, 2012
    Publication date: April 24, 2014
    Inventors: Yuefei Yang, Shing-Kuo Wang
  • Publication number: 20140054608
    Abstract: A compound semiconductor integrated circuit is provided, comprising a substrate, at least one compound semiconductor electronic device, a first metal layer, a protection layer, a plurality of second metal layers, and at least one dielectric layer. The first metal layer contains Au but does not contain Cu, and is at least partly electrically connected to the compound semiconductor electronic device. The protection layer covers the compound semiconductor electronic device and at least part of the first metal layer. Each of the plurality of second metal layers contains at least a Cu layer, and at least one of the plurality of second metal layers is partly electrically connected to the first metal layer described above. The at least one dielectric layer separates each pair of adjacent second metal layers. The second metal layers are used to form passive electronic components.
    Type: Application
    Filed: August 24, 2012
    Publication date: February 27, 2014
    Applicant: WIN SEMICONDUCTORS CORP.
    Inventors: Shinichiro TAKATANI, Hsien-Fu HSIAO, Yu-Kai WU
  • Publication number: 20130341681
    Abstract: A heterojunction bipolar transistor (HBT) with improved current gain and the fabrication method thereof, in which the HBT comprises a substrate, a p-type buffer layer, a sub-collector layer, a collector layer, a base layer, an emitter layer, an emitter cap layer, and an emitter contact layer. Multiple etching processes are used for etching a base electrode contact region and terminated at the base layer. A collector electrode contact region is then formed in the base electrode contact region by an etching process terminated at the sub-collector layer. A base electrode is disposed on the base layer in the base electrode contact region. A collector electrode is disposed on the sub-collector layer in the collector electrode contact region. An emitter electrode is disposed on the emitter layer.
    Type: Application
    Filed: June 22, 2012
    Publication date: December 26, 2013
    Inventors: H.P. XIAO, Galen HSIEH
  • Publication number: 20130313614
    Abstract: The present invention discloses a metal silicide self-aligned SiGe heterojunction bipolar transistor, which is designed to overcome the shortcomings such as the large base resistance RB of the prior art products. The metal silicide self-aligned SiGe heterojunction bipolar transistor of the present invention mainly comprises an Si collector region, a local dielectric region, a base region, a base-region low-resistance metal silicide layer, a polysilicon emitter region, an emitter-base spacer dielectric region composed of a liner silicon oxide layer and a silicon nitride inner sidewall, a monocrystalline emitter region, a contact hole dielectric layer, an emitter metal electrode and a base metal electrode. The base-region low-resistance metal silicide layer extends all the way to the outside of the emitter-base spacer dielectric region. The present invention discloses a method of forming a metal silicide self-aligned SiGe heterojunction bipolar transistor, which is used to form the aforesaid bipolar transistor.
    Type: Application
    Filed: September 24, 2012
    Publication date: November 28, 2013
    Applicant: TSINGHUA UNIVERSITY
    Inventors: Jun Fu, Yu-dong Wang, Wei Zhang, Gao-qing Li, Zheng-li Wu, Jie Cui, Yue Zhao, Zhi-hong Liu
  • Patent number: 8592870
    Abstract: The present invention discloses a pseudo buried layer, a deep hole contact and a bipolar transistor, and also discloses a manufacturing method of a pseudo buried layer, including: etching a silicon substrate to form an active region and shallow trenches; sequentially implanting phosphorous ion and arsenic ion into the bottom of the shallow trenches to form phosphorus impurity regions and arsenic impurity regions; conducting thermal annealing to the phosphorus impurity regions and arsenic impurity regions. The implantation of the pseudo buried layer, adopting phosphorous with rapid thermal diffusion and arsenic with slow thermal diffusion, can improve the impurity concentration on the surface of the pseudo buried layers, reduce the sheet resistance of the pseudo buried layer, form a good ohmic contact between the pseudo buried layer and a deep hole and reduce the contact resistance, and improve the frequency characteristic and current output of triode devices.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: November 26, 2013
    Assignee: Shanghai Hua Hong NEC Electronics Co., Ltd.
    Inventors: Donghua Liu, Wensheng Qian
  • Publication number: 20130285120
    Abstract: This disclosure relates to bipolar transistors, such as heterojunction bipolar transistors, having at least one grading in the collector. One aspect of this disclosure is a bipolar transistor that includes a collector having a high doping concentration at a junction with the base and at least one grading in which doping concentration increases away from the base. In some embodiments, the high doping concentration can be at least about 3×1016 cm?3. According to certain embodiments, the collector includes two gradings. Such bipolar transistors can be implemented, for example, in power amplifiers.
    Type: Application
    Filed: April 30, 2012
    Publication date: October 31, 2013
    Applicant: Skyworks Solutions, Inc.
    Inventor: Peter J. Zampardi, JR.
  • Publication number: 20130256758
    Abstract: A method of forming an integrated circuit structure includes: forming a vent via extending through a shallow trench isolation (STI) and into a substrate; selectively removing an exposed portion of the substrate at a bottom of the vent via to form an opening within the substrate, wherein the opening within the substrate abuts at least one of a bottom surface or a sidewall of the STI; and sealing the vent via to form an air gap in the opening within the substrate.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Renata A. Camillo-Castillo, James S. Dunn, David L. Harame, Anthony K. Stamper
  • Publication number: 20130256756
    Abstract: An integrated circuit is provided. The integrated circuit may include, but is not limited to, a plurality of heterojunction bipolar transistors, wherein each heterojunction bipolar transistor is staggered with respect to any adjacent heterojunction bipolar transistor. The plurality of heterojunction bipolar transistors may be arranged in a column, wherein each heterojunction bipolar transistor is staggered in the column with respect to any adjacent heterojunction bipolar transistor in the column in a first direction and a second direction, wherein the second direction is substantially orthogonal to the first direction.
    Type: Application
    Filed: March 27, 2012
    Publication date: October 3, 2013
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventor: Yun Wei
  • Publication number: 20130256757
    Abstract: A lateral heterojunction bipolar transistor is formed on a semiconductor-on-insulator substrate including a top semiconductor portion of a first semiconductor material having a first band gap and a doping of a first conductivity type. A stack of an extrinsic base and a base cap is formed such that the stack straddles over the top semiconductor portion. A dielectric spacer is formed around the stack. Ion implantation of dopants of a second conductivity type is performed to dope regions of the top semiconductor portion that are not masked by the stack and the dielectric spacer, thereby forming an emitter region and a collector region. A second semiconductor material having a second band gap greater than the first band gap and having a doping of the second conductivity type is selectively deposited on the emitter region and the collector region to form an emitter contact region and a collector contact region, respectively.
    Type: Application
    Filed: March 29, 2012
    Publication date: October 3, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jin Cai, Kevin K. Chan, Christopher P. D'Emic, Tak H. Ning, Dae-Gyu Park
  • Publication number: 20130248935
    Abstract: A pnp SiGe heterojunction bipolar transistor (HBT) reduces the rate that p-type dopant atoms in the p+ emitter of the transistor out diffuse into a lowly-doped region of the base of the transistor by epitaxially growing the emitter to include a single-crystal germanium region and an overlying single-crystal silicon region.
    Type: Application
    Filed: March 23, 2012
    Publication date: September 26, 2013
    Inventors: Jeffrey A. Babcock, Alexei Sadovnikov
  • Publication number: 20130234209
    Abstract: A switching device for heterojunction integrated circuits is disclosed. According to one aspect, the switching device is configured to protect a circuit from an electro-static discharge (ESD) event. The switching device includes a second base contact region that is configured to be electrically floating, a first base contact region and a collector contact region that are coupled to a first input terminal of the switching device, and an emitter contact region that is coupled to a second input terminal of the switching device. Due in part to capacitive coupling between the first base contact region and the second base contact region, the switching device exhibits a low transient trigger voltage and a fast response to ESD events. Further, the switching device exhibits a high DC trigger voltage (for example, greater than 20V), while maintaining relatively low leakage current during operation (for example, less than about 0.5 ?A at 20V DC.
    Type: Application
    Filed: March 9, 2012
    Publication date: September 12, 2013
    Applicant: ANALOG DEVICES, INC.
    Inventors: Srivatsan Parthasarathy, Javier A. Salcedo, Shuyun Zhang
  • Patent number: 8519443
    Abstract: The invention concerns a heterojunction bipolar transistor comprising a support, and epitaxially grown from said support, at least: one collecting, respectively emitting, layer; at least one base layer; and at least one emitting, respectively collecting, layer. The collecting, respectively emitting, layer comprises: at least one first undercoat contacted with said base layer, substantially of similar composition as said emitting, respectively collecting, layer; and at least one second undercoat on the side opposite said base layer relative to said first undercoat.
    Type: Grant
    Filed: July 18, 2006
    Date of Patent: August 27, 2013
    Assignees: Centre National de la Recherche Scientifique-CNRS, S.O.I. Tec Silicon on Insulator Technologies
    Inventors: Jean-Luc Pelouard, Melania Lijadi, Christophe Dupuis, Fabrice Pardo, Philippe Bove
  • Publication number: 20130214275
    Abstract: Disclosed are a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a narrow in-substrate collector region for reduced base-collector junction capacitance. The transistor has, within a substrate, a collector region positioned laterally adjacent to a trench isolation region. A relatively thin seed layer covers the trench isolation region and collector region. This seed layer has a monocrystalline center, which is aligned above and wider than the collector region (e.g., due to a solid phase epitaxy regrowth process), and a polycrystalline outer section. An intrinsic base layer is epitaxially deposited on the seed layer such that it similarly has a monocrystalline center section that is aligned above and wider than the collector region. An extrinsic base layer is the intrinsic base layer and has a monocrystalline extrinsic base-to-intrinsic base link-up region that is offset vertically from the collector region.
    Type: Application
    Filed: February 21, 2012
    Publication date: August 22, 2013
    Applicant: International Business Machines Corporation
    Inventors: James W. Adkisson, David L. Harame, Qizhi Liu
  • Publication number: 20130187198
    Abstract: A heterojunction bipolar transistor (HBT) structure, method of manufacturing the same and design structure thereof are provided. The HBT structure includes a semiconductor substrate having a sub-collector region therein. The HBT structure further includes a collector region overlying a portion of the sub-collector region. The HBT structure further includes an intrinsic base layer overlying at least a portion of the collector region. The HBT structure further includes an extrinsic base layer adjacent to and electrically connected to the intrinsic base layer. The HBT structure further includes an isolation region extending vertically between the extrinsic base layer and the sub-collector region. The HBT structure further includes an emitter overlying a portion of the intrinsic base layer. The HBT structure further includes a collector contact electrically connected to the sub-collector region. The collector contact advantageously extends through at least a portion of the extrinsic base layer.
    Type: Application
    Filed: January 25, 2012
    Publication date: July 25, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Renata Camillo-Castillo, Zhong-Xiang He, Jeffrey B. Johnson, Qizhi Liu, Xuefeng Liu
  • Publication number: 20130146947
    Abstract: A self-aligned bipolar transistor and method of fabricating the same are disclosed. In an embodiment, a substrate and an intrinsic base are provided, followed by a first oxide layer, and an extrinsic base over the first oxide layer. A first opening is formed, exposing a portion of a surface of the extrinsic base. Sidewall spacers are formed in the first opening, and a self-aligned oxide mask is selectively formed on the exposed surface of the extrinsic base. The spacers are removed, and using the self-aligned oxide mask, the exposed extrinsic base and the first oxide layer are etched to expose the intrinsic base layer, forming a first and a second slot. A silicon layer stripe is selectively grown on the exposed intrinsic and/or extrinsic base layers in each of the first and second slots, substantially filling the respective slot.
    Type: Application
    Filed: December 13, 2011
    Publication date: June 13, 2013
    Applicant: International Business Machines Corporation
    Inventors: Kevin K. Chan, David L. Harame, Russell T. Herrin, Qizhi Liu
  • Publication number: 20130134483
    Abstract: Disclosed are a transistor and a method of forming the transistor with a raised collector pedestal in reduced dimension for reduced base-collector junction capacitance. The raised collector pedestal is on the top surface of a substrate, extends vertically through dielectric layer(s), is un-doped or low-doped, is aligned above a sub-collector region contained within the substrate and is narrower than that sub-collector region. An intrinsic base layer is above the raised collector pedestal and the dielectric layer(s). An extrinsic base layer is above the intrinsic base layer. Thus, the space between the extrinsic base layer and the sub-collector region is increased. This increased space is filled by dielectric material and the electrical connection between the intrinsic base layer and the sub-collector region is provided by the relatively narrow, un-doped or low-doped, raised collector pedestal.
    Type: Application
    Filed: November 30, 2011
    Publication date: May 30, 2013
    Applicant: International Business Machines Corporation
    Inventors: James W. Adkisson, John J. Ellis-Monaghan, David L. Harame, Qizhi Liu, John J. Pekarik
  • Publication number: 20130119435
    Abstract: An integrated device includes a lower layer pattern on a semiconductor substrate. The lower layer pattern includes a first region including first electrical devices and a second region including second electrical devices and electrically nonconductive dummy devices. A first device density of the first electrical devices in the first region is substantially greater than a second device density of the second electrical devices in the second region. A partially-planarizing dielectric layer is disposed on the lower layer pattern so as to cover the first electrical devices, the second electrical devices, and the electrically nonconductive dummy devices. The average height of the partially-planarizing dielectric layer in the first region is approximately the same as the average height in the second region. Through-holes are formed in the first region, and an electrically conductive material is disposed in the through-holes.
    Type: Application
    Filed: November 15, 2011
    Publication date: May 16, 2013
    Applicant: Avago Technologies Wiresess IP (Singapore) Pte. Ltd.
    Inventor: Thomas Dungan
  • Publication number: 20130119436
    Abstract: Methods of fabricating bipolar junction transistors, bipolar junction transistors, and design structures for a bipolar junction transistor. A first portion of the intrinsic base layer is masked while a second portion of an intrinsic base layer is etched. As a consequence of the masking, the second portion of the intrinsic base layer is thinner than the first portion of the intrinsic base layer. An emitter and an extrinsic base layer are formed in respective contacting relationships with the first and second portions of the intrinsic base layer.
    Type: Application
    Filed: November 16, 2011
    Publication date: May 16, 2013
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kevin K. Chan, Peng Cheng, Qizhi Liu, Ljubo Radic
  • Publication number: 20130119434
    Abstract: Disclosed are embodiments of a transistor (e.g., bipolar junction transistor (BJT) or a heterojunction bipolar transistor (HBT)) and a method of forming the transistor with a collector region having a protected upper edge portion for reduced base-collector junction capacitance Cbc. In the embodiments, a collector region is positioned laterally adjacent to a trench isolation region within a substrate. Mask layer(s) cover the trench isolation region and further extend laterally onto the edge portion of the collector region. A first section of an intrinsic base layer is positioned above a center portion of the collector region and a second section of the intrinsic base layer is positioned above the mask layer(s). During processing these mask layer(s) prevent divot formation in the upper corner of the trench isolation region at the isolation region-collector region interface and further limit dopant diffusion from a subsequently formed raised extrinsic base layer into the collector region.
    Type: Application
    Filed: November 15, 2011
    Publication date: May 16, 2013
    Applicant: International Business Machines Corporation
    Inventors: JAMES W. ADKISSON, David L. Harame, Robert K. Leidy, Qizhi Liu
  • Publication number: 20130113021
    Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) having a deep pseudo buried layer is disclosed. The SiGe HBT includes isolation structures formed in trenches, first pseudo buried layers and second pseudo buried layers, and a collector region. The first pseudo buried layers are formed under the respective trenches and the second pseudo buried layers are formed under the first pseudo buried layers, with each first pseudo buried layer vertically contacting with a second pseudo buried layer. The second pseudo buried layers are laterally connected to each other, and the collector region is surrounded by the trenches, the first pseudo buried layers and the second pseudo buried layers. The cross section of each of the trenches has a regular trapezoidal shape, namely, each trench's width of its top is smaller than that of its bottom. A manufacturing method of the SiGe HBT is also disclosed.
    Type: Application
    Filed: November 8, 2012
    Publication date: May 9, 2013
    Applicant: SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD.
    Inventor: Shanghai Hua Hong Nec Electronics Co., Ltd.
  • Publication number: 20130113020
    Abstract: A SiGe HBT is disclosed, which includes: a silicon substrate; shallow trench field oxides formed in the silicon substrate; a pseudo buried layer formed at bottom of each shallow trench field oxide; a collector region formed beneath the surface of the silicon substrate, the collector region being sandwiched between the shallow trench field oxides and between the pseudo buried layers; a polysilicon gate formed above each shallow trench field oxide having a thickness of greater than 150 nm; a base region on the polysilicon gates and the collector region; emitter region isolation oxides on the base region; and an emitter region on the emitter region isolation oxides and a part of the base region. The polysilicon gate is formed by gate polysilicon process of a MOSFET in a CMOS process. A method of manufacturing the SiGe HBT is also disclosed.
    Type: Application
    Filed: September 13, 2012
    Publication date: May 9, 2013
    Applicant: SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD.
    Inventors: Donghua Liu, Wenting Duan, Wensheng Qian, Jun Hu, Jing Shi
  • Publication number: 20130113022
    Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, which includes: two isolation structures each being formed in a trench; a set of three or more pseudo buried layers formed under each trench with every adjacent two pseudo buried layers of the set being vertically contacted with each other; and a collector region. In this design, the lowermost pseudo buried layers of the two sets are laterally in contact with each other, and the collector region is surrounded by the two isolation structures and the two sets of pseudo buried layers. As the breakdown voltage of a SiGe HBT according to the present invention is determined by the distance between an uppermost pseudo buried layer and the edge of an active region, SiGe HBTs having different breakdown voltages can be achieved. A manufacturing method of the SiGe HBT is also disclosed.
    Type: Application
    Filed: November 8, 2012
    Publication date: May 9, 2013
    Applicant: SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD.
    Inventor: SHANGHAI HUA HONG NEC ELECTRONICS CO.
  • Publication number: 20130099287
    Abstract: Embodiments of semiconductor structure are disclosed along with methods of forming the semiconductor structure. In one embodiment, the semiconductor structure includes a semiconductor substrate, a collector layer formed over the semiconductor substrate, a base layer formed over the semiconductor substrate, and an emitter layer formed over the semiconductor substrate. The semiconductor substrate is formed from Gallium Arsenide (GaAs), while the base layer is formed from a Gallium Indium Nitride Arsenide Antimonide (GaInNAsSb) compound. The base layer formed from the GaInNAsSb compound has a low bandgap, but a lattice that substantially matches a lattice constant of the underlying semiconductor substrate formed from GaAs. In this manner, semiconductor devices with lower base resistances, turn-on voltages, and/or offset voltages can be formed using the semiconductor structure.
    Type: Application
    Filed: October 19, 2012
    Publication date: April 25, 2013
    Applicant: RF MICRO DEVICES, INC.
    Inventor: RF MICRO DEVICES, INC.
  • Publication number: 20130099288
    Abstract: A silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) is disclosed, in which a shallow trench is formed of a first shallow trench and a second shallow trench vertically joined together in the active region, the second shallow trench being located directly under the first shallow trench and having a width less than that of the first shallow trench; a pseudo buried layer is formed surrounding the bottom and side walls of the second shallow trench and is in contact with the collector region to serve as a connection layer of a collector; a deep hole contact is formed in the shallow trench and is in contact with the pseudo buried layer to pick up the collector. A SiGe HBT manufacturing method is also disclosed. The present invention is capable of improving the cut-off frequency of a SiGe HBT.
    Type: Application
    Filed: October 24, 2012
    Publication date: April 25, 2013
    Applicant: SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD
    Inventor: Shanghai Hua Hong Nec Electronics Co.,Ltd.
  • Publication number: 20130092981
    Abstract: A SiGe HBT having a position controlled emitter-base junction is disclosed. The SiGe HBT includes: a collector region formed of an N-doped active region; a base region formed on the collector region and including a base epitaxial layer, the base epitaxial layer including a SiGe layer and a capping layer formed thereon, the SiGe layer being formed of a SiGe epitaxial layer doped with a P-type impurity, the capping layer being doped with an N-type impurity; and an emitter region formed on the base region, the emitter region being formed of polysilicon. By optimizing the distribution of impurities doped in the base region, a controllable position of the emitter-base junction and adjustability of the reverse withstanding voltage thereof can be achieved, and thereby increasing the stability of the process and improving the uniformity within wafer.
    Type: Application
    Filed: September 13, 2012
    Publication date: April 18, 2013
    Applicant: SHANGHAI HUA HONG NEC ELECTRONICS CO., LTD.
    Inventors: Feng Han, Donghua Liu, Jun Hu, Wenting Duan, Jing Shi
  • Publication number: 20130092939
    Abstract: Disclosed are example bipolar transistors capable of reducing the area of a collector, reducing the distance between a base and a collector, and/or reducing the number of ion implantation processes. A bipolar transistor may includes a trench formed by etching a portion of a semiconductor substrate. A first collector may be formed on the inner wall of the trench. A second collector may be formed inside the semiconductor substrate in the inner wall of the trench. A first isolation film may be formed on the sidewall of the first collector. An intrinsic base may be connected to the third collector. An extrinsic base may be formed on the intrinsic base and inside the first isolation film. A second isolation film may be formed on the inner wall of the extrinsic base. An emitter may be formed by burying a conductive material inside the second isolation film.
    Type: Application
    Filed: July 6, 2012
    Publication date: April 18, 2013
    Applicant: Dongbu HiTek Co., Ltd.
    Inventor: Nam Joo KIM
  • Patent number: 8415762
    Abstract: The external base electrode has a two-layered structure where a p-type polysilicon film doped with a medium concentration of boron is laminated on a p-type polysilicon film doped with a high concentration of boron. Therefore, since the p-type polysilicon film doped with a high concentration of boron is in contact with an intrinsic base layer at a junction portion between the external base electrode and the intrinsic base layer, the resistance of the junction portion can be reduced. In addition, since the resistance of the external base electrode becomes a parallel resistance of the two layers of the p-type polysilicon films, the resistance of the p-type polysilicon film whose boron concentration is relatively lower is dominant.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: April 9, 2013
    Assignee: Hitachi, Ltd.
    Inventors: Yoshinori Yoshida, Tatsuya Tominari, Toshio Ando
  • Publication number: 20130062668
    Abstract: Heterojunction bipolar transistors with reduced base resistance, as well as fabrication methods for heterojunction bipolar transistors and design structures for BiCMOS integrated circuits. The heterojunction bipolar transistor includes a conductive layer between the intrinsic base and the extrinsic base. The conductive layer is comprised of a conductive material, such as a silicide, having a lower resistivity than the materials forming the intrinsic base and the extrinsic base.
    Type: Application
    Filed: November 8, 2012
    Publication date: March 14, 2013
    Applicant: International Business Machines Corporation
    Inventor: International Business Machines Corporation
  • Patent number: 8395237
    Abstract: A bipolar transistor includes: a substrate; a collector and a base layer with a p-conductive-type, an emitter layer with an n-conductive-type. The collector layer is formed above the substrate and includes a first nitride semiconductor. The base layer with the p-conductive-type is formed on the collector layer and includes a second nit ride semiconductor. The emitter layer with the n-conductive-type is formed on the base layer and includes a third nitride semiconductor. The collector layer, the base layer and the emitter layer are formed so that crystal growing directions with respect to a surface of the substrate are in parallel to a [0001] direction of the substrate. The first nitride semiconductor includes: InycAlxcGa1-xc-ycN (0?xc?1, 0?yc?1, 0<xc+yc?1). In the first nitride semiconductor, a length of an a-axis on a surface side is longer than a length of an a-axis on a substrate side.
    Type: Grant
    Filed: October 16, 2009
    Date of Patent: March 12, 2013
    Assignee: NEC Corporation
    Inventors: Yuji Ando, Hironobu Miyamoto, Tatsuo Nakayama, Yasuhiro Okamoto, Takashi Inoue, Kazuki Ota
  • Publication number: 20130020614
    Abstract: A dual-gate normally-off nitride transistor that includes a first gate structure formed between a source electrode and a drain electrode for controlling a normally-off channel region of the dual-gate normally-off nitride transistor. A second gate structure is formed between the first gate structure and the drain electrode for modulating a normally-on channel region underneath the second gate structure. The magnitude of the threshold voltage of the second gate structure is smaller than the drain breakdown of the first gate structure for proper operation of the dual-gate normally-off nitride transistor.
    Type: Application
    Filed: July 25, 2012
    Publication date: January 24, 2013
    Applicant: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Bin Lu, Tomas Palacios
  • Publication number: 20120319170
    Abstract: Electronic device is provided, including: a base wafer whose surface is made of silicon crystal; a Group 3-5 compound semiconductor crystal formed directly or indirectly on partial region of the silicon crystal; an electronic element including a portion of the Group 3-5 compound semiconductor crystal as active layer; an insulating film formed directly or indirectly on the base wafer and covering the electronic element; an electrode formed directly or indirectly on the insulating film; a first coupling wiring extending through the insulating film, having at least a portion thereof formed directly or indirectly on the insulating film, and electrically coupling the electronic element with the electrode; a passive element formed directly or indirectly on the insulating film; a second coupling wiring extending through the insulating film, having at least a portion thereof formed directly or indirectly on the insulating film, and electrically coupling the electronic element with the passive element.
    Type: Application
    Filed: August 24, 2012
    Publication date: December 20, 2012
    Applicant: SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventors: Masahiko HATA, Sadanori YAMANAKA, Tomoyuki TAKADA, Kazuhiko HONJO
  • Publication number: 20120313146
    Abstract: Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance Rb. Specifically, a metal silicide layer covers the extrinsic base, including the portion of the extrinsic base that extends below the upper portion of a T-shaped emitter. One exemplary technique for ensuring that the metal silicide layer covers this portion of the extrinsic base requires tapering the upper portion of the emitter. Such tapering allows a sacrificial layer below the upper portion of the emitter to be completely removed during processing, thereby exposing the extrinsic base below and allowing the metal layer required for silicidation to be deposited thereon. This metal layer can be deposited, for example, using a high pressure sputtering technique to ensure that all exposed surfaces of the extrinsic base, even those below the upper portion of the emitter, are covered.
    Type: Application
    Filed: June 8, 2011
    Publication date: December 13, 2012
    Applicant: International Business Machines Corporation
    Inventors: Marc W. Cantell, Thai Doan, Jessica A. Levy, Qizhi Liu, William J. Murphy, Christa R. Willets
  • Patent number: 8299500
    Abstract: A heterojunction bipolar transistor (HBT), an integrated circuit (IC) chip including at least one HBT and a method of forming the IC. The HBT includes an extrinsic base with one or more buried interstitial barrier layer. The extrinsic base may be heavily doped with boron and each buried interstitial barrier layer is doped with a dopant containing carbon, e.g., carbon or SiGe:C. The surface of the extrinsic base may be silicided.
    Type: Grant
    Filed: August 23, 2005
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventors: Wade J. Hodge, Alvin J. Joseph, Rajendran Krishnasamy, Qizhi Liu, Bradley A. Orner
  • Publication number: 20120235151
    Abstract: A horizontal heterojunction bipolar transistor (HBT) includes doped single crystalline Ge having a doping of the first conductivity type as the base having an energy bandgap of about 0.66 eV, and doped polysilicon having a doping of a second conductivity type as a wide-gap-emitter having an energy bandgap of about 1.12 eV. In one embodiment, doped polysilicon having a doping of the second conductivity type is employed as the collector. In other embodiments, a single crystalline Ge having a doping of the second conductivity type is employed as the collector. In such embodiments, because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. In both embodiments, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.
    Type: Application
    Filed: March 15, 2011
    Publication date: September 20, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jin Cai, Kevin K. Chan, Wilfried W. Haensch, Tak H. Ning
  • Patent number: 8247843
    Abstract: An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: August 21, 2012
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Liberty L Gunter, Kanin Chu, Charles R Eddy, Jr., Theodore D Moustakas, Enrico Bellotti
  • Publication number: 20120199881
    Abstract: High frequency performance of (e.g., silicon) bipolar devices (100) is improved by reducing the extrinsic base resistance Rbx. Emitter (160), intrinsic base (161, 163) and collector (190) are formed in a semiconductor body (115). An emitter contact (154) has a region (1541) that overlaps a portion (1293, 1293?) of an extrinsic base contact (129). A sidewall (1294) is formed in the extrinsic base contact (129) proximate a lateral edge (1543) of the overlap region (1541) of the emitter contact (154). The sidewall (1294) is amorphized during or after formation so that when the emitter contact (154) and the extrinsic base contact (129) are, e.g., silicided, some of the metal atoms forming the silicide penetrate into the sidewall (1294) so that part (183) of the highly conductive silicided extrinsic base contact (182, 183) extends under the edge (1543) of the overlap region (1541) of the emitter contact (154) closer to the intrinsic base (161, 163), thereby reducing Rbx.
    Type: Application
    Filed: February 9, 2011
    Publication date: August 9, 2012
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Jay P. John, James A. Kirchgessner, Vishal P. Trivedi
  • Patent number: 8212288
    Abstract: A compound semiconductor substrate which inhibits the generation of a crack or a warp and is preferable for a normally-off type high breakdown voltage device, arranged that a multilayer buffer layer 2 in which AlxGa1-xN single crystal layers (0.6?X?1.0) 21 containing carbon from 1×1018 atoms/cm3 to 1×1021 atoms/cm3 and AlyGa1-yN single crystal layers (0.1?y?0.5) 22 containing carbon from 1×1017 atoms/cm3 to 1×1021 atoms/cm3 are alternately and repeatedly stacked in order, and a nitride active layer 3 provided with an electron transport layer 31 having a carbon concentration of 5×1017 atoms/cm3 or less and an electron supply layer 32 are deposited on a Si single crystal substrate 1 in order. The carbon concentrations of the AlxGa1-xN single crystal layers 21 and that of the AlGa1-yN single crystal layers 22 respectively decrease from the substrate 1 side towards the above-mentioned active layer 3 side. In this way, the compound semiconductor substrate is produced.
    Type: Grant
    Filed: September 10, 2010
    Date of Patent: July 3, 2012
    Assignee: Covalent Materials Corporation
    Inventors: Jun Komiyama, Kenichi Eriguchi, Hiroshi Oishi, Yoshihisa Abe, Akira Yoshida, Shunichi Suzuki
  • Publication number: 20120153351
    Abstract: According to one embodiment, a group III-V semiconductor device comprises a compositionally graded body disposed over a substrate and below a buffer layer supporting an active area of the group III-V semiconductor device. The compositionally graded body includes a first region applying compressive stress to the substrate. The compositionally graded body further includes a stress modulating region over the first region, where the stress modulating region applies tensile stress to the substrate. In one embodiment, a method for fabricating a group III-V semiconductor device comprises providing a substrate for the group III-V semiconductor device and forming a first region of a compositionally graded body over the substrate to apply compressive stress to the substrate. The method further comprises forming a stress modulating region of the compositionally graded body over the first region, where the stress modulating region applies tensile stress to the substrate.
    Type: Application
    Filed: December 21, 2010
    Publication date: June 21, 2012
    Applicant: INTERNATIONAL RECTIFIER CORPORATION
    Inventors: Anilkumar Chandolu, Ronald H. Birkhahn, Troy Larsen, Brett Hughes, Steve Hoff, Scott Nelson, Robert Brown, Leanne Sass
  • Publication number: 20120139009
    Abstract: A lateral heterojunction bipolar transistor (HBT) is formed on a semiconductor-on-insulator substrate. The HBT includes a base including a doped silicon-germanium alloy base region, an emitter including doped silicon and laterally contacting the base, and a collector including doped silicon and laterally contacting the base. Because the collector current is channeled through the doped silicon-germanium base region, the HBT can accommodate a greater current density than a comparable bipolar transistor employing a silicon channel. The base may also include an upper silicon base region and/or a lower silicon base region. In this case, the collector current is concentrated in the doped silicon-germanium base region, thereby minimizing noise introduced to carrier scattering at the periphery of the base. Further, parasitic capacitance is minimized because the emitter-base junction area is the same as the collector-base junction area.
    Type: Application
    Filed: December 2, 2010
    Publication date: June 7, 2012
    Applicant: International Business Machine Corporation
    Inventors: Tak H. Ning, Kevin K. Chan, Marwan H. Khater
  • Publication number: 20120132961
    Abstract: Disclosed is a method of manufacturing a heterojunction bipolar transistor comprising a substrate, an upper region of said substrate comprising an active region of the bipolar transistor bordered by shallow trench insulation, said active region comprising a buried collector region extending to a depth beyond the depth of the shallow trench insulation, the method comprising forming a trench in the substrate adjacent to said active region, said trench extending through the shallow trench insulation; at least partially filling said trench with an impurity; and forming a collector sinker in the substrate by developing said impurity to extend into the substrate to a depth beyond the depth of the shallow trench insulation. An IC comprising a heterojunction bipolar transistor manufactured by this method is also disclosed.
    Type: Application
    Filed: November 18, 2011
    Publication date: May 31, 2012
    Applicant: NXP B.V.
    Inventors: Tony Vanhoucke, Johannes Josephus Theodorus Marinus Donkers, Hans Mertens, Blandine Duriez, Evelyne Gridelet