Comprising Lattice Mismatched Active Layers (e.g., Sige Strained Layer Transistors) (epo) Patents (Class 257/E29.193)
  • Patent number: 9041057
    Abstract: A field effect transistor device includes a substrate, a silicon germanium (SiGe) layer disposed on the substrate, gate dielectric layer lining a surface of a cavity defined by the substrate and the silicon germanium layer, a metallic gate material on the gate dielectric layer, the metallic gate material filling the cavity, a source region, and a drain region.
    Type: Grant
    Filed: July 17, 2012
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Dechao Guo, Shu-Jen Han, Chung-Hsun Lin
  • Patent number: 8987785
    Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor includes a base situated on a substrate. The heterojunction bipolar transistor can be an NPN silicon-germanium heterojunction bipolar transistor, for example. The heterojunction bipolar transistor further includes a cap layer situated on the base, where the cap layer includes a barrier region. The barrier region can comprises carbon and has a thickness, where the thickness of the barrier region determines a depth of an emitter-junction of the heterojunction bipolar transistor. An increase in the thickness of the barrier region can cause a decrease in the depth of the emitter-base junction. According to this exemplary embodiment, the heterojunction bipolar transistor further includes an emitter situated over the cap layer, where the emitter comprises an emitter dopant, which can be phosphorus. A diffusion retardant in the barrier region of the cap layer impedes diffusion of the emitter dopant.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: March 24, 2015
    Assignee: Newport Fab, LLC
    Inventor: Greg D. U'ren
  • Patent number: 8975634
    Abstract: An object is to suppress occurrence of oxygen deficiency. An oxide semiconductor film is formed using germanium (Ge) instead of part of or all of gallium (Ga) or tin (Sn). At least one of bonds between a germanium (Ge) atom and oxygen (O) atoms has a bond energy higher than at least one of bonds between a tin (Sn) atom and oxygen (O) atoms or a gallium (Ga) atom and oxygen (O) atoms. Thus, a crystal of an oxide semiconductor formed using germanium (Ge) has a low possibility of occurrence of oxygen deficiency. Accordingly, an oxide semiconductor film is formed using germanium (Ge) in order to suppress occurrence of oxygen deficiency.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: March 10, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Motoki Nakashima
  • Patent number: 8952420
    Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.
    Type: Grant
    Filed: July 29, 2013
    Date of Patent: February 10, 2015
    Assignee: STMicroelectronics, Inc.
    Inventors: Nicolas Loubet, Pierre Morin
  • Patent number: 8939765
    Abstract: In sophisticated semiconductor devices, the defect rate that may typically be associated with the provision of a silicon/germanium material in the active region of P-channel transistors may be significantly decreased by incorporating a carbon species prior to or during the selective epitaxial growth of the silicon/germanium material. In some embodiments, the carbon species may be incorporated during the selective growth process, while in other cases an ion implantation process may be used. In this case, superior strain conditions may also be obtained in N-channel transistors.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: January 27, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Peter Javorka, Maciej Wiatr, Roman Boschke, Christian Krueger
  • Patent number: 8890226
    Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
    Type: Grant
    Filed: May 2, 2013
    Date of Patent: November 18, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mayank T. Bulsara, Matthew T. Currie, Anthony J. Lochtefeld
  • Patent number: 8853023
    Abstract: A method for stressing a pattern having a pattern surface, in a layer of semiconductive material that can be silicon on the surface of a stack of layers generated on the surface of a substrate, said stack comprising at least one stress layer of alloy SixGey with x and y being molar fractions, and a buried layer of silicon oxide, comprises: etching at the periphery of a surface of dimensions greater than said pattern surface, of the buried layer of silicon oxide and layer of alloy SixGey over a part of the depth of said layer of alloy; the buried layer of silicon oxide being situated between said layer of semiconductive material and said stress layer of alloy SixGey. In a transistor structure, etching at the periphery of said surface obtains a pattern thus defined having dimensions greater than the area of interest situated under the gate of the transistor.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: October 7, 2014
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Simeon Morvan, Francois Andrieu, Jean-Charles Barbe
  • Patent number: 8828818
    Abstract: Methods of fabricating integrated circuit device with fin transistors having different threshold voltages are provided. The methods may include forming first and second semiconductor fins including first and second semiconductor materials, respectively, and covering at least one among the first and second semiconductor fins with a mask. The methods may further include depositing a compound semiconductor layer including the first and second semiconductor materials directly onto sidewalls of the first and second semiconductor fins not covered by the mask and oxidizing the compound semiconductor layer. The oxidization process oxidizes the first semiconductor material within the compound semiconductor layer while driving the second semiconductor material within the compound semiconductor layer into the sidewalls of the first and second semiconductor fins not covered by the mask.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: September 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Mark S. Rodder
  • Patent number: 8809835
    Abstract: Circuits for processing radio frequency (“RF”) and microwave signals are fabricated using field effect transistors (“FETs”) that have one or more strained channel layers disposed on one or more planarized substrate layers. FETs having such a configuration exhibit improved values for, for example, transconductance and noise figure. RF circuits such as, for example, voltage controlled oscillators (“VCOs”), low noise amplifiers (“LNAs”), and phase locked loops (“PLLs”) built using these FETs also exhibit enhanced performance.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: August 19, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Glyn Braithwaite, Richard Hammond, Matthew T. Currie
  • Patent number: 8796666
    Abstract: A device includes a substrate, insulation regions extending into the substrate, and a semiconductor fin higher than top surfaces of the insulation regions. The semiconductor fin has a first lattice constant. A semiconductor region includes sidewall portions on opposite sides of the semiconductor fin, and a top portion over the semiconductor fin. The semiconductor region has a second lattice constant different from the first lattice constant. A strain buffer layer is between and contacting the semiconductor fin and the semiconductor region. The strain buffer layer includes an oxide.
    Type: Grant
    Filed: April 26, 2013
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Tung Ying Lee, Chung-Hsien Chen, Chi-Wen Liu
  • Patent number: 8796788
    Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides a processing for forming improved source/drain features in the semiconductor device. Semiconductor devices with the improved source/drain features may prevent or reduce defects and achieve high strain effect resulting from epi layers. In an embodiment, the source/drain features comprises a second portion surrounding a first portion, and a third portion between the second portion and the semiconductor substrate, wherein the second portion has a composition different from the first and third portions.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsz-Mei Kwok, Hsueh-Chang Sung, Kuan-Yu Chen, Hsien-Hsin Lin
  • Patent number: 8674447
    Abstract: A method and structure of an embedded stressor in a semiconductor transistor device having a sigma-shaped channel sidewall and a vertical isolation sidewall. The embedded stressor structure is made by a first etch to form a recess in a substrate having a gate and first and second spacers. The second spacers are removed and a second etch creates a step in the recess on a channel sidewall. An anisotropic etch creates facets in the channel sidewall of the recess. Where the facets meet, a vertex is formed. The depth of the vertex is determined by the second etch depth (step depth). The lateral position of the vertex is determined by the thickness of the first spacers. A semiconductor material having a different lattice spacing than the substrate is formed in the recess to achieve the embedded stressor structure.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: March 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Thomas N Adam, Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 8642413
    Abstract: A method to form a strain-inducing epitaxial film is described. In one embodiment, the strain-inducing epitaxial film is a three-component epitaxial film comprising atoms from a parent film, charge-neutral lattice-substitution atoms and charge-carrier dopant impurity atoms. In another embodiment, the strain-inducing epitaxial film is formed by a multiple deposition/etch cycle sequence involving hydrogenated amorphous silicon, followed by charge carrier dopant and charge-neutral lattice-forming impurity atom implant steps and, finally, a kinetically-driven crystallization process.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: February 4, 2014
    Assignee: Intel Corporation
    Inventors: Anand S. Murthy, Jeffrey L. Armstrong, Dennis G. Hanken
  • Patent number: 8564018
    Abstract: A structure for an integrated circuit is disclosed. The structure includes a crystalline substrate and four crystalline layers. The first crystalline layer of first lattice constant is positioned on the crystalline substrate. The second crystalline layer has a second lattice constant different from the first lattice constant, and is positioned on said first crystalline layer. The third crystalline layer has a third lattice constant different than said second lattice constant, and is positioned on said second crystalline layer. The strained fourth crystalline layer includes, at least partially, a MOSFET device.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: October 22, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun Chich Lin, Yee-Chia Yeo, Chien-Chao Huang, Chao-Hsiung Wang, Tien-Chih Chang, Chenming Hu, Fu-Liang Yang, Shih-Chang Chen, Mong-Song Liang, Liang-Gi Yao
  • Patent number: 8501508
    Abstract: Embodiments described include straining transistor quantum well (QW) channel regions with metal source/drains, and conformal regrowth source/drains to impart a uni-axial strain in a MOS channel region. Removed portions of a channel layer may be filled with a junction material having a lattice spacing different than that of the channel material to causes a uni-axial strain in the channel, in addition to a bi-axial strain caused in the channel layer by a top barrier layer and a bottom buffer layer of the quantum well.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: August 6, 2013
    Assignee: Intel Corporation
    Inventors: Prashant Majhi, Mantu Hudait, Jack T. Kavalieros, Ravi Pillarisetty, Marko Radosavljevic, Gilbert Dewey, Titash Rakshit, Willman Tsai
  • Patent number: 8455858
    Abstract: A semiconductor structure is provided. The semiconductor structure may include a substrate (100); a buffer layer or an insulation layer (200) formed on the substrate; a first strained wide bandgap semiconductor material layer (400) formed on the buffer layer or the insulation layer; a strained narrow bandgap semiconductor material layer (500) formed on the first strained wide bandgap semiconductor material layer; a second strained wide bandgap semiconductor material layer (700) formed on the strained narrow bandgap semiconductor material layer; a gate stack (300) formed on the second strained wide bandgap semiconductor material layer; and a source and a drain (600) formed in the first strained wide bandgap semiconductor material layer, the strained narrow bandgap semiconductor material layer and the second strained wide bandgap semiconductor material layer respectively.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: June 4, 2013
    Assignee: Tsinghua University
    Inventors: Jing Wang, Jun Xu, Lei Guo
  • Patent number: 8450179
    Abstract: A method for fabricating a semiconductor device having a first and second bipolar devices of the same dopant type includes: depositing a dielectric layer over a semiconductor layer, depositing a gate conductor layer over the dielectric layer, defining base regions of both bipolar devices, removing the gate conductor layer and dielectric layer in the base regions, depositing a base layer on the gate conductor layer and on the exposed semiconductor layer in the base regions, depositing an insulating layer over the base layer, forming a photoresist layer and defining emitter regions of both bipolar devices, removing the photoresist layer in the emitter regions thereby forming two emitter windows, masking the emitter window of the first bipolar device and exposing the base layer in the base region of the second bipolar device to an additional emitter implant through the associated emitter window.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: May 28, 2013
    Assignee: Texas Instruments Deutschland GmbH
    Inventors: Badih El-Kareh, Hiroshi Yasuda, Scott Balster
  • Patent number: 8441055
    Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: May 14, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mayank T. Bulsara, Matthew T. Currie, Anthony J. Lochtefeld
  • Patent number: 8426265
    Abstract: A method of manufacturing a complementary metal oxide semiconductor (CMOS) circuit, in which the method includes a reactive ion etch (RIE) of a CMOS circuit substrate that forms recesses, the CMOS circuit substrate including: an n-type field effect transistor (n-FET) region; a p-type field effect transistor (p-FET) region; an isolation region disposed between the n-FET and p-FET regions; and a gate wire comprising an n-FET gate, a p-FET gate, and gate material extending transversely from the n-FET gate across the isolation region to the p-FET gate, in which the recesses are formed adjacent to sidewalls of a reduced thickness; growing silicon germanium (SiGe) in the recesses; depositing a thin insulator layer on the CMOS circuit substrate; masking at least the p-FET region; removing the thin insulator layer from an unmasked n-FET region and an unmasked portion of the isolation region; etching the CMOS circuit substrate with hydrogen chloride (HCl) to remove the SiGe from the recesses in the n-FET region; and g
    Type: Grant
    Filed: November 3, 2010
    Date of Patent: April 23, 2013
    Assignees: International Business Machines Corporation, GlobalFoundries, Inc.
    Inventors: Bo Bai, Linda Black, Abhishek Dube, Judson R. Holt, Viorel C. Ontalus, Kathryn T. Schonenberg, Matthew W. Stoker, Keith H. Tabakman
  • Patent number: 8377780
    Abstract: A method of forming a field effect transistor and a field effect transistor. The method includes (a) forming gate stack on a silicon layer of a substrate; (b) forming two or more SiGe filled trenches in the silicon layer on at least one side of the gate stack, adjacent pairs of the two or more SiGe filled trenches separated by respective silicon regions of the silicon layer; and (c) forming source/drains in the silicon layer on opposite sides of the gate stack, the source/drains abutting a channel region of the silicon layer under the gate stack.
    Type: Grant
    Filed: September 21, 2010
    Date of Patent: February 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent A. Anderson, Edward J. Nowak
  • Patent number: 8357976
    Abstract: An electrical device on a single semiconductor substrate includes: an open base vertical PNP transistor placed in parallel with a wide bandgap, high voltage diode wherein the PNP transistor has a P doped collector region, an N-doped base layer, an N doped buffer layer, and a P doped emitter layer.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: January 22, 2013
    Assignee: Fairchild Semiconductor Corporation
    Inventors: Joseph A. Yedinak, Richard L. Woodin, Christopher L. Rexer, Praveen Muralheedaran Shenoy, Kwanghoon Oh, Chongman Yun
  • Patent number: 8350253
    Abstract: An integrated circuit (“IC”) fabricated on a semiconductor substrate has an active gate structure formed over a channel region in the semiconductor substrate. A dummy gate structure is formed on a dielectric isolation structure. The dummy gate structure and the active gate structure have the same width. A sidewall spacer on the dummy gate structure overlies a semiconductor portion between a strain-inducing insert and the dielectric isolation structure.
    Type: Grant
    Filed: January 29, 2010
    Date of Patent: January 8, 2013
    Assignee: Xilinx, Inc.
    Inventors: Bei Zhu, Hong-Tze Pan, Bang-Thu Nguyen, Qi Lin, Zhiyuan Wu, Ping-Chin Yeh, Jae-Gyung Ahn, Yun Wu
  • Patent number: 8343872
    Abstract: The present disclosure provides a method of fabricating that includes providing a semiconductor substrate; forming a gate structure on the substrate; performing an implantation process to form a doped region in the substrate; forming spacers on sidewalls of the gate structure; performing an first etching to form a recess in the substrate, where the first etching removes a portion of the doped region; performing a second etching to expand the recess in the substrate, where the second etching includes an etchant and a catalyst that enhances an etching rate at a remaining portion of the doped region; and filling the recess with a semiconductor material.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: January 1, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsueh-Chang Sung, Hsien-Hsin Lin, Kuan-Yu Chen, Chien-Chang Su, Tsz-Mei Kwok, Yi-Fang Pai
  • Patent number: 8344355
    Abstract: Semiconductor structures and devices including strained material layers having impurity-free zones, and methods for fabricating same. Certain regions of the strained material layers are kept free of impurities that can interdiffuse from adjacent portions of the semiconductor. When impurities are present in certain regions of the strained material layers, there is degradation in device performance. By employing semiconductor structures and devices (e.g., field effect transistors or “FETs”) that have the features described, or are fabricated in accordance with the steps described, device operation is enhanced.
    Type: Grant
    Filed: December 15, 2011
    Date of Patent: January 1, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matthew T. Currie, Anthony J. Lochtefeld, Richard Hammond, Eugene A. Fitzgerald
  • Patent number: 8293622
    Abstract: A semiconductor device fabrication method and a semiconductor layer formation method for making a semiconductor layer having excellent morphology selectively epitaxial-grow over a semiconductor, and a semiconductor device. When a recessed source/drain pMOSFET is fabricated, a gate electrode is formed over a Si substrate in which STIs are formed with a gate insulating film therebetween (step S1). After a side wall is formed (step S2), recesses are formed in portions of the Si substrate on both sides of the side wall (step S3). A SiGe layer including a lower layer portion and an upper layer portion is formed in the recesses of the Si substrate. The lower layer portion and the upper layer portion included in the SiGe layer are made to epitaxial-grow under a condition that growth selectivity of the lower layer portion with respect to the side wall and the STIs is lower than growth selectivity of the upper layer portion with respect to the side wall and the STIs (steps S4 and S5).
    Type: Grant
    Filed: May 14, 2008
    Date of Patent: October 23, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Masahiro Fukuda, Yosuke Shimamune
  • Patent number: 8288757
    Abstract: A recess along a sidewall is formed in a pMOS region and an nMOS region. An SiC layer of which thickness is thicker than a depth of the recess is formed in the recess. A sidewall covering a part of the SiC layer is formed at both lateral sides of a gate electrode in the pMOS region. A recess is formed by selectively removing the SiC layer in the pMOS region. A side surface of the recess at the gate insulating film side is inclined so that the upper region of the side surface, the closer to the gate insulating film in a lateral direction at a region lower than the surface of the silicon substrate. An SiGe layer is formed in the recess in the pMOS region.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: October 16, 2012
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroyuki Ohta, Yosuke Shimamune
  • Patent number: 8274071
    Abstract: A semiconductor structure includes a semiconductor substrate having a first lattice constant; a gate dielectric on the semiconductor substrate; a gate electrode on the semiconductor substrate; and a stressor having at least a portion in the semiconductor substrate and adjacent the gate electrode. The stressor has a tilted sidewall on a side adjacent the gate electrode. The stressor includes a first stressor layer having a second lattice constant substantially different from the first lattice constant; and a second stressor layer on the first stressor layer, wherein the second stressor has a third lattice constant substantially different from the first and the second lattice constants.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: September 25, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hua Yu, Mong-Song Liang, Tze-Liang Lee, Jr.-Hung Li
  • Publication number: 20120235143
    Abstract: A vertical heterojunction bipolar transistor (HBT) includes doped polysilicon having a doping of a first conductivity type as a wide-gap-emitter with an energy bandgap of about 1.12 eV and doped single crystalline Ge having a doping of the second conductivity type as the base having the energy bandgap of about 0.66 eV. Doped single crystalline Ge having of doping of the first conductivity type is employed as the collector. Because the base and the collector include the same semiconductor material, i.e., Ge, having the same lattice constant, there is no lattice mismatch issue between the collector and the base. Further, because the emitter is polycrystalline and the base is single crystalline, there is no lattice mismatch issue between the base and the emitter.
    Type: Application
    Filed: March 15, 2011
    Publication date: September 20, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jin Cai, Kevin K. Chan, Wilfried E. Haensch, Tak H. Ning
  • Patent number: 8253205
    Abstract: An integrated circuit (IC) includes a plurality of compressively strained PMOS transistors. The IC includes a substrate having a semiconductor surface. A gate stack is formed in or on the semiconductor surface and includes a gate electrode on a gate dielectric, wherein a channel region is located in the semiconductor surface below the gate dielectric. A source and a drain region is opposing sides of the gate stack. At least one compressive strain inducing region including at least one specie selected from Ge, Sn and Pb is located in at least a portion of the source and drain regions of the PMOS transistors, wherein the strain inducing region provides ?1010 dislocation lines/cm2 and an active concentration of the compressive strain inducing specie that is above a solid solubility limit for the compressive strain inducing specie in the compressive strain inducing region.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: August 28, 2012
    Assignee: Texas Instruments Incorporated
    Inventor: Amitabh Jain
  • Patent number: 8253181
    Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: August 28, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mayank Bulsara, Matthew T. Currie, Anthony J. Lochtefeld
  • Patent number: 8207040
    Abstract: A method of manufacturing a semiconductor device includes forming a gate electrode on a semiconductor substrate and a sidewall spacer on the gate electrode. Then, a portion of the semiconductor substrate at both sides of the sidewall spacer is partially etched to form a trench. A SiGe mixed crystal layer is formed in the trench. A silicon layer is formed on the SiGe mixed crystal layer. A portion of the silicon layer is partially etched using an etching solution having different etching rates in accordance with a crystal direction of a face of the silicon layer to form a capping layer including a silicon facet having an (111) inclined face.
    Type: Grant
    Filed: February 4, 2011
    Date of Patent: June 26, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoi-Sung Chung, Dong-Suk Shin, Dong-Hyuk Kim, Jung-Shik Heo, Myung-Sun Kim
  • Patent number: 8168501
    Abstract: A semiconductor device and method of manufacture thereof wherein a PMOS source/drain region of a transistor within the substrate includes a first strained layer in the PMOS source/drain region and a first capping layer in contact with the first strained layer. Further, the semiconductor device and method provide for an NMOS source/drain region of a transistor within the substrate including a second strained layer in the NMOS source/drain region and a second capping layer in contact with the second strained layer.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: May 1, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Hua Yu, Ling-Yen Yeh, Tze-Liang Lee
  • Patent number: 8154051
    Abstract: A strained channel transistor can be provided by combining a stressor positioned in the channel region with stressors positioned on opposite sides of the channel region. This produces increased strain in the channel region, resulting in correspondingly enhanced transistor performance.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: April 10, 2012
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hao Wang, Ching-Wei Tsai, Ta-Wei Wang
  • Patent number: 8124473
    Abstract: A strain enhanced semiconductor device and methods for its fabrication are provided. One method comprises embedding a strain inducing semiconductor material in the source and drain regions of the device to induce a strain in the device channel. Thin metal silicide contacts are formed to the source and drain regions so as not to relieve the induced strain. A layer of conductive material is selectively deposited in contact with the thin metal silicide contacts, and metallized contacts are formed to the conductive material.
    Type: Grant
    Filed: April 12, 2007
    Date of Patent: February 28, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: James N. Pan, Sey-Ping Sun, Andrew M. Waite
  • Patent number: 8115194
    Abstract: A semiconductor device including transistors and strain layers is provided. Each transistor includes a source region and a drain region on a substrate and a gate structure on a channel region between the source region and the drain region. Lengths of the channel regions of these transistors are the same, but at least one source or drain region has a width along a channel length direction and the width is different from widths of other source or drain regions. The strain layers include first and second strain layers embedded separately at two sides of each gate structure in the substrate. A first width of each first strain layer along the channel length direction is the same, and a second width of each second strain layer along the channel length direction is the same.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: February 14, 2012
    Assignee: United Microelectronics Corp.
    Inventor: Chin-sheng Yang
  • Patent number: 8110487
    Abstract: By incorporating a carbon species below the channel region of a P-channel transistor prior to the formation of the gate electrode structure, an efficient strain-inducing mechanism may provided, thereby enhancing performance of P-channel transistors. The position and size of the strain-inducing region may be determined on the basis of an implantation mask and respective implantation parameters, thereby providing a high degree of compatibility with conventional techniques, since the strain-inducing region may be incorporated at an early manufacturing stage, directly to respective “large area” contact elements.
    Type: Grant
    Filed: July 23, 2008
    Date of Patent: February 7, 2012
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Uwe Griebenow, Kai Frohberg, Christoph Schwan, Kerstin Ruttloff
  • Patent number: 8093143
    Abstract: A method for producing a wafer with a silicon single crystal substrate having a front and a back side and a layer of SiGe deposited on the front side, the method using steps in the following order: simultaneously polishing the front and the back side of the silicon single crystal substrate; depositing a stress compensating layer on the back side of the silicon single crystal substrate; polishing the front side of the silicon single crystal substrate; cleaning the silicon single crystal substrate having the stress compensating layer deposited on the back side; and depositing a fully or partially relaxed layer of SiGe on the front side of the silicon single crystal substrate.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: January 10, 2012
    Assignee: Siltronic AG
    Inventors: Peter Storck, Thomas Buschhardt
  • Patent number: 8084784
    Abstract: The invention relates to a method for forming a semiconductor heterostructure by providing a substrate with a first in-plane lattice parameter a1, providing a buffer layer with a second in-plane lattice parameter a2 and providing a top layer over the buffer layer. In order to improve the surface roughness of the semiconductor heterostructure, an additional layer is provided in between the buffer layer and the top layer, wherein the additional layer has a third in-plane lattice parameter a3 which is in between the first and second lattice parameters.
    Type: Grant
    Filed: June 30, 2010
    Date of Patent: December 27, 2011
    Assignee: S.O.I. Tec Silicon on Insulator Technologies
    Inventors: Christophe Figuet, Mark Kennard
  • Patent number: 8071435
    Abstract: A method for manufacturing a semiconductor device includes the steps of (a) forming a gate electrode on a silicon substrate, through a gate insulating film; (b) forming a lamination of an insulating film and a sacrificial film having different etching characteristics on the silicon substrate, covering the gate electrode, and anisotropically etching the lamination to form side wall spacers on side walls of the gate electrode and the gate insulating film; (c) implanting impurities into the silicon substrate on both sides of the side wall spacers; (d) etching the silicon substrate and the sacrificial film to form recesses in the silicon substrate, and to change a cross sectional shape of each of the side wall spacers to approximately an L-shape; (e) epitaxially growing Si—Ge-containing crystal in the recesses; and (f) depositing an insulating film containing stress, covering the side wall spacers.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: December 6, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Naoyoshi Tamura
  • Patent number: 8043919
    Abstract: A method of fabricating a semiconductor device is provided. A gate structure is formed on a substrate and then a first spacer is formed at a sidewall of the gate structure. Next, recesses are respectively formed in the substrate at two sides of the first spacer. Thereafter, a buffer layer and a doped semiconductor compound layer are formed in each recess. An extra implantation region is respectively formed on the surfaces of each buffer layer and each doped semiconductor compound layer. Afterward, source/drain contact regions are formed in the substrate at two sides of the gate structure.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: October 25, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Tai-Ju Chen, Tung-Hsing Lee, Da-Kung Lo
  • Patent number: 8039869
    Abstract: A gallium nitride device substrate comprises a layer of gallium nitride containing an additional lattice parameter altering element located over a substitute substrate.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: October 18, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Steven D. Lester, Virginia M. Robbins, Scott W. Corzine
  • Patent number: 8004035
    Abstract: A dual stress liner manufacturing method and device is described. Overlapping stress liner layers of opposite effect (e.g., tensile versus compression) may be deposited over portions of the device, and the uppermost overlapping layer may be polished down in a process that uses the bottom overlapping layer as a stopper. An insulating film may be deposited on the stress liner layers before the polishing, and another insulating film may be deposited above the first insulating film after the polishing. Contacts may be formed such that the contacts need only penetrate one stress liner layer to reach a transistor well or gate structure.
    Type: Grant
    Filed: August 4, 2009
    Date of Patent: August 23, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Gaku Sudo
  • Patent number: 7994541
    Abstract: Embodiments relate to a method for forming a wiring in a semiconductor device, that may include laminating a conductive layer for wiring formation on a semiconductor substrate, forming a photoresist layer pattern on the conductive layer, performing primary dry etching for the conductive layer after employing the photoresist layer pattern as a mask, thereby forming a wiring pattern, partially removing the photoresist layer pattern through secondary dry etching, thereby forming a passivation layer on a surface of the wiring pattern, performing tertiary dry etching for the wiring pattern and a diffusion barrier after employing the photoresist layer pattern as a mask, thereby forming a metal wiring, and removing the photoresist layer pattern.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: August 9, 2011
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Jong Soon Lee
  • Patent number: 7985985
    Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate; a first impurity diffusion suppression layer formed on the semiconductor substrate for suppressing diffusion of a channel impurity; an impurity channel layer formed on the first impurity diffusion suppression layer and containing the channel impurity; a second impurity diffusion suppression layer formed on the impurity channel layer for suppressing diffusion of the channel impurity; a channel layer formed on the second impurity diffusion suppression layer; a gate insulating film formed on the channel layer; and a gate electrode formed on the gate insulating film.
    Type: Grant
    Filed: December 19, 2008
    Date of Patent: July 26, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Akira Hokazono
  • Patent number: 7973337
    Abstract: A semiconductor device and method of manufacture thereof wherein a PMOS source/drain region of a transistor within the substrate includes a first strained layer in the PMOS source/drain region and a first capping layer in contact with the first strained layer. Further, the semiconductor device and method provide for an NMOS source/drain region of a transistor within the substrate including a second strained layer in the NMOS source/drain region and a second capping layer in contact with the second strained layer.
    Type: Grant
    Filed: July 28, 2010
    Date of Patent: July 5, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Hua Yu, Ling-Yen Yeh, Tze-Liang Lee
  • Patent number: 7968414
    Abstract: A method of fabricating a semiconductor device is disclosed that is able to suppress a short channel effect and improve carrier mobility. In the method, trenches are formed in a silicon substrate corresponding to a source region and a drain region. When epitaxially growing p-type semiconductor mixed crystal layers to fill up the trenches, the surfaces of the trenches are demarcated by facets, and extended portions of the semiconductor mixed crystal layers are formed between bottom surfaces of second side wall insulating films and a surface of the silicon substrate, and extended portion are in contact with a source extension region and a drain extension region.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: June 28, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Hiroyuki Ohta, Takashi Sakuma, Yosuke Shimamune, Akiyoshi Hatada, Akira Katakami, Naoyoshi Tamura
  • Patent number: 7964865
    Abstract: A method for forming a semiconductor substrate structure is provided. A compressively strained SiGe layer is formed on a silicon substrate. Atoms are ion-implanted onto the SiGe layer to cause end-of-range damage. Annealing is performed to relax the strained SiGe layer. During the annealing, interstitial dislocation loops are formed as uniformly distributed in the SiGe layer. The interstitial dislocation loops provide a basis for nucleation of misfit dislocations between the SiGe layer and the silicon substrate. Since the interstitial dislocation loops are distributed uniformly, the misfit locations are also distributed uniformly, thereby relaxing the SiGe layer. A tensilely strained silicon layer is formed on the relaxed SiGe layer.
    Type: Grant
    Filed: February 3, 2005
    Date of Patent: June 21, 2011
    Assignee: International Business Machines Corporation
    Inventors: Dureseti Chidambarrao, Omer H. Dokumaci
  • Patent number: 7960794
    Abstract: A non-planar tri-gate p-MOS transistor structure with a strained channel region and a non-planar tri-gate integrated strained complimentary metal-oxide-semiconductor (CMOS) structure are described. A relaxed Si1-x Gex layer is formed on the silicon-on-isolator (SOI) substrate. The relaxed Si1-x Gex layer is patterned and subsequently etched to form a fin on the oxide. The compressively stressed Si1-y Gey layer, having the Ge content y higher than the Ge content x in the relaxed Si1-x Gex layer, is epitaxially grown on the fin. The Si1-y Gey layer covers the top and two sidewalls of the fin. The compressive stress in the Si1-y Gey layer substantially increases the hole mobility in a channel of the non-planar tri-gate p-MOS transistor structure.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: June 14, 2011
    Assignee: Intel Corporation
    Inventors: Brian S Doyle, Suman Datta, Been-Yih Jin, Nancy M Zelick, Robert Chau
  • Patent number: 7956390
    Abstract: A semiconductor device having a semiconductor substrate, a first impurity region including a first conductive impurity formed in the semiconductor substrate, a first transistor and a second transistor formed in the first impurity region, a first stress film and a second stress having a first stress over the first transistor a and the second transistor, and a third stress film having a second stress different from the first stress provided in the first impurity region between the first stress film and the second stress film.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: June 7, 2011
    Assignee: Fujitsu Semiconductor Limited
    Inventor: Manabu Kojima
  • Patent number: 7943961
    Abstract: A semiconductor structure includes an active region; a gate strip overlying the active region; and a metal-oxide-semiconductor (MOS) device. A portion of the gate strip forms a gate of the MOS device. A portion of the active region forms a source/drain region of the MOS device. The semiconductor structure further includes a stressor region over the MOS device; and a stressor-free region inside the stressor region and outside the region over the active region.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: May 17, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Sen Wang, Chung-Te Lin, Min Cao, Sheng-Jier Yang