With Two-dimensional Charge Carrier Gas Channel (e.g., Hemt; With Two-dimensional Charge-carrier Layer Formed At Heterojunction Interface) (epo) Patents (Class 257/E29.246)
  • Patent number: 10109730
    Abstract: A semiconductor device includes a codoped layer, a channel layer, a barrier layer, and a gate electrode disposed in a trench extending through the barrier layer and reaching a middle point in the channel layer via a gate insulating film. On both sides of the gate electrode, a source electrode and a drain electrode are formed. On the source electrode side, an n-type semiconductor region is disposed to fix a potential and achieve a charge removing effect while, on the drain electrode side, a p-type semiconductor region is disposed to improve a drain breakdown voltage. By introducing hydrogen into a region of the codoped layer containing Mg as a p-type impurity in an amount larger than that of Si as an n-type impurity where the n-type semiconductor region is to be formed, it is possible to inactivate Mg and provide the n-type semiconductor region.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: October 23, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuo Nakayama, Hironobu Miyamoto
  • Patent number: 9035353
    Abstract: A HEMT has a compound semiconductor layer, a protection film which has an opening and covers an upper side of the compound semiconductor layer, and a gate electrode which fills the opening and has a shape riding on the compound semiconductor layer, wherein the protection film has a stacked structure of a lower insulating film not containing oxygen and an upper insulating film containing oxygen, and the opening includes a first opening formed in the lower insulating film and a second opening formed in the upper insulating film and wider than the first opening, the first opening and the second opening communicating with each other.
    Type: Grant
    Filed: August 6, 2012
    Date of Patent: May 19, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Toshihiro Ohki, Naoya Okamoto, Yuichi Minoura, Kozo Makiyama, Shirou Ozaki
  • Patent number: 9018056
    Abstract: A device with N-Channel and P-Channel III-Nitride field effect transistors comprising a non-inverted P-channel III-Nitride field effect transistor on a first nitrogen-polar nitrogen face III-Nitride material, a non-inverted N-channel III-Nitride field effect transistor, epitaxially grown, a first III-Nitride barrier layer, two-dimensional hole gas, second III-Nitride barrier layer, and a two-dimensional hole gas. A method of making complementary non-inverted P-channel and non-inverted N-channel III-Nitride FET comprising growing epitaxial layers, depositing oxide, defining opening, growing epitaxially a first nitrogen-polar III-Nitride material, buffer, back barrier, channel, spacer, barrier, and cap layer, and carrier enhancement layer, depositing oxide, growing AlN nucleation layer/polarity inversion layer, growing gallium-polar III-Nitride, including epitaxial layers, depositing dielectric, fabricating P-channel III-Nitride FET, and fabricating N-channel III-Nitride FET.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: April 28, 2015
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis J. Anderson, Michael A. Mastro, Charles R. Eddy, Jr., Jennifer K. Hite
  • Patent number: 9006791
    Abstract: A non-inverted P-channel III-nitride field effect transistor with hole carriers in the channel comprising a nitrogen-polar III-Nitride first material, a barrier material layer, a two-dimensional hole gas in the barrier layer, and wherein the nitrogen-polar III-Nitride material comprises one or more III-Nitride epitaxial material layers grown in such a manner that when GaN is epitaxially grown the top surface of the epitaxial layer is nitrogen-polar. A method of making a P-channel III-nitride field effect transistor with hole carriers in the channel comprising selecting a face or offcut orientation of a substrate so that the nitrogen-polar (001) face is the dominant face, growing a nucleation layer, growing a GaN epitaxial layer, doping the epitaxial layer, growing a barrier layer, etching the GaN, forming contacts, performing device isolation, defining a gate opening, depositing and defining gate metal, making a contact window, depositing and defining a thick metal.
    Type: Grant
    Filed: January 31, 2014
    Date of Patent: April 14, 2015
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis J. Anderson, Andrew D. Koehler, Karl D. Hobart
  • Patent number: 9000486
    Abstract: A III-nitride heterojunction semiconductor device having a III-nitride heterojunction that includes a discontinuous two-dimensional electron gas under a gate thereof.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: April 7, 2015
    Assignee: International Rectifier Corporation
    Inventors: Paul Bridger, Robert Beach
  • Patent number: 9000485
    Abstract: An electrode structure, a GaN-based semiconductor device including the electrode structure, and methods of manufacturing the same, may include a GaN-based semiconductor layer and an electrode structure on the GaN-based semiconductor layer. The electrode structure may include an electrode element including a conductive material and a diffusion layer between the electrode element and the GaN-based semiconductor layer. The diffusion layer may include a material which is an n-type dopant with respect to the GaN-based semiconductor layer, and the diffusion layer may contact the GaN-based semiconductor layer. A region of the GaN-based semiconductor layer contacting the diffusion layer may be doped with the n-type dopant. The material of the diffusion layer may comprise a Group 4 element.
    Type: Grant
    Filed: June 6, 2012
    Date of Patent: April 7, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jeong-yub Lee, Wenxu Xianyu, Chang-youl Moon, Yong-young Park, Woo-young Yang, In-jun Hwang
  • Patent number: 9000484
    Abstract: A high electron mobility field effect transistor (HEMT) includes a two dimensional electron gas (2DEG) in the drift region between the gate and the drain that has a non-uniform lateral 2DEG distribution that increases in a direction in the drift region from the gate to the drain.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: April 7, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Sameh G. Khalil, Karim S. Boutros
  • Patent number: 8987783
    Abstract: A semiconductor heterostructure having: a substrate (SS); a buffer layer (h); a spacer layer (d, e, f); a barrier layer (b, c); and which may also include a cover layer (a) is provided. The barrier layer is doped (DS); and the barrier and spacer layers are made of one or more semiconductors having wider bandgaps than the one or more materials forming the buffer layer, the heterostructure being characterized in that: the barrier layer comprises a first barrier sublayer (c) in contact with the spacer layer, and a second barrier sublayer (b), distant from the spacer layer; and in that the second barrier sublayer has a wider bandgap than the first barrier sublayer. The invention also relates to a HEMT transistor produced using such a heterostructure and to the use of such a transistor at cryogenic temperatures.
    Type: Grant
    Filed: October 7, 2011
    Date of Patent: March 24, 2015
    Assignee: Centre National de la Recherch Scientifique
    Inventors: Yong Jin, Ulf Gennser, Antonella Cavanna
  • Patent number: 8981429
    Abstract: The present invention discloses a high electron mobility transistor (HEMT) and a manufacturing method thereof. The HEMT device includes: a substrate, a first gallium nitride (GaN) layer; a P-type GaN layer, a second GaN layer, a barrier layer, a gate, a source, and a drain. The first GaN layer is formed on the substrate, and has a stepped contour from a cross-section view. The P-type GaN layer is formed on an upper step surface of the stepped contour, and has a vertical sidewall. The second GaN layer is formed on the P-type GaN layer. The barrier layer is formed on the second GaN layer. two dimensional electron gas regions are formed at junctions between the barrier layer and the first and second GaN layers. The gate is formed on an outer side of the vertical sidewall.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: March 17, 2015
    Assignee: Richtek Technology Corporation, R.O.C.
    Inventors: Chih-Fang Huang, Po-Chin Peng, Tsung-Chieh Hsiao, Ya-Hsien Liu, K. C. Chang, Hung-Der Su, Chien-Wei Chiu, Tsung-Yi Huang, Tsung-Yu Yang, Ting-Fu Chang
  • Patent number: 8975664
    Abstract: Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device may include a buffer layer disposed on a substrate, the buffer layer including gallium (Ga) and nitrogen (N), a barrier layer disposed on the buffer layer, the barrier layer including aluminum (Al) and nitrogen (N), a regrown structure disposed in and epitaxially coupled with the barrier layer, the regrown structure including nitrogen (N) and at least one of aluminum (Al) or gallium (Ga) and being epitaxially deposited at a temperature less than or equal to 600° C., and a gate terminal disposed in the barrier layer, wherein the regrown structure is disposed between the gate terminal and the buffer layer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: June 27, 2012
    Date of Patent: March 10, 2015
    Assignee: TriQuint Semiconductor, Inc.
    Inventors: Paul A. Saunier, Edward A. Beam, III
  • Patent number: 8969919
    Abstract: A field-effect transistor includes a carrier transport layer made of nitride semiconductor, a gate electrode having first and second sidewall surfaces on first and second sides, respectively, an insulating film formed directly on the gate electrode to cover at least one of the first and second sidewall surfaces, first and second ohmic electrodes formed on the first and second sides, respectively, a passivation film including a first portion extending from the first ohmic electrode toward the gate electrode to cover a surface area between the first ohmic electrode and the gate electrode and a second portion extending from the second ohmic electrode toward the gate electrode to cover a surface area between the second ohmic electrode and the gate electrode, wherein the insulating film is in direct contact with at least the first and second passivation film portions, and has a composition different from that of the passivation film.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: March 3, 2015
    Assignee: Fujitsu Limited
    Inventors: Toshihiro Ohki, Naoya Okamoto
  • Patent number: 8969918
    Abstract: An enhancement mode GaN transistor having a gate pGaN structure having a thickness which avoids dielectric failure. In one embodiment, this thickness is in the range of 400 ? to 900 ?. In a preferred embodiment, the thickness is 600 ?.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: March 3, 2015
    Assignee: Efficient Power Conversion Corporation
    Inventors: Alexander Lidow, Robert Beach, Alana Nakata, Jianjun Cao, Guang Yuan Zhao
  • Patent number: 8957453
    Abstract: A method of manufacturing a semiconductor device includes laminating and forming an electron transit layer, an electron supplying layer, an etching stop layer, and a p-type film on a substrate sequentially, the p-type film being formed of a nitride semiconductor material that includes Al doped with an impurity element that attains p-type, the etching stop layer being formed of a material that includes GaN, removing the p-type film in an area except an area where a gate electrode is to be formed, by dry etching to form a p-type layer in the area where the gate electrode is to be formed, the dry etching being conducted while plasma emission in the dry etching is observed, the dry etching being stopped after the dry etching is started and plasma emission originating from Al is not observed, and forming the gate electrode on the p-type layer.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: February 17, 2015
    Assignee: Transphorm Japan, Inc.
    Inventors: Atsushi Yamada, Kenji Nukui
  • Patent number: 8957425
    Abstract: A semiconductor device includes: a semiconductor layer disposed above a substrate; an insulating film formed by oxidizing a portion of the semiconductor layer; and an electrode disposed on the insulating film, wherein the insulating film includes gallium oxide, or gallium oxide and indium oxide.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: February 17, 2015
    Assignee: Fujitsu Limited
    Inventor: Atsushi Yamada
  • Patent number: 8956935
    Abstract: A compound semiconductor device includes: a compound semiconductor multilayer structure; a gate insulating film on the compound semiconductor multilayer structure; and a gate electrode, wherein the gate electrode includes a gate base portion on the gate insulating film and a gate umbrella portion, and a surface of the gate umbrella portion includes a Schottky contact with the compound semiconductor multilayer structure.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: February 17, 2015
    Assignee: Fujitsu Limited
    Inventor: Naoko Kurahashi
  • Patent number: 8957454
    Abstract: There are disclosed herein various implementations of semiconductor structures including III-Nitride interlayer modules. One exemplary implementation comprises a substrate and a first transition body over the substrate. The first transition body has a first lattice parameter at a first surface and a second lattice parameter at a second surface opposite the first surface. The exemplary implementation further comprises a second transition body, such as a transition module, having a smaller lattice parameter at a lower surface overlying the second surface of the first transition body and a larger lattice parameter at an upper surface of the second transition body, as well as a III-Nitride semiconductor layer over the second transition body. The second transition body may consist of two or more transition modules, and each transition module may include two or more interlayers. The first and second transition bodies reduce strain for the semiconductor structure.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: February 17, 2015
    Assignee: International Rectifier Corporation
    Inventor: Michael A. Briere
  • Patent number: 8952422
    Abstract: A field effect transistor includes an active layer and a capping layer sequentially stacked on a substrate, and a gate electrode penetrating the capping layer and being adjacent to the active layer. The gate electrode includes a foot portion adjacent to the active layer and a head portion having a width greater than a width of the foot portion. The foot portion of an end part of the gate electrode has a width less than a width of the head portion of another part of the gate electrode and greater than a width of the foot portion of the another part of the gate electrode. The foot portion of the end part of the gate electrode further penetrates the active layer so as to be adjacent to the substrate.
    Type: Grant
    Filed: June 7, 2013
    Date of Patent: February 10, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hokyun Ahn, Jong-Won Lim, Jeong-Jin Kim, Hae Cheon Kim, Jae Kyoung Mun, Eun Soo Nam
  • Patent number: 8952352
    Abstract: A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: February 10, 2015
    Assignee: International Rectifier Corporation
    Inventors: Robert Beach, Zhi He, Jianjun Cao
  • Patent number: 8941148
    Abstract: A semiconductor device is disclosed. One embodiment includes a lateral HEMT (High Electron Mobility Transistor) structure with a heterojunction between two differing group III-nitride semiconductor compounds and a layer arranged on the heterojunction. The layer includes a group III-nitride semiconductor compound and at least one barrier to hinder current flow in the layer.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: January 27, 2015
    Assignee: Infineon Technologies Austria AG
    Inventor: Gerhard Prechtl
  • Patent number: 8941116
    Abstract: In an aspect of a semiconductor device, there are provided a substrate, a transistor including an electron transit layer and an electron supply layer formed over the substrate, a nitride semiconductor layer formed over the substrate and connected to a gate of the transistor, and a controller controlling electric charges moving in the nitride semiconductor layer.
    Type: Grant
    Filed: August 12, 2011
    Date of Patent: January 27, 2015
    Assignee: Fujitsu Limited
    Inventor: Tadahiro Imada
  • Patent number: 8941118
    Abstract: A III-nitride transistor includes a III-nitride channel layer, a barrier layer over the channel layer, the barrier layer having a thickness of 1 to 10 nanometers, a dielectric layer on top of the barrier layer, a source electrode contacting the channel layer, a drain electrode contacting the channel layer, a gate trench extending through the dielectric layer and barrier layer and having a bottom located within the channel layer, a gate insulator lining the gate trench and extending over the dielectric layer, and a gate electrode in the gate trench and extending partially toward the source and the drain electrodes to form an integrated gate field-plate, wherein a distance between an interface of the channel layer and the barrier layer and the bottom of the gate trench is greater than 0 nm and less than or equal to 5 nm.
    Type: Grant
    Filed: September 30, 2013
    Date of Patent: January 27, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Rongming Chu, David F. Brown, Adam J. Williams
  • Patent number: 8936976
    Abstract: Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: January 20, 2015
    Assignee: Intel Corporation
    Inventors: Marko Radosavljevic, Prashant Majhi, Jack T. Kavalieros, Niti Goel, Wilman Tsai, Niloy Mukherjee, Yong Ju Lee, Gilbert Dewey, Willy Rachmady
  • Patent number: 8937337
    Abstract: A compound semiconductor device includes a substrate having an opening formed from the rear side thereof; a compound semiconductor layer disposed over the surface of the substrate; a local p-type region in the compound semiconductor layer, partially exposed at the end of the substrate opening; and a rear electrode made of a conductive material, disposed in the substrate opening so as to be connected to the local p-type region.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: January 20, 2015
    Assignee: Fujitsu Limited
    Inventor: Yuichi Minoura
  • Patent number: 8933487
    Abstract: A high electron mobility field effect transistor (HEMT) includes a two dimensional electron gas (2DEG) in the drift region between the gate and the drain that has a non-uniform lateral 2DEG distribution that increases in a direction in the drift region from the gate to the drain.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: January 13, 2015
    Assignee: HRL Laboratories,LLC
    Inventors: Sameh G. Khalil, Karim S. Boutros
  • Patent number: 8927354
    Abstract: An apparatus in one example comprises an antimonide-based compound semiconductor (ABCS) stack, an upper barrier layer formed on the ABCS stack, and a gate stack formed on the upper barrier layer. The upper barrier layer comprises indium, aluminum, and arsenic. The gate stack comprises a base layer of titanium and tungsten formed on the upper barrier layer.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: January 6, 2015
    Assignees: Northrop Grumman Systems Corporation, The United States of America As Represented by the Secretary of The Navy
    Inventors: Yeong-Chang Chou, Jay Crawford, Jane Lee, Jeffrey Ming-Jer Yang, John Bradley Boos, Nicolas Alexandrou Papanicolaou
  • Patent number: 8928037
    Abstract: A heterostructure semiconductor device includes a first active layer and a second active layer disposed on the first active layer. A two-dimensional electron gas layer is formed between the first and second active layers. An AlSiN passivation layer is disposed on the second active layer. First and second ohmic contacts electrically connect to the second active layer. The first and second ohmic contacts are laterally spaced-apart, with a gate being disposed between the first and second ohmic contacts.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: January 6, 2015
    Assignee: Power Integrations, Inc.
    Inventors: Jamal Ramdani, Michael Murphy, John Paul Edwards
  • Patent number: 8928039
    Abstract: According to one embodiment, a semiconductor device has a first nitride semiconductor layer, a second nitride semiconductor layer provided on the first nitride semiconductor layer and formed of a non-doped or n-type nitride semiconductor having a band gap wider than that of the first nitride semiconductor layer, a heterojunction field effect transistor having a source electrode, a drain electrode, and a gate electrode, a Schottky barrier diode having an anode electrode and a cathode electrode, and first and second element isolation insulating layers. The first element isolation insulating layer has a first end contacting with the drain electrode and the anode electrode, and a second end located in the first nitride semiconductor layer. The second element isolation insulating layer has a third end contacting with the cathode electrode, and a fourth end located in the first nitride semiconductor layer.
    Type: Grant
    Filed: October 8, 2013
    Date of Patent: January 6, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Yasunobu Saito, Hidetoshi Fujimoto, Akira Yoshioka, Tetsuya Ohno, Toshiyuki Naka
  • Patent number: 8921893
    Abstract: A circuit structure includes a substrate, an unintentionally doped gallium nitride (UID GaN) layer over the substrate, a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. A number of islands are over the donor-supply layer between the gate structure and the drain. The gate structure disposed between the drain and the source. The gate structure is adjoins at least a portion of one of the islands and/or partially disposed over at least a portion of at least one of the islands.
    Type: Grant
    Filed: December 1, 2011
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Ju Yu, Chih-Wen Hsiung, Fu-Wei Yao, Chun-Wei Hsu, Jiun-Lei Jerry Yu, Fu-Chih Yang
  • Patent number: 8921868
    Abstract: A semiconductor device includes: a semiconductor layer disposed above a substrate; an insulating film formed by oxidizing a portion of the semiconductor layer; and an electrode disposed on the insulating film, wherein the insulating film includes gallium oxide, or gallium oxide and indium oxide.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: December 30, 2014
    Assignee: Fujitsu Limited
    Inventor: Atsushi Yamada
  • Patent number: 8916908
    Abstract: A III-nitride heterojunction semiconductor device having a III-nitride heterojunction that includes a discontinuous two-dimensional electron gas under a gate thereof.
    Type: Grant
    Filed: May 30, 2013
    Date of Patent: December 23, 2014
    Assignee: International Rectifier Corporation
    Inventors: Robert Beach, Paul Bridger
  • Patent number: 8907377
    Abstract: A higher electron mobility transistor (HEMT) and a method of manufacturing the same are disclosed. According to example embodiments, the HEMT may include a channel supply layer on a channel layer, a source electrode and a drain electrode that are on at least one of the channel layer and the channel supply layer, a gate electrode between the source electrode and the drain electrode, and a source pad and a drain pad. The source pad and a drain pad electrically contact the source electrode and the drain electrode, respectively. At least a portion of at least one of the source pad and the drain pad extends into a corresponding one of the source electrode and drain electrode that the at least one of the source pad and the drain pad is in electrical contact therewith.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: December 9, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-chul Jeon, Ki-yeol Park, Young-hwan Park, Jai-kwang Shin, Jae-joon Oh, Hyuk-soon Choi, Jong-bong Ha
  • Patent number: 8907378
    Abstract: A device includes a source and a drain for transmitting and receiving an electronic charge. The device also includes a first stack and a second stack for providing at least part of a conduction path between the source and the drain, wherein the first stack includes a first gallium nitride (GaN) layer of a first polarity, and the second stack includes a second gallium nitride (GaN) layer of the second polarity, and wherein the first polarity is different from the second polarity. At least one gate operatively connected to at least the first stack for controlling a conduction of the electronic charge, such that, during an operation of the device, the conduction path includes a first two-dimensional electron gas (2DEG) channel formed in the first GaN layer and a second 2DEG channel formed in the second GaN layer.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 9, 2014
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Koon Hoo Teo, Peijie Feng, Rui Ma
  • Patent number: 8901606
    Abstract: A pseudomorphic high electron mobility transistor (pHEMT) comprises: a substrate comprising a Group III-V semiconductor material; buffer layer disposed over the substrate; and a channel layer disposed over the buffer layer. The buffer layer comprises microprecipitates of a Group V semiconductor element. A method of fabricating a pHEMT is also described.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: December 2, 2014
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Nate Perkins, Jonathan Abrokwah, Hans G. Rohdin, Phil Marsh, John Stanback
  • Patent number: 8900939
    Abstract: High electron mobility transistors and fabrication processes are presented in which a barrier material layer of uniform thickness is provided for threshold voltage control under an enhanced channel charge inducing material layer (ECCIML) in source and drain regions with the ECCIML layer removed in the gate region.
    Type: Grant
    Filed: January 28, 2014
    Date of Patent: December 2, 2014
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Travis Anderson, Karl D. Hobart, Michael A. Mastro, Charles R. Eddy, Jr.
  • Patent number: 8890211
    Abstract: A high performance high-electron mobility transistor (HEMT) design and methods of manufacturing the same are provided. This design introduces a bias layer in to the HEMT allowing the transistor to be fed with alternating current (AC) alone without the need for a negative direct current (DC) bias power supply.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: November 18, 2014
    Assignee: Lockheed Martin Corporation
    Inventors: Michael J. Mayo, Alfred A. Zinn, Roux M. Heyns
  • Patent number: 8884308
    Abstract: A high electron mobility transistor (HEMT) includes a silicon substrate, an unintentionally doped gallium nitride (UID GaN) layer over the silicon substrate. The HEMT further includes a donor-supply layer over the UID GaN layer, a gate structure, a drain, and a source over the donor-supply layer. The HEMT further includes a dielectric layer having one or more dielectric plug portions in the donor-supply layer and top portions between the gate structure and the drain over the donor-supply layer. A method for making the HEMT is also provided.
    Type: Grant
    Filed: October 12, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Ju Yu, Chih-Wen Hsiung, Fu-Wei Yao, Chun-Wei Hsu, King-Yuen Wong, Jiun-Lei Jerry Yu, Fu-Chih Yang
  • Patent number: 8884335
    Abstract: A semiconductor including a lateral HEMT and to a method for production of a lateral HEMT is disclosed. In one embodiment, the lateral HEMT has a substrate and a first layer, wherein the first layer has a semiconductor material of a first conduction type and is arranged at least partially on the substrate. Furthermore, the lateral HEMT has a second layer, wherein the second layer has a semiconductor material and is arranged at least partially on the first layer. In addition, the lateral HEMT has a third layer, wherein the third layer has a semiconductor material of a second conduction type, which is complementary to the first conduction type, and is arranged at least partially in the first layer.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: November 11, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Walter Rieger, Markus Zundel
  • Patent number: 8884334
    Abstract: A transistor includes a first layer of a first type disposed over a buffer layer and having a first concentration of a first material. A first layer of a second type is disposed over the first layer of the first type, and a second layer of the first type is disposed over the first layer of the second type. The second layer of the first type having a second concentration of a first material that is greater than the first concentration of the first material. A source and a drain are spaced laterally from one another and are disposed over the buffer layer. A gate disposed over at least a portion of the second layer of the first type and disposed within a recessed area defined by the first and second layers of the first type and the first layer of the second type.
    Type: Grant
    Filed: November 9, 2012
    Date of Patent: November 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wen Hsiung, Chen-Ju Yu, Fu-Wei Yao
  • Patent number: 8878246
    Abstract: A High electron mobility transistor (HEMT) includes a source electrode, a gate electrode, a drain electrode, a channel forming layer in which a two-dimensional electron gas (2DEG) channel is induced, and a channel supplying layer for inducing the 2DEG channel in the channel forming layer. The source electrode and the drain electrode are located on the channel supplying layer. A channel increase layer is between the channel supplying layer and the source and drain electrodes. A thickness of the channel supplying layer is less than about 15 nm.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-jun Hwang, Jai-kwang Shin, Jae-joon Oh, Jong-seob Kim, Hyuk-soon Choi, Ki-ha Hong
  • Patent number: 8872190
    Abstract: A semiconductor device including a plurality of source pads, a plurality of drain fingers, a plurality of gate fingers, a drain combiner connected to the plurality of drain fingers, and a gate combiner connected to the plurality of gate fingers. The plurality of source pads generally comprises a pair of end source pads and one or more inner source pads. Each end source pad is configured to have added inductance. Each of the drain fingers is generally disposed between two of the plurality of source pads. Each of the gate fingers is generally disposed between a respective source pad and a respective drain finger.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: October 28, 2014
    Assignee: M/A-COM Technology Solutions Holdings, Inc.
    Inventors: Alan C. Young, Simon J. Mahon
  • Patent number: 8866191
    Abstract: A transistor in which the electric field is reduced in critical areas using field plates, permitting the electric field to be more uniformly distributed along the component, is provided, wherein the electric field in the active region is smoothed and field peaks are reduced. The semiconductor component has a substrate with an active layer structure, a source contact and a drain contact located on said active layer structure. The source contact and the drain contact are mutually spaced and at least one part of a gate contact is provided on the active layer structure in the region between the source contact and the drain contact, a gate field plate being electrically connected to the gate contact. In addition, at least two separate field plates are placed directly on the active layer structure or directly on a passivation layer.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: October 21, 2014
    Assignee: Forschungsverbund Berlin E.V.
    Inventors: Eldat Bahat-Treidel, Victor Sidorov, Joachim Wuerfl
  • Patent number: 8860091
    Abstract: A device and a method of making said wherein the device wherein the device has a group III-nitride buffer deposited on a substrate; and a group III-nitride heterostructure disposed on a surface of the group III-nitride buffer, wherein the group III-nitride heterostructure has a group III-nitride channel and a group III-nitride barrier layer disposed on a surface of the group III-nitride channel, the group III-nitride barrier layer including Al as one of its constituent group III elements, the Al having a mole fraction which varies at least throughout a portion of said group III-nitride barrier layer.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: October 14, 2014
    Assignee: HRL Laboratories, LLC
    Inventors: David F. Brown, Miroslav Micovic
  • Patent number: 8860087
    Abstract: The present invention relates to a nitride semiconductor device and a manufacturing method thereof. According to one aspect of the present invention, a nitride semiconductor device including: a nitride semiconductor layer having a 2DEG channel; a source electrode in ohmic contact with the nitride semiconductor layer; a drain electrode in ohmic contact with the nitride semiconductor layer; a plurality of p-type nitride semiconductor segments formed on the nitride semiconductor layer and each formed lengthways from a first sidewall thereof, which is spaced apart from the source electrode, to a drain side; and a gate electrode formed to be close to the source electrode and in contact with the nitride semiconductor layer between the plurality of p-type semiconductor segments and portions of the p-type semiconductor segments extending in the direction of a source-side sidewall of the gate electrode aligned with the first sidewalls of the p-type nitride semiconductor segments is provided.
    Type: Grant
    Filed: April 9, 2012
    Date of Patent: October 14, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Hwan Park, Woo Chul Jeon, Ki Yeol Park, Seok Yoon Hong
  • Patent number: 8853744
    Abstract: Some exemplary embodiments of a III-nitride power device including a HEMT with multiple interconnect metal layers and a solderable front metal structure using solder bars for external circuit connections have been disclosed. The solderable front metal structure may comprise a tri-metal such as TiNiAg, and may be configured to expose source and drain contacts of the HEMT as alternating elongated digits or bars. Additionally, a single package may integrate multiple such HEMTs wherein the front metal structures expose alternating interdigitated source and drain contacts, which may be advantageous for DC-DC power conversion circuit designs using III-nitride devices. By using solder bars for external circuit connections, lateral conduction is enabled, thereby advantageously reducing device Rdson.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 7, 2014
    Assignee: International Rectifier Corporation
    Inventors: Chuan Cheah, Michael A. Briere
  • Patent number: 8847280
    Abstract: An improved insulated gate field effect device is obtained by providing a substrate desirably comprising a III-V semiconductor, having a further semiconductor layer on the substrate adapted to contain the channel of the device between spaced apart source-drain electrodes formed on the semiconductor layer. A dielectric layer is formed on the semiconductor layer. A sealing layer is formed on the dielectric layer and exposed to an oxygen plasma. A gate electrode is formed on the dielectric layer between the source-drain electrodes. The dielectric layer preferably comprises gallium-oxide and/or gadolinium-gallium oxide, and the oxygen plasma is preferably an inductively coupled plasma. A further sealing layer of, for example, silicon nitride is desirably provided above the sealing layer. Surface states and gate dielectric traps that otherwise adversely affect leakage and channel sheet resistance are much reduced.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: September 30, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jonathan K. Abrokwah, Ravindranath Droopad, Matthias Passlack
  • Patent number: 8841703
    Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. A fluorine region is embedded in the second III-V compound layer under the gate electrode. A gate dielectric layer is disposed over the second III-V compound layer. The gate dielectric layer has a fluorine segment on the fluorine region and under at least a portion of the gate electrode.
    Type: Grant
    Filed: November 16, 2011
    Date of Patent: September 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: King-Yuen Wong, Chen-Ju Yu, Fu-Wei Yao, Chun-Wei Hsu, Jiun-Lei Jerry Yu, Chih-Wen Hsiung, Fu-Chih Yang
  • Patent number: 8841704
    Abstract: Disclosed herein is a nitride based semiconductor device, including: a substrate; a nitride based semiconductor layer having a lower nitride based semiconductor layer and an upper nitride based semiconductor layer on the substrate; an isolation area including an interface between the lower nitride based semiconductor layer and the upper nitride based semiconductor layer; and drain electrodes, source electrode, and gate electrodes formed on the upper nitride based semiconductor layer. According to preferred embodiments of the present invention, in the nitride based semiconductor device, by using the isolation area including the interface between the lower nitride based semiconductor layer and the upper nitride based semiconductor layer, problems of parasitic capacitance and leakage current are solved, and as a result, a switching speed can be improved through a gate pad.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: September 23, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young Hwan Park, Woo Chul Jeon, Ki Yeol Park, Seok Yoon Hong
  • Patent number: 8841706
    Abstract: An AlN layer (2), a GaN buffer layer (3), a non-doped AlGaN layer (4a), an n-type AlGaN layer (4b), an n-type GaN layer (5), a non-doped AlN layer (6) and an SiN layer (7) are sequentially formed on an SiC substrate (1). At least three openings are formed in the non-doped AlN layer (6) and the SiN layer (7), and a source electrode (8a), a drain electrode (8b) and a gate electrode (19) are evaporated in these openings.
    Type: Grant
    Filed: May 9, 2013
    Date of Patent: September 23, 2014
    Assignee: Fujitsu Limited
    Inventor: Toshihide Kikkawa
  • Patent number: 8841702
    Abstract: A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.
    Type: Grant
    Filed: July 30, 2013
    Date of Patent: September 23, 2014
    Assignee: Transphorm Inc.
    Inventors: Umesh Mishra, Robert Coffie, Likun Shen, Ilan Ben-Yaacov, Primit Parikh
  • Patent number: 8835984
    Abstract: Embodiments of the invention include sensors comprising AlGaAs/GaAs high electron mobility transistors (HEMTs), inGaP/GaAs HEMTs. InAlAs/InGaAs HEMTs, AlGaAs/InGaAs PHEMTs, InAlAs/InGaAs PHEMTs, Sb based HEMTs, or InAs based HEMTs, the HEMTs having functionalization at a gate surface with target receptors. The target receptors allow sensitivity to targets (or substrates) for detecting breast cancer, prostate cancer, kidney injury, chloride, glucose, metals or pEI where a signal is generated by the HEMI when a solution is contacted with the sensor. The solution can be blood, saliva, urine, breath condensate, or any solution suspected of containing any specific analyte for the sensor.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: September 16, 2014
    Assignee: University of Florida Research Foundation, Inc.
    Inventors: Fan Ren, Stephen John Pearton, Tanmay Lele, Hung-Ta Wang, Byoung-Sam Kang