Abstract: One object is to provide a semiconductor device capable of reducing loss during turn-on and degradation of forward voltage. A vertical MOSFET includes a semiconductor substrate 2 of a first conductivity type, a first semiconductor layer 1 of the first conductivity type, a second semiconductor layer 16 of a second conductivity type, first semiconductor regions 17 of the first conductivity type, first trenches 31 and a second trench 32, gate electrodes 20 provided in the first trenches 31 via a gate insulating film 19, and a Schottky electrode 29 provided in the second trench 32. The first trenches 31 are provided in a striped pattern, in a plan view and the second trench 32 surrounds the first trenches 31.

Abstract: Temperature sensors for integrated circuits that use back-gate bias for low power operation. A temperature sensor can comprise a voltage-gate-source generator having sensing transistors; an Ibias generator; a back-gate bias generator; and a temperature read-out circuit. In a calibration mode, the temperature sensor determines a back-gate bias voltage and a resistor trimming code to be used during functional operation.

Abstract: Devices and methods are provided where a control terminal resistance of a transistor device is set depending on operating conditions within a specified range of operating conditions.

Abstract: A non-planar semiconductor transistor device includes a substrate layer. Conductive channels extend between corresponding source and drain electrodes. A gate stack extending in a direction perpendicular to the conductive channels crosses over the plurality of conductive channels. The gate stack includes a dielectric layer running along the substrate and the plurality of conductive channels and arranged with a substantially uniform layer thickness, a work-function electrode layer covers the dielectric layer and is arranged with a substantially uniform layer thickness, and a metal layer, distinct from the work-function electrode layer, covers the work-function electrode layer and is arranged with a substantially uniform height with respect to the substrate such that the metal layer fills a gap between proximate conductive channels of the plurality of conductive channels.

Abstract: A device includes a semiconductor region in a semiconductor chip, a gate dielectric layer over the semiconductor region, and a gate electrode over the gate dielectric. A drain region is disposed at a top surface of the semiconductor region and adjacent to the gate electrode. A gate spacer is on a sidewall of the gate electrode. A dielectric layer is disposed over the gate electrode and the gate spacer. A conductive field plate is over the dielectric layer, wherein the conductive field plate has a portion on a drain side of the gate electrode. A deep metal via is disposed in the semiconductor region. A source electrode is underlying the semiconductor region, wherein the source electrode is electrically shorted to the conductive field plate through the deep metal via.

Abstract: Electronic devices (20, 20?) of superior design flexibility that avoid channel-width quantization effects common with prior art fin-type (FIN) field effect transistors (FIN-FETS) (22) are obtained by providing multiple FIN-FETs (22) and at least one planar FET (32, 32?) on a common substrate (21), wherein the multiple FIN-FETs (22) have fins (231, 232) of at least fin heights H1 and H2, with H2<H1. The multiple FIN-FETs (22) and the at least one planar FET (32, 32?) are separated vertically as well as laterally, which aids electrical isolation therebetween. Such electrical isolation can be enhanced by forming the planar FET (32) in a semiconductor region (441) insulated from the common substrate (21).

Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Abstract: A semiconductor device that includes a gate structure on a channel region of a semiconductor substrate. A first source region and a first drain region are present in the semiconductor substrate on opposing sides of the gate structure. At least one spacer is present on the sidewalls of the gate structure. The at least one spacer includes a first spacer and a second spacer. The first spacer of the at least one spacer is in direct contact with the sidewall of the gate structure and is present over an entire width of the first source region and the first drain region. The second spacer of the at least one spacer extends from the first spacer of the at least one spacer and has a length that covers an entire length of a first source region and a first drain region.

Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Abstract: A semiconductor device that includes a gate structure on a channel region of a semiconductor substrate. A first source region and a first drain region are present in the semiconductor substrate on opposing sides of the gate structure. At least one spacer is present on the sidewalls of the gate structure. The at least one spacer includes a first spacer and a second spacer. The first spacer of the at least one spacer is in direct contact with the sidewall of the gate structure and is present over an entire width of the first source region and the first drain region. The second spacer of the at least one spacer extends from the first spacer of the at least one spacer and has a length that covers an entire length of a first source region and a first drain region.

Abstract: A short gate high power metal oxide semiconductor field effect transistor formed in a trench includes a short gate having gate length defined by spacers within the trench. The transistor further includes a buried region that extends beneath the trench and beyond a corner of the trench, that effectively shields the gate from high drain voltage, to prevent short channel effects and resultantly improve device performance and reliability.

Abstract: A nonplanar semiconductor device having a semiconductor body formed on an insulating layer of a substrate. The semiconductor body has a top surface opposite a bottom surface formed on the insulating layer and a pair of laterally opposite sidewalls wherein the distance between the laterally opposite sidewalls at the top surface is greater than at the bottom surface. A gate dielectric layer is formed on the top surface of the semiconductor body and on the sidewalls of the semiconductor body. A gate electrode is formed on the gate dielectric layer on the top surface and sidewalls of the semiconductor body. A pair of source/drain regions are formed in the semiconductor body on opposite sides of the gate electrode.

Abstract: A semiconductor device is formed having lower gate to drain capacitance. A trench (80) is formed adjacent to a drain (20) of the semiconductor device. Trench (80) has a sidewall surface (100) and a surface (90). A doped region (110) is implanted through the sidewall surface (100) of trench (80). A dielectric layer (150) overlies the sidewall surface (100) of trench (80). A shield layer (170) overlies the dielectric layer (150). The shield layer (170) is between a portion of drain (20) and a portion of the gate and gate interconnect of the semiconductor device thereby reducing gate to drain capacitance. The shield layer (170) overlies a minority portion of the surface (90) of trench (80). A second shield layer (270) further reduces gate to drain capacitance.

Abstract: A power semiconductor device includes a semiconductor body. The semiconductor body includes a body region of a first conductivity type for forming therein a conductive channel of a second conductivity type; a gate electrode arranged next to the body region; and a floating electrode arranged between the gate electrode and the body region.

Abstract: Embodiments relate to a semiconductor device having a minimized on-resistance. According to embodiments, a semiconductor device may include at least one of the following: a first conductive type well formed on and/or over a semiconductor substrate, a second conductive type body region formed within the first conductive type well a first conductive type source region formed on and/or over the surface of the body region, a first conductive type drain region formed on and/or over the surface of the first conductive type well. Further, according to embodiments, a semiconductor device may include a field insulation layer positioned between the first conductive type source region and the first conductive type drain region and a gate electrode formed on and/or over the field insulation layer. The source region may be formed at a lower position than the drain region.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type and a first doping concentration. A first semiconductor region, used as drain, of the first conductivity type has a lower doping concentration than the semiconductor layer and is over the semiconductor layer. A gate dielectric is over the first semiconductor region. A gate electrode over the gate dielectric has a metal-containing center portion and first and second silicon portions on opposite sides of the center portion. A second semiconductor region, used as a channel, of the second conductivity type has a first portion under the first silicon portion and the gate dielectric. A third semiconductor region, used as a source, of the first conductivity type is laterally adjacent to the first portion of the second semiconductor region. The metal-containing center portion, replacing silicon, increases the source to drain breakdown voltage.

Abstract: Provided are a semiconductor device having a mesa-type active region including a plurality of slabs and a method of manufacturing the semiconductor device. The semiconductor device includes a first active region and a second active region. The first active region is formed in a line-and-space pattern on a substrate and includes the slabs, each slab having a first surface, a second surface facing a direction opposite to the first side, and a top surface. The first active region and the second active region are composed of identical or different materials. The second active region contacts at least one end of each of the slabs on the substrate to connect the slabs to one another. The method includes forming a first active region in a line-and-space pattern on the substrate and forming the second active region.

Abstract: A silicon (Si)-on-insulator (SOI) high voltage transistor with a body ground is provided with an associated fabrication process. The method provides a SOI substrate with a buried oxide (BOX) layer and a Si top layer having a first thickness and a second thickness, greater than the first thickness. A body ground is formed in the second thickness of Si top layer overlying the BOX layer. A control channel is formed in the first thickness of the Si top layer. A control gate is formed overlying the control channel. An auxiliary channel is formed in the second thickness of Si top layer partially overlying the body ground and extending into the first thickness of the Si top layer. An auxiliary gate is formed overlying the auxiliary channel. A pn junction is formed in the second thickness of Si top layer between the auxiliary channel and the body ground.

Abstract: Unit cells of metal oxide semiconductor (MOS) transistors are provided including an integrated circuit substrate and a MOS transistor on the integrated circuit substrate. The MOS transistor has a source region, a drain region and a gate region, the gate region being between the source region and the drain region. First and second channel regions are provided between the source and drain regions. The channel region is defined by first and second spaced apart protrusions in the integrated circuit substrate separated by a trench region. The first and second protrusions extend away from the integrated circuit substrate and upper surfaces of the first and second protrusions are substantially planar with upper surfaces of the source and drain regions. A gate electrode is provided in the trench region extending on sidewalls of the first and second spaced apart protrusions and on at least a portion of surfaces of the first and second spaced apart protrusions.

Abstract: A semiconductor component includes a semiconductor layer (110) having a trench (326). The trench has first and second sides. A portion (713) of the semiconductor layer has a conductivity type and a charge density. The semiconductor component also includes a control electrode (540, 1240) in the trench. The semiconductor component further includes a channel region (120) in the semiconductor layer and adjacent to the trench. The semiconductor component still further includes a region (755) in the semiconductor layer. The region has a conductivity type different from that of the portion of the semiconductor layer. The region also has a charge density balancing the charge density of the portion of the semiconductor layer.

Abstract: In a method of forming semiconductor device, a semiconductor fin is formed on a semiconductor-on-insulator substrate. A gate dielectric is formed over at least a portion of the semiconductor fin. A first gate electrode material is formed over the gate dielectric and a second gate electrode material is formed over the first gate electrode material. The second gate electrode material is planarized and then etched selectively with respect to first gate electrode material. The first gate electrode material can then be etched.

Abstract: A fin field effect transistor (FinFET) includes a first gate and a second gate. The first gate has a vertical part that is defined by sidewalls of a silicon fin and sidewalls of a capping pattern disposed on the silicon fin and a horizontal part horizontally extends from the vertical part. The second gate is made of a low-resistivity material and is in direct contact with the horizontal part of the first gate. A channel may be controlled due to the first gate, and a device operating speed may be enhanced due to the second gate. Related fabrication methods also are described.