With Ldd Structure Or Extension Or Offset Region Or Characterized By Doping Profile (epo) Patents (Class 257/E29.278)
  • Patent number: 9935137
    Abstract: The present invention provides a manufacture method of a LTPS array substrate. By utilizing one halftone mask, the N type heavy doping, the channel doping of the first polysilicon layer of the NMOS region and the P type heavy doping of the second polysilicon layer of the PMOS region, the three processes which previously require three masks are integrated into one mask process, and two exposure processes are eliminated, which significantly raises the exposure capacity, and meanwhile saves the manufacture cost of two masks to effectively reduce the manufacture cost of the LTPS array substrate, and the manufactured LTPS array substrate possesses great electrical property.
    Type: Grant
    Filed: May 26, 2016
    Date of Patent: April 3, 2018
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Chao He
  • Patent number: 9768268
    Abstract: A semiconductor device according to an embodiment switches high-frequency signals and includes a semiconductor layer of a first conductivity type. A first layer of a second conductivity type is provided in the semiconductor layer. A second layer of the second conductivity type is provided in the semiconductor layer. A gate dielectric film is provided on the semiconductor layer, the first layer and the second layer. A gate electrode is provided on the gate dielectric film. The gate dielectric film includes a first portion and the semiconductor layer, and a second portion located at both side of the first portion-in a gate length direction of the gate electrode and being thicker than the first portion. At least a part of the second portion is located between the gate electrode and the first layer and between the gate electrode and the second layer.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: September 19, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Nishihori, Takahiro Nakagawa
  • Patent number: 9666709
    Abstract: A non-planar semiconductor structure includes a semiconductor substrate, multiple raised semiconductor structures coupled to the substrate, a drain well in each of the raised structures, and a drain in each drain well. The structure further includes an isolation region in each drain well adjacent the drain, each isolation region reaching to a top surface of the corresponding raised structure, and a conductive center gate on each raised structure, the conductive center gate covering a top surface, a front surface and a back surface thereof, and covering a portion of the isolation region opposite the drain. The isolation regions in the drain wells reaching to the raised structure top surface is a result of preserving the isolation region by covering it during fabrication with an HDP oxide to prevent partial removal.
    Type: Grant
    Filed: January 29, 2015
    Date of Patent: May 30, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Xiaoli He, Yanxiang Liu, Jerome Ciavatti, Myung Hee Nam
  • Patent number: 9583613
    Abstract: A semiconductor device includes a first well that is disposed in a semiconductor substrate. The semiconductor device further includes a second well that is disposed in the semiconductor substrate. The semiconductor device further includes a source region, a drain region, and a gate structure between the source region and the drain region. The gate structure is disposed above the first well. The source region includes a first conducting contact above the first well and. The drain region includes a second conducting contact above the second well, the drain region being connected with the second well at least partially through a first epi region. The first epi region and the second well are configured to lower a first driving voltage applied on the source region and the drain region to a second voltage applied on the gate structure.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: February 28, 2017
    Assignee: BROADCOM CORPORATION
    Inventors: Akira Ito, Shom Ponoth
  • Patent number: 9583519
    Abstract: The present invention provides a method of manufacturing a thin film transistor pixel unit, comprising: forming a metal oxide layer, a gate insulating layer, a gate metal layer and an etching barrier layer on a substrate, wherein the metal oxide layer is in a thin film transistor region; through a same mask, etching a part of the etching barrier layer, the gate metal layer and the gate insulating layer on the substrate for forming a gate region, source and drain regions for forming contact vias, a gate interface region, and a storage capacitor region, respectively. Through additional steps including etching, metallizing, and filling, a source contact via is formed in the source region, a drain contact via is formed in the drain region, and a connecting contact via is formed in the gate interface region, respectively.
    Type: Grant
    Filed: December 23, 2015
    Date of Patent: February 28, 2017
    Assignee: SHENZHEN ROYOLE TECHNOLOGIES CO., LTD.
    Inventors: Xiaojun Yu, Peng Wei, Zihong Liu
  • Patent number: 9269796
    Abstract: The present invention provides a method of manufacturing a thin film transistor and a pixel unit thereof, comprising: forming a metal oxide layer, a gate insulating layer, a gate metal layer and an etching barrier layer on a substrate; through the same mask, etching a part of the etching barrier layer, the gate metal layer and the gate insulating layer on the substrate, while retaining: the metal oxide layer, the gate insulating layer, the gate metal layer and the etching barrier layer in a gate region, and the part of the metal oxide layer, the gate insulating layer and the gate metal layer in source and drain regions for forming contact vias; and exposing the remaining metal oxide layer in the source region and in the drain region; depositing a passivation layer, etching and metallizing the exposed oxide in the source and drain regions to form the source and drain contact vias.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: February 23, 2016
    Assignee: SHENZHEN ROYOLE TECHNOLOGIES CO., LTD.
    Inventors: Xiaojun Yu, Peng Wei, Zihong Liu
  • Patent number: 9041108
    Abstract: MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created.
    Type: Grant
    Filed: October 22, 2013
    Date of Patent: May 26, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Pranita Kerber, Ali Khakifirooz
  • Patent number: 8957424
    Abstract: Disclosed is an electroluminescence device having a substrate, a thin film transistor over the substrate, an insulating film over the thin film transistor, an electroluminescence element over the insulating film, a passivation film over the electroluminescence element, and a counter substrate over the passivation film. The electroluminescence element is configured to emit light through the counter substrate, and a space between the substrate and the counter substrate is filled with a filler. The electroluminescence device is featured by the tapered side surface of a gate electrode of the thin film transistor.
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: February 17, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Ono, Hideomi Suzawa, Tatsuya Arao
  • Patent number: 8872182
    Abstract: By increasing an interval between electrodes which drives liquid crystals, a gradient of an electric field applied between the electrodes can be controlled and an optimal electric field can be applied between the electrodes. The invention includes a first electrode formed over a substrate, an insulating film formed over the substrate and the first electrode, a thin film transistor including a semiconductor film in which a source, a channel region, and a drain are formed over the insulating film, a second electrode located over the semiconductor film and the first electrode and including first opening patterns, and liquid crystals provided over the second electrode.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: October 28, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 8841671
    Abstract: By increasing an interval between electrodes which drives liquid crystals, a gradient of an electric field applied between the electrodes can be controlled and an optimal electric field can be applied between the electrodes. The invention includes a first electrode formed over a substrate, an insulating film formed over the substrate and the first electrode, a thin film transistor including a semiconductor film in which a source, a channel region, and a drain are formed over the insulating film, a second electrode located over the semiconductor film and the first electrode and including first opening patterns, and liquid crystals provided over the second electrode.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: September 23, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 8803143
    Abstract: A transistor in a display device is expected to have higher withstand voltage, and it is an object to improve the reliability of a transistor which is driven by high voltage or large current. A semiconductor device includes a transistor in which buffer layers are provided between a semiconductor layer forming a channel formation region and source and drain electrode layers. The buffer layers are provided between the semiconductor layer forming a channel formation region and the source and drain electrode layers in order to particularly relieve an electric field in the vicinity of a drain edge and improve the withstand voltage of the transistor.
    Type: Grant
    Filed: October 12, 2011
    Date of Patent: August 12, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8729557
    Abstract: Disclosed is an electroluminescence device having a substrate, a thin film transistor over the substrate, an insulating film over the thin film transistor, an electroluminescence element over the insulating film, a passivation film over the electroluminescence element, and a counter substrate over the passivation film. The electroluminescence element is configured to emit light through the counter substrate, and a space between the substrate and the counter substrate is filled with a filler. The electroluminescence device is featured by the tapered side surface of a gate electrode of the thin film transistor.
    Type: Grant
    Filed: September 16, 2013
    Date of Patent: May 20, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Ono, Hideomi Suzawa, Tatsuya Arao
  • Patent number: 8664659
    Abstract: Provided are an organic light-emitting diode (OLED) display apparatus and a method of manufacturing the OLED display apparatus. Pixel-defining layers (PDLs) are formed of inorganic and organic insulating layers to minimize non-uniformities of the thicknesses of organic emission layers (OEMLs) and planarize lower thin film transistors (TFTs). Therefore, a lifespan of the OLED display apparatus is improved.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: March 4, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jin-Goo Kang, Mu-Hyun Kim, Jae-Bok Kim
  • Patent number: 8648394
    Abstract: A method for forming a conformal buffer layer of uniform thickness and a resulting semiconductor structure are disclosed. The conformal buffer layer is used to protect highly-doped extension regions during formation of an epitaxial layer that is used for inducing mechanical stress on the channel region of transistors.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: February 11, 2014
    Assignee: International Business Machines Corporation
    Inventors: Abhishek Dube, Jophy Stephen Koshy
  • Patent number: 8629502
    Abstract: MOSFETs and methods for making MOSFETs with a recessed channel and abrupt junctions are disclosed. The method includes creating source and drain extensions while a dummy gate is in place. The source/drain extensions create a diffuse junction with the silicon substrate. The method continues by removing the dummy gate and etching a recess in the silicon substrate. The recess intersects at least a portion of the source and drain junction. Then a channel is formed by growing a silicon film to at least partially fill the recess. The channel has sharp junctions with the source and drains, while the unetched silicon remaining below the channel has diffuse junctions with the source and drain. Thus, a MOSFET with two junction regions, sharp and diffuse, in the same transistor can be created.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: January 14, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce Doris, Ali Khakifirooz, Pranita Kulkarni
  • Patent number: 8569767
    Abstract: Disclosed is an electroluminescence device having a substrate, a thin film transistor over the substrate, an insulating film over the thin film transistor, an electroluminescence element over the insulating film, a passivation film over the electroluminescence element, and a counter substrate over the passivation film. The electroluminescence element is configured to emit light through the counter substrate, and a space between the substrate and the counter substrate is filled with a filler. The electroluminescence device is featured by the tapered side surface of a gate electrode of the thin film transistor.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: October 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Ono, Hideomi Suzawa, Tatsuya Arao
  • Patent number: 8546204
    Abstract: A method for forming a conformal buffer layer of uniform thickness and a resulting semiconductor structure are disclosed. The conformal buffer layer is used to protect highly-doped extension regions during formation of an epitaxial layer that is used for inducing mechanical stress on the channel region of transistors.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: October 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Abhishek Dube, Jophy Stephen Koshy
  • Patent number: 8525177
    Abstract: By increasing an interval between electrodes which drives liquid crystals, a gradient of an electric field applied between the electrodes can be controlled and an optimal electric field can be applied between the electrodes. The invention includes a first electrode formed over a substrate, an insulating film formed over the substrate and the first electrode, a thin film transistor including a semiconductor film in which a source, a channel region, and a drain are formed over the insulating film, a second electrode located over the semiconductor film and the first electrode and including first opening patterns, and liquid crystals provided over the second electrode.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: September 3, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hajime Kimura
  • Patent number: 8518754
    Abstract: An organic EL display including a plurality of pixels each having, in order from a substrate side, a first electrode, an organic layer including a light emission layer, and a second electrode; an auxiliary wiring disposed in a periphery region of each of the plurality of pixels and conducted to the second electrode; and another auxiliary wiring disposed apart from the auxiliary wiring at least in a part of outer periphery of a formation region of the auxiliary wiring in a substrate surface.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: August 27, 2013
    Assignee: Sony Corporation
    Inventors: Kazunari Takagi, Kazuo Nakamura
  • Patent number: 8507996
    Abstract: An integrated circuit structure includes a semiconductor substrate; a gate stack overlying the semiconductor substrate; a gate spacer on a sidewall of the gate stack; a first contact plug having an inner edge contacting a sidewall of the gate spacer, and a top surface level with a top surface of the gate stack; and a second contact plug over and contacting the first contact plug. The second contact plug has a cross-sectional area smaller than a cross-sectional area of the first contact plug.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: August 13, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sey-Ping Sun, Chih-Hao Chang, Chao-An Jong, Tsung-Lin Lee, Chung-Ju Lee, Chin-Hsiang Lin
  • Patent number: 8482058
    Abstract: In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: July 9, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Yutaka Hoshino, Shuji Ikeda, Isao Yoshida, Shiro Kamohara, Megumi Kawakami, Tomoyuki Miyake, Masatoshi Morikawa
  • Patent number: 8450161
    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: May 28, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hao Chen, Hao-Ming Lien, Ssu-Yu Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Liang Chen, Chung-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang
  • Patent number: 8421191
    Abstract: Semiconductor structures are disclosed that include at least one FET gate stack located on a semiconductor substrate. The at least one FET gate stack includes source and drain extension regions located within the semiconductor substrate. A device channel is also present between the source and drain extension regions and beneath the at least one gate stack. Embedded stressor elements are located on opposite sides of the at least one FET gate stack and within the semiconductor substrate. Each stressor element includes a lower layer of a first epitaxy doped semiconductor material having a lattice constant that is different from a lattice constant of the semiconductor substrate and imparts a strain in the device channel, and an upper layer of a second epitaxy doped semiconductor material. At least one monolayer of dopant is located within the upper layer of each of the embedded stressor elements.
    Type: Grant
    Filed: June 26, 2012
    Date of Patent: April 16, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kevin K. Chan, Abhishek Dube, Judson R. Holt, Jinghong Li, Joseph S. Newbury, Viorel Ontalus, Dae-Gyu Park, Zhengmao Zhu
  • Patent number: 8410549
    Abstract: Insulated-gate field-effect transistors (“IGFETs”), both symmetric and asymmetric, suitable for a semiconductor fabrication platform that provides IGFETs for analog and digital applications, including mixed-signal applications, utilize empty-well regions in achieving high performance. A relatively small amount of semiconductor well dopant is near the top of each empty well. Each IGFET (100, 102, 112, 114, 124, or 126) has a pair of source/drain zones laterally separated by a channel zone of body material of the empty well (180, 182, 192, 194, 204, or 206). A gate electrode overlies a gate dielectric layer above the channel zone. Each source/drain zone (240, 242, 280, 282, 520, 522, 550, 552, 720, 722, 752, or 752) has a main portion (240M, 242M, 280M, 282M, 520M, 522M, 550M, 552M, 720M, 722M, 752M, or 752M) and a more lightly doped lateral extension (240E, 242E, 280E, 282E, 520E, 522E, 550E, 552E, 720E, 722E, 752E, or 752E).
    Type: Grant
    Filed: March 27, 2009
    Date of Patent: April 2, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Constantin Bulucea, Jeng-Jiun Yang, William D. French, Sandeep R. Bahl, D. Courtney Parker
  • Patent number: 8362491
    Abstract: An LCD device is disclosed, to minimize the signal distortion by decreasing the instability of voltage in a-Si:H TFT of a gate driving signal output unit, which includes a signal controller for outputting first and second control signals Q and /Q; a pull-up transistor between a clock signal terminal CLK and a gate driving signal output terminal for receiving the first control signal Q, the pull-up transistor having a first gate electrode, a first source electrode and a first drain electrode, wherein the pull-up transistor has an asymmetric structure in a first area of the first source electrode overlapped with the first gate electrode and a second area of the first drain electrode overlapped with the first gate electrode; and a pull-down transistor connected between the gate driving signal output terminal and a ground voltage terminal, wherein the pull-down transistor receives the second control signal.
    Type: Grant
    Filed: April 11, 2011
    Date of Patent: January 29, 2013
    Assignee: LG Display Co., Ltd.
    Inventors: Yong Ho Jang, Nam Wook Cho, Min Doo Chun
  • Patent number: 8278722
    Abstract: A flat panel display device is disclosed that may include a light-emitting layer portion including a first electrode, a second electrode, and an organic light-emitting layer between the first and second electrodes; at least two thin film transistors for controlling the light-emitting layer portion; a scanning signal line for supplying a scanning signal to the thin film transistor; a data signal line for supplying a data signal to the thin film transistor; a light emitting region having a common power supply line for supplying current to the light-emitting layer portion; and a peripheral common power supply line having at least one curved portion and connected to the common power supply line on a panel of a non-light emitting region except the light emitting region, wherein the common power supply line has a reduced wiring width while maintaining a constant wiring resistance to thereby reduce the total size of the display panel.
    Type: Grant
    Filed: August 2, 2007
    Date of Patent: October 2, 2012
    Assignee: Samsung Display Co., Ltd.
    Inventors: Tae-Wook Kang, Choong-Youl Im
  • Patent number: 8264015
    Abstract: A semiconductor device in which a first insulated gate field effect transistor (1) is connected in series with a second field effect transistor, FET, (2), wherein the second field effect transistor (2) has a heavily doped source region (19A) which is electrically connected to a heavily doped drain contact region (191) of the first insulated gate field effect transistor, and further that the breakthrough voltage of the first insulated gate field effect transistor (1) is higher than the pinch voltage, Vp, of the second field effect transistor (2).
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: September 11, 2012
    Inventor: Klas-Håkan Eklund
  • Patent number: 8198683
    Abstract: A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.
    Type: Grant
    Filed: December 2, 2010
    Date of Patent: June 12, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshimitsu Konuma, Akira Sugawara, Yukiko Uehara, Hongyong Zhang, Atsunori Suzuki, Hideto Ohnuma, Naoaki Yamaguchi, Hideomi Suzawa, Hideki Uochi, Yasuhiko Takemura
  • Patent number: 8193586
    Abstract: The present disclosure provides a semiconductor device that includes a semiconductor substrate and a transistor formed in the substrate. The transistor includes a gate stack having a high-k dielectric and metal gate, a sealing layer formed on sidewalls of the gate stack, the sealing layer having an inner edge and an outer edge, the inner edge interfacing with the sidewall of the gate stack, a spacer formed on the outer edge of the sealing layer, and a source/drain region formed on each side of the gate stack, the source/drain region including a lightly doped source/drain (LDD) region that is aligned with the outer edge of the sealing layer.
    Type: Grant
    Filed: February 20, 2009
    Date of Patent: June 5, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hao Chen, Hao-Ming Lien, Ssu-Yi Li, Jun-Lin Yeh, Kang-Cheng Lin, Kuo-Tai Huang, Chii-Horng Li, Chien-Hau Fei, Wen-Chih Yang, Jin-Aun Ng, Chi Hsin Chang, Chun Ming Lin, Harry Chuang, Chien-Liang Chen
  • Patent number: 8129262
    Abstract: Fabrication of an insulated-gate field-effect transistor (110) entails separately introducing three body-material dopants, typically through an opening in a mask, into body material (50) of a semiconductor body so as to reach respective maximum dopant concentrations at three different vertical locations in the body material. A gate electrode (74) is subsequently defined after which a pair of source/drain zones (60 and 62), each having a main portion (60M or 80M) and a more lightly doped lateral extension (60E or 62E), are formed in the semiconductor body. An anneal is performed during or subsequent to introduction of semiconductor dopant that defines the source/drain zones. The body material is typically provided with at least one more heavily doped halo pocket portion (100 and 102) along the source/drain zones. The vertical dopant profile resulting from the body-material dopants alleviates punchthrough and reduces current leakage.
    Type: Grant
    Filed: October 27, 2009
    Date of Patent: March 6, 2012
    Assignee: National Semiconductor Corporation
    Inventors: Constantin Bulucea, Fu-Cheng Wang, Prasad Chaparala
  • Patent number: 8120039
    Abstract: In a semiconductor device, typically an active matrix display device, the structure of TFTs arranged in the respective circuits are made suitable in accordance with the function of the circuit, and along with improving the operating characteristics and the reliability of the semiconductor device, the manufacturing cost is reduced and the yield is increased by reducing the number of process steps.
    Type: Grant
    Filed: July 13, 2009
    Date of Patent: February 21, 2012
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Koji Ono, Hideomi Suzawa, Tatsuya Arao
  • Patent number: 8106466
    Abstract: A method for fabricating a MOS transistor is disclosed. First, a semiconductor substrate having a gate thereon is provided. A spacer is then formed on the sidewall of the gate, and two recesses are formed adjacent to the spacer and within the semiconductor substrate. Next, the spacer is thinned, and epitaxial layer is grown in each of the two recesses. By thinning the spacer before the epitaxial layer is formed, the present invention could stop the epitaxial layer to grow against the sidewall of the spacer, thereby preventing problem such as Ion degradation.
    Type: Grant
    Filed: August 10, 2008
    Date of Patent: January 31, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Po-Lun Cheng, Pin-Chien Chu
  • Patent number: 8067804
    Abstract: The present invention provides a semiconductor device capable of suppressing a body floating effect, and a manufacturing method thereof. A semiconductor device having an SOI structure includes a silicon substrate, a buried insulating layer formed on the silicon substrate, and a semiconductor layer formed on the buried insulating layer. The semiconductor layer has a body region of a first conduction type, a source region of a second conduction type and a drain region of the second conduction type, and a gate electrode is formed on the body region between the source region and the drain region via a gate oxide film. The source region includes an extension layer of the second conduction type, and a silicide layer which makes contact with the extension layer at its side face, and a crystal defect region is formed on a region of a depletion layer generated in a boundary portion between the silicide layer and the body region.
    Type: Grant
    Filed: October 18, 2005
    Date of Patent: November 29, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Shigeto Maegawa, Takashi Ipposhi
  • Patent number: 8067772
    Abstract: An object is to provide a semiconductor device with improved reliability and for which a defect due to an end portion of a semiconductor layer provided in an island-shape is prevented, and a manufacturing method thereof. A structure includes an island-shaped semiconductor layer provided over a substrate, an insulating layer provided over a top surface and a side surface of the island-shaped semiconductor layer, and a gate electrode provided over the island-shaped semiconductor layer with the insulating layer interposed therebetween. In the insulating layer provided to be in contact with the island-shaped semiconductor layer, a region that is in contact with the side surface of the island-shaped semiconductor layer is made to have a lower dielectric constant than a region over the top surface of the island-shaped semiconductor layer.
    Type: Grant
    Filed: December 3, 2007
    Date of Patent: November 29, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kazuko Ikeda, Shinya Sasagawa, Hideomi Suzawa, Shunpei Yamazaki
  • Patent number: 7994040
    Abstract: A method for forming a semiconductor device is disclosed. A substrate including a gate dielectric layer and a gate electrode layer sequentially formed thereon is provided. An offset spacer is formed on sidewalls of the gate dielectric layer and the gate electrode layer. A carbon spacer is formed on a sidewall of the offset spacer, and the carbon spacer is then removed. The substrate is implanted to form a lightly doped region using the gate electrode layer and the offset spacer as a mask. The method may also include providing a substrate having a gate dielectric layer and a gate electrode layer sequentially formed thereon. A liner layer is formed on sidewalls of the gate electrode layer and on the substrate. A carbon spacer is formed on a portion of the liner layer adjacent the sidewall of the gate electrode layer. A main spacer is formed on a sidewall of the carbon spacer. The carbon spacer is removed to form an opening between the liner layer and the main spacer.
    Type: Grant
    Filed: April 13, 2007
    Date of Patent: August 9, 2011
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Min-Hwa Chi, Wen-Chuan Chiang, Mu-Chi Chiang, Chang-Ku Chen
  • Patent number: 7964873
    Abstract: A thin film transistor array panel is provided, which includes: a substrate; a first polysilicon member that is formed on the substrate and includes an intrinsic region, at least one first extrinsic region, and at least one second extrinsic region disposed between the intrinsic region and the at least one first extrinsic region and having an impurity concentration lower than the at least one first extrinsic region; a first insulator formed on the first polysilicon member and having an edge substantially coinciding with a boundary between the at least one first extrinsic region and the at least one second extrinsic region; and a first electrode formed on the first• insulator and having an edge substantially coinciding with a boundary between the intrinsic region and the at least one second extrinsic region.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: June 21, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Chun-Gi You
  • Patent number: 7956425
    Abstract: Thin film transistors (TFT) and methods for making same. The TFTs generally comprise: (a) a semiconductor layer comprising source and drain terminals and a channel region therebetween; (b) a gate electrode comprising a gate and a gate dielectric layer between the gate and the channel region; (c) a first dielectric layer adjacent to the gate electrode and in contact with the source and drain terminals, the first dielectric layer comprising a material which comprises a dopant therein; and (d) an electrically functional source/drain extensions in the channel region, adjacent to the source and drain terminals, comprising a material which comprises the same dopant as the first dielectric layer.
    Type: Grant
    Filed: February 2, 2010
    Date of Patent: June 7, 2011
    Assignee: Kovio, Inc.
    Inventor: James Montague Cleeves
  • Patent number: 7947984
    Abstract: An LCD device is disclosed, to minimize the signal distortion by decreasing the instability of voltage in a—Si:H TFT of a gate driving signal output unit, which includes a signal controller for outputting first and second control signals Q and /Q; a pull-up transistor between a clock signal terminal CLK and a gate driving signal output terminal for receiving the first control signal Q, the pull-up transistor having a first gate electrode, a first source electrode and a first drain electrode, wherein the pull-up transistor has an asymmetric structure in a first area of the first source electrode overlapped with the first gate electrode and a second area of the first drain electrode overlapped with the first gate electrode; and a pull-down transistor connected between the gate driving signal output terminal and a ground voltage terminal, wherein the pull-down transistor receives the second control signal.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: May 24, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: Yong Ho Jang, Nam Wook Cho, Min Doo Chun
  • Patent number: 7948040
    Abstract: A semiconductor device includes a semiconductor layer overlapping with a gate electrode and having an impurity region outside a region which overlaps with the gate electrode; a first conductive layer which is provided on a side provided with the gate electrode of the semiconductor layer and partially in contact with the impurity region; an insulating layer provided over the gate electrode and the first conductive layer; and a second conductive layer which is formed in the insulating layer and in contact with the first conductive layer through an opening at least part of which overlaps with the first conductive layer.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: May 24, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Kengo Akimoto
  • Patent number: 7906820
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a source offset type MOS transistor in which a source and a drain are formed on a semiconductor substrate by having a predetermined distance between the source and the drain, and a gate electrode is formed on the semiconductor substrate between the source and the drain via a gate insulation film. One end of the drain overlaps or abuts on one end of the gate electrode when viewed from above the gate electrode, and the source is formed by having a distance from the gate electrode when viewed from above the gate electrode.
    Type: Grant
    Filed: October 31, 2008
    Date of Patent: March 15, 2011
    Assignee: Ricoh Company, Ltd.
    Inventor: Masaya Ohtsuka
  • Patent number: 7902002
    Abstract: When a semi-conductor film is irradiated with conventional pulsed laser light, unevenness, which is called as ridge, is caused on the surface of the semiconductor film. In the case of a top-gate type TFT, element characteristics are changed depending on the ridge. In particular, there is a problem in that variation in the plural thin film transistors electrically connected in parallel with one another. According to the present invention, in manufacturing a circuit including plural thin film transistors, the width LP of a region (not including a microcrystal region) that is melted by irradiating a semiconductor film with light of a continuous wave laser is enlarged, and active layers of a plurality of thin film transistors (that are electrically connected in parallel with one another) are arranged in one region.
    Type: Grant
    Filed: July 25, 2005
    Date of Patent: March 8, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Koichiro Tanaka
  • Patent number: 7888752
    Abstract: A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive type to the substrate using the gate structure as a mask, to form a doped depletion region beneath and separated from the source/drain regions. The doped depletion regions have an impurity concentration and thickness so that the doped depletion regions are depleted due to a built-in potential creatable between the doped depletion regions and the substrate. The doped depletion region and substrate form depletion regions between the source/drain regions and the doped depletion region. We perform a S/D implant by implanting ions having a second conductivity type into the substrate to form S/D regions. The doped depletion region and depletion regions reduce the capacitance between the source/drain regions and the substrate.
    Type: Grant
    Filed: February 14, 2007
    Date of Patent: February 15, 2011
    Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.
    Inventors: King Jien Chui, Francis Benistant, Ganesh Shamkar Samudra, Kian Meng Tee, Yisuo Li, Kum Woh Vincent Leong, Kheng Chok Tee
  • Patent number: 7872309
    Abstract: A recessed-gate thin-film transistor (RG-TFT) with a self-aligned lightly doped drain (LDD) is provided, along with a corresponding fabrication method. The method deposits an insulator overlying a substrate and etches a trench in the insulator. The trench has a bottom and sidewalls. An active silicon (Si) layer is formed overlying the insulator and trench, with a gate oxide layer over the active Si layer. A recessed gate electrode is then formed in the trench. The TFT is doped and LDD regions are formed in the active Si layer overlying the trench sidewalls. The LDD regions have a length that extends from a top of the trench sidewall, to the trench bottom, with a doping density that decreases in response to the LDD length. Alternately stated, the LDD length is directly related to the depth of the trench.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: January 18, 2011
    Assignee: Sharp Labratories of America, Inc.
    Inventors: Paul J. Schuele, Mark A. Crowder, Apostolos T. Voutsas, Hidayat Kisdarjono
  • Patent number: 7847355
    Abstract: A TFT formed on an insulating substrate source, drain and channel regions, a gate insulating film formed on at least the channel region and a gate electrode formed on the gate insulating film. Between the channel region and the drain region, a region having a higher resistivity is provided in order to reduce an Ioff current. A method for forming this structure comprises the steps of anodizing the gate electrode to form a porous anodic oxide film on the side of the gate electrode; removing a portion of the gate insulating using the porous anodic oxide film as a mask so that the gate insulating film extends beyond the gate electrode but does not completely cover the source and drain regions. Thereafter, an ion doping of one conductivity element is performed. The high resistivity region is defined under the gate insulating film.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: December 7, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshimitsu Konuma, Akira Sugawara, Yukiko Uehara, Hongyong Zhang, Atsunori Suzuki, Hideto Ohnuma, Naoaki Yamaguchi, Hideomi Suzawa, Hideki Uochi, Yasuhiko Takemura
  • Patent number: 7829393
    Abstract: A copper gate electrode, applied in a thin-film-transistor liquid crystal display (LCD) device, at least comprises a patterned copper layer formed on a glass substrate, and a barrier layer formed on the patterned copper layer. The barrier layer comprises at least one of nitrogen and phosphorus, or comprises an alloy formularized as M1M2R wherein M1 is cobalt (Co) or molybdenum (Mo), M2 is tungsten (W), molybdenum (Mo), rhenium (Re) or vanadium (V), and R is boron (B) or phosphorus (P).
    Type: Grant
    Filed: February 6, 2009
    Date of Patent: November 9, 2010
    Assignee: Au Optronics Corp.
    Inventors: Yu-Wei Liu, Wen-Ching Tsai, Kuo-Yu Huang, Hui-Fen Lin
  • Patent number: 7808037
    Abstract: A high-voltage semiconductor device includes a silicon substrate having a main surface, a gate on the main surface of the silicon substrate, a source region in a portion of the silicon substrate proximate the main surface and a drain region in a portion of the silicon substrate proximate the main surface. The drain region is spaced apart from the source region. A channel region is defined in a portion of the silicon substrate proximate the main surface between the source region and the drain region. The channel region is at least partially beneath the gate. An additional region is disposed on the main surface proximate the channel region. The additional region being formed of one of a high-k material and a conductive material.
    Type: Grant
    Filed: December 16, 2005
    Date of Patent: October 5, 2010
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Hsin Wen Chang, Yao Wen Chang
  • Patent number: 7799627
    Abstract: Embodiments relate to a multi device that may include a first MOS transistor having a first gate oxide film, and a second MOS transistor having a second gate oxide film thicker than the first gate oxide film. According to embodiments, a LDD structure of the first MOS transistor may be a two-layered structure in which a first LDD region and a second LDD region are disposed vertically downward from the surface of a wafer, and the second LDD region is substantially the same as an LDD structure in the second MOS transistor in doping concentration.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: September 21, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventors: Jae-Hyun Yoo, Jong-Min Kim
  • Patent number: 7800178
    Abstract: A semiconductor device includes at least one thin film transistor including a semiconductor layer that has a crystalline region including a channel region, a source region and a drain region, a gate insulating film disposed at least on the channel region, the source region and the drain region of the semiconductor layer, and a gate electrode arranged so as to oppose the channel region via the gate insulating film. At least a portion of the semiconductor layer includes a catalyst element capable of promoting crystallization, and the semiconductor layer further includes a gettering region that includes the catalyst element at a higher concentration than in the channel region or the source region and the drain region. The thickness of the gate insulating film on the gettering region is smaller than that on the source region and the drain region, or the gate insulating film is not disposed on the gettering region.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: September 21, 2010
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Naoki Makita
  • Patent number: RE41764
    Abstract: A semiconductor device may include a channel region formed between a source and a drain region. One or more first pockets may be formed in the channel region adjacent to junctions. The first pockets may be doped with a dopant of the first conductivity type. At least one second pocket may be formed adjacent to each of the junctions and stacked against each of the first pockets. The second pocket may be doped with a dopant of a second conductivity type such that the dopant concentration in the second pocket is less than the dopant concentration in the first pockets. The second pocket may reduce a local substrate concentration without changing the conductivity type of the channel region.
    Type: Grant
    Filed: June 5, 2000
    Date of Patent: September 28, 2010
    Inventors: Thomas Skotnicki, Romain Gwoziecki
  • Patent number: RE41927
    Abstract: In a TFT LCD device comprising a substrate, at least one thin film transistor formed on the substrate, having a source electrode and a drain electrode, an insulating layer formed over the whole surface of the substrate on which the thin film transistor is formed, having at least one contact hole exposing a portion of the drain electrode, and reflective layer pixel electrode corresponding to the thin film transistor, formed on the insulating layer to be connected with the drain electrode through the contact hole, the pixel electrode is formed of a multi-layered conductive layer. The drain electrode is composed of multiple layers, and the most upper layer of the multiple layers is one selected from a Cr layer and a MoW layer. Preferably, the multi-layered conductive layer is composed of two-layered conductive layer having a lower layer of the same material as that of the most upper layer and an upper layer of Al-containing metal.
    Type: Grant
    Filed: May 11, 2006
    Date of Patent: November 16, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Suk Chung, Chang-Won Hwang