Polycrystalline Or Microcrystalline Silicon Transistor (epo) Patents (Class 257/E29.292)
  • Patent number: 8089071
    Abstract: A thin film semiconductor device is provided. The semiconductor device includes a semiconductor thin film configured to have an active region turned into a polycrystalline region through irradiation with an energy beam, and a gate electrode configured to be provided to traverse the active region. Successive crystal grain boundaries extend along the gate electrode in a channel part that is the active region overlapping with the gate electrode, and the crystal grain boundaries traverse the channel part and are provided cyclically in a channel length direction.
    Type: Grant
    Filed: March 7, 2007
    Date of Patent: January 3, 2012
    Assignee: Sony Corporation
    Inventors: Akio Machida, Toshio Fujino, Tadahiro Kono
  • Publication number: 20110309364
    Abstract: It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface while controlling film formation time, can control treatment time of heating treatment with an object of removing moisture, and can prevent moisture in the interlayer insulating film from being discharged to a film or an electrode adjacent to the interlayer insulating film. An inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover a TFT. Next, an organic resin film containing photosensitive acrylic resin is applied to the organic insulating film, and the organic resin film is partially exposed to light to be opened. Thereafter, an inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover the opened organic resin film.
    Type: Application
    Filed: August 25, 2011
    Publication date: December 22, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Satoshi MURAKAMI, Masahiko HAYAKAWA, Kiyoshi KATO, Mitsuaki OSAME
  • Publication number: 20110303919
    Abstract: To provide a display device including a thin film transistor in which high electric characteristics and reduction in off-current can be achieved. The display device having a thin film transistor includes a substrate, a gate electrode provided over the substrate, a gate insulating film provided over the gate electrode, a microcrystalline semiconductor film provided over the gate electrode with the gate insulating film interposed therebetween, a channel protection layer which is provided over and in contact with the microcrystalline semiconductor film, an amorphous semiconductor film provided over the gate insulating film and on a side surface of the microcrystalline semiconductor film and the channel protection layer, an impurity semiconductor layer provided over the amorphous semiconductor film, and a source electrode and a drain electrode provided over and in contact with the impurity semiconductor layer.
    Type: Application
    Filed: August 23, 2011
    Publication date: December 15, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Satoshi KOBAYASHI, Atsushi MIYAGUCHI, Yoshitaka MORIYA, Yoshiyuki KUROKAWA, Daisuke KAWAE
  • Publication number: 20110297940
    Abstract: A semiconductor element of the electric circuit includes a semiconductor layer over a gate electrode. The semiconductor layer of the semiconductor element is formed of a layer including polycrystalline silicon which is obtained by crystallizing amorphous silicon by heat treatment or laser irradiation, over a substrate. The obtained layer including polycrystalline silicon is also used for a structure layer such as a movable electrode of a structure body. Therefore, the structure body and the electric circuit for controlling the structure body can be formed over one substrate. As a result, a micromachine can be miniaturized. Further, assembly and packaging are unnecessary, so that manufacturing cost can be reduced.
    Type: Application
    Filed: August 22, 2011
    Publication date: December 8, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Mayumi Yamaguchi, Konami Izumi
  • Publication number: 20110297952
    Abstract: A thin film transistor according to an example embodiment includes: a substrate body; a semiconductor layer formed on the substrate body and comprising a polycrystalline silicon film having a surface resistance from about 2000 ohm/sq to about 8000 ohm/sq; and a source electrode and a drain electrode each contacted with the semiconductor layer and comprising a metallic material having a resistance from about 350 to about 2000 ohm.
    Type: Application
    Filed: May 25, 2011
    Publication date: December 8, 2011
    Applicant: Samsung Mobile Display Co., Ltd.
    Inventors: Jae-Seob LEE, Yong-Hwan Park, Young-Shin Pyo
  • Publication number: 20110284859
    Abstract: A method includes forming a non-continuous epitaxial layer over a semiconductor substrate. The substrate includes multiple mesas separated by trenches. The epitaxial layer includes crystalline Group III nitride portions over at least the mesas of the substrate. The method also includes depositing a dielectric material in the trenches. The method could also include forming spacers on sidewalls of the mesas and trenches or forming a mask over the substrate that is open at tops of the mesas. The epitaxial layer could also include Group III nitride portions at bottoms of the trenches. The method could further include forming gate structures, source and drain contacts, conductive interconnects, and conductive plugs over at least one crystalline Group III nitride portion, where at least some interconnects and plugs are at least partially over the trenches. The gate structures, source and drain contacts, interconnects, and plugs could be formed using standard silicon processing tools.
    Type: Application
    Filed: May 19, 2010
    Publication date: November 24, 2011
    Applicant: National Semiconductor Corporation
    Inventors: Sandeep R. Bahl, Abdalla Naem
  • Publication number: 20110284860
    Abstract: A method for producing a semiconductor device includes a step of forming a first insulation film, a step of forming a separation layer in a base layer, a step of forming a light-blocking film on the surface of the first insulation film, a step of forming a second insulation film such that the light-blocking film is covered, a step of affixing the base layer provided with the light-blocking film to a substrate, a step of separating and removing along the separation layer a portion of the base layer affixed to the substrate, and a step of forming a semiconductor layer such that at least a portion thereof overlaps with the light-blocking film.
    Type: Application
    Filed: December 4, 2009
    Publication date: November 24, 2011
    Applicant: SHARP KABUSHIKI KAISHA
    Inventor: Kenshi Tada
  • Publication number: 20110278583
    Abstract: A thin-film semiconductor device includes, in order, a substrate, a gate electrode, a gate insulating film, a first channel layer, and a second channel layer. The second channel layer includes a protrusion between first top surface end portions. The protrusion has first lateral surfaces that each extend between one of the first top surface end portions and a top surface of the protrusion. An insulation layer is on the top surface of the protrusion. The insulation layer has second lateral surfaces that each extend to one of second top surface end portions of the insulation layer. Two contact layers are each on one of the second top surface end portions of the insulation layer, adjacent one of the second lateral surfaces of the insulation layer, adjacent one of the first lateral surfaces of the protrusion, and on one of the first top surface end portions of the second channel layer. A source electrode is on one of the two contact layers, and a drain electrode is on the other of the two contact layers.
    Type: Application
    Filed: May 25, 2011
    Publication date: November 17, 2011
    Applicants: PANASONIC LIQUID CRYSTAL DISPLAY CO., LTD., PANASONIC CORPORATION
    Inventors: Hiroshi HAYASHI, Takahiro KAWASHIMA, Genshiro KAWACHI
  • Publication number: 20110272701
    Abstract: A thin film transistor with excellent electric characteristics, a display device having the thin film transistor, and a method for manufacturing the thin film transistor and the display device are proposed. The thin film transistor includes a gate insulating film formed over a gate electrode, a microcrystalline semiconductor film formed over the gate insulating film, a buffer layer formed over the microcrystalline semiconductor film, a pair of semiconductor films to which an impurity element imparting one conductivity type is added and which are formed over the buffer layer, and wirings formed over the pair of semiconductor films to which the impurity element imparting one conductivity type is added. A part of the gate insulating film or the entire gate insulating film, and/or a part of the microcrystalline semiconductor or the entire microcrystalline semiconductor includes an impurity element which serves as a donor.
    Type: Application
    Filed: July 21, 2011
    Publication date: November 10, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Yoshiyuki KUROKAWA, Yasuhiro JINBO, Satoshi KOBAYASHI, Daisuke KAWAE
  • Publication number: 20110241007
    Abstract: The present invention provides a light-emitting element having a structure in which the drive voltage is comparatively low and a light-emitting element in which the increase in the drive voltage over time is small. Further, the present invention provides a display device in which the drive voltage and the increase in the drive voltage over time are small and which can resist long-term use. A layer in contact with an electrode in a light-emitting element is a layer containing a P-type semiconductor or a hole-generating layer such as an organic compound layer containing a material having electron-accepting properties. The light-emitting layer is sandwiched between the hole-generating layers, and an electron-generating layer is sandwiched between the light-emitting layer and the hole-generating layer on a cathode side.
    Type: Application
    Filed: June 16, 2011
    Publication date: October 6, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Daisuke KUMAKI, Satoshi SEO
  • Patent number: 8026557
    Abstract: A semiconductor device with an increased channel length and a method for fabricating the same are provided. The semiconductor device includes: a substrate with an active region including a planar active region and a prominence active region formed on the planar active region; a gate insulation layer formed over the active region; and a gate structure including at least one gate lining layer encompassing the prominence active region on the gate insulation layer.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: September 27, 2011
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Jin-Ki Jung
  • Patent number: 8026162
    Abstract: A layer-stacked wiring made up of a microcrystalline silicon thin film and a metal thin film is provided which is capable of suppressing an excessive silicide formation reaction between the microcrystalline silicon thin film and metal thin film, thereby preventing peeling of the thin film. In a polycrystalline silicon TFT (Thin Film Transistor) using the layer-stacked wiring, the microcrystalline silicon thin film is so configured that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 60% or more of a film thickness of the microcrystalline silicon thin film amount to 15% or less of total number of crystal grains or that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 50% or less of a film thickness of the microcrystalline silicon thin film amount to 85% or more of the total number of crystal grains making up the microcrystalline silicon thin film.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: September 27, 2011
    Assignees: NEC Corporation, NEC LCD Technologies, Ltd.
    Inventors: Jun Tanaka, Hiroshi Kanoh
  • Publication number: 20110220904
    Abstract: A mask for sequential lateral solidification (SLS) which is capable of preventing an overlapping region and a diagonal stain based on a crystallization pattern of an active layer. The mask for SLS, which moves in a first direction and selectively transmits a laser beam emitted by a laser emitting device, includes slits which are formed such that the width of a slit in the first direction is smaller than the width of the slit in a second direction, which is perpendicular to the first direction. Each of the slits is tilted by a predetermined angle with respect to the first direction.
    Type: Application
    Filed: January 3, 2011
    Publication date: September 15, 2011
    Applicant: Samsung Mobile Display Co., Ltd.
    Inventors: Kwon-Hyung LEE, Cheol-Ho PARK, In-Do CHUNG, Jae-Beom CHOI
  • Publication number: 20110220895
    Abstract: The present invention makes it possible to prepare a thin film transistor fitted with a resin substrate by lowering a process temperature during formation of an oxide semiconductor, and further makes it possible to improve manufacturing efficiency and reduce variations in thin film transistor performance. Disclosed is a thin film transistor of the present invention possessing a semiconductor containing metal oxide, the semiconductor comprising a coating film made from a solution or a dispersion of a precursor, wherein the metal oxide contains indium as a first metal element, gallium or aluminum as a second metal element, and zinc or tin as a third metal element, and a ratio of the third metal element to total metal elements in the metal oxide is 25 at % or less, or 0 at %.
    Type: Application
    Filed: November 10, 2009
    Publication date: September 15, 2011
    Applicant: KONICA MINOLTA HOLDINGS, INC.
    Inventors: Katsura Hirai, Makoto Honda, Masaki Miyoshi
  • Publication number: 20110220909
    Abstract: There is provided a backplane for an organic electronic device. The backplane has a TFT substrate having a multiplicity of electrode structures thereon. There are spaces around the electrode structures and a layer of inorganic filler in the spaces. The thickness of the layer of inorganic filler is the same as the thickness of the electrode structures.
    Type: Application
    Filed: December 4, 2009
    Publication date: September 15, 2011
    Applicant: E.I. DU PONT DE NEMOURS AND COMPANY
    Inventors: Matthew Stainer, Yaw-Ming A. Tsai
  • Publication number: 20110215324
    Abstract: A thin film transistor (TFT) and a fabricating method thereof are provided. The TFT includes a channel layer, an ohmic contact layer, a dielectric layer, a source, a drain, a gate, and a gate insulating layer. The channel layer has an upper surface and a sidewall. The ohmic contact layer is disposed on a portion of the upper surface of the channel layer. The dielectric layer is disposed on the sidewall of the channel layer, and does not overlap with the ohmic contact layer. The source and the drain are disposed on portions of the ohmic contact layer and the dielectric layer. A portion of dielectric layer is not covered by the source or the drain. The gate is above or below the channel layer. The gate insulating layer is disposed between the gate and the channel layer.
    Type: Application
    Filed: May 14, 2010
    Publication date: September 8, 2011
    Applicant: AU OPTRONICS CORPORATION
    Inventors: Guang-Ren Shen, Pei-Ming Chen, Chun-Hsiun Chen, Wei-Ming Huang
  • Publication number: 20110210333
    Abstract: To realize a semiconductor device including a capacitor element capable of obtaining a sufficient capacitor without reducing an opening ratio, in which a pixel electrode is flattened in order to control a defect in orientation of liquid crystal. A semiconductor device of the present invention includes a light-shielding film formed on the thin film transistor, a capacitor insulating film formed on the light-shielding film, a conductive layer formed on the capacitor insulating film, and a pixel electrode that is formed so as to be electrically connected to the conductive layer, in which a storage capacitor element comprises the light-shielding film, the capacitor insulating film, and the conductive layer, whereby an area of a region serving as the capacitor element can be increased.
    Type: Application
    Filed: May 9, 2011
    Publication date: September 1, 2011
    Inventor: Tatsuya Arao
  • Publication number: 20110210336
    Abstract: For forming a gate electrode, a conductive film with low resistance including Al or a material containing Al as its main component and a conductive film with low contact resistance for preventing diffusion of Al into a semiconductor layer are laminated, and the gate electrode is fabricated by using an apparatus which is capable of performing etching treatment at high speed.
    Type: Application
    Filed: May 10, 2011
    Publication date: September 1, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Koji Ono, Yoshihiro Kusuyama
  • Publication number: 20110198599
    Abstract: A source-drain voltage of one of two transistors connected in series becomes quite small in a set operation (write signal), thus the set operation is performed to the other transistor. In an output operation, two transistors operate as a multi-gate transistor, therefore, a current value can be small in the output operation. In other words, a current can be large in the set operation. Therefore, the set operation can be performed rapidly without being easily influenced by an intersection capacitance and a wiring resistance which are parasitic on a wiring and the like. Further, an influence of variations between adjacent ones can be small as one same transistor is used in the set operation and the output operation.
    Type: Application
    Filed: April 25, 2011
    Publication date: August 18, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Hajime Kimura
  • Patent number: 7999262
    Abstract: A thin film transistor includes a gate electrode, a gate insulation layer on the gate electrode, source and drain electrodes formed on the gate insulation layer, a polysilicon channel layer overlapping the ohmic contact layers and on the gate insulation layer between the source and drain electrodes, ohmic contact regions over the source and drain electrodes for contacting the polysilicon channel to the source and drain electrodes, and doping layers over the source and drain electrodes.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: August 16, 2011
    Assignee: LG Display Co., Ltd.
    Inventors: Gee Sung Chae, Seung Hwan Cha
  • Publication number: 20110180789
    Abstract: Thin-film transistors are made using an organosilicate glass (OSG) as an insulator material. The organosilicate glasses may be SiO2-silicone hybrid materials deposited by plasma-enhanced chemical vapor deposition from siloxanes and oxygen. These hybrid materials may be employed as the gate dielectric, as a subbing layer, and/or as a back channel passivating layer. The transistors may be made in any conventional TFT geometry.
    Type: Application
    Filed: July 30, 2009
    Publication date: July 28, 2011
    Inventors: Lin Han, Prashant Mandlik, Sigurd Wagner
  • Publication number: 20110180797
    Abstract: It is an object of the present invention to provide a semiconductor device capable of preventing deterioration due to penetration of moisture or oxygen, for example, a light-emitting apparatus having an organic light-emitting device that is formed over a plastic substrate, and a liquid crystal display apparatus using a plastic substrate. According to the present invention, devices formed on a glass substrate or a quartz substrate (a TFT, a light-emitting device having an organic compound, a liquid crystal device, a memory device, a thin-film diode, a pin-junction silicon photoelectric converter, a silicon resistance element, or the like) are separated from the substrate, and transferred to a plastic substrate having high thermal conductivity.
    Type: Application
    Filed: January 21, 2011
    Publication date: July 28, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei Yamazaki, Toru Takayama, Junya Maruyama, Yumiko Ohno
  • Publication number: 20110156045
    Abstract: A crystal manufacturing apparatus capable of manufacturing a crystal in a desired position on a substrate is provided. A spring has one end fixed to a mount and the other end coupled to a magnetic body. The magnetic body has one end coupled to the spring and the other end coupled to a piston. A coil is wound around the magnetic body and electrically connected between a power supply circuit and a ground node (GND). The piston has a linear member inserted in a cylinder. The cylinder has a hollow columnar shape and a small hole at a bottom surface. The cylinder holds a silicon melt. A substrate is supported by an XY stage to be opposed to the small hole of the cylinder. The power supply circuit passes pulse shaped current through the coil to move the piston in an up-down direction (DR1). As a result, a droplet is discharged toward the substrate from the small hole at an initial speed of 1.02 m/s.
    Type: Application
    Filed: August 28, 2009
    Publication date: June 30, 2011
    Applicant: HIROSHIMA UNIVERSITY
    Inventors: Seiichiro Higashi, Naohiro Koba
  • Publication number: 20110156044
    Abstract: There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
    Type: Application
    Filed: February 14, 2011
    Publication date: June 30, 2011
    Applicant: SanDisk 3D LLC
    Inventors: Thomas H. Lee, Vivek Subramanian, James M. Cleeves, Andrew J. Walker, Christopher J. Petti, Igor G. Kouznetzov, Mark G. Johnson, Paul Michael Farmwald, Brad Herner
  • Patent number: 7960734
    Abstract: A finFET field effect transistor is produced by the formation of an electrical junction between the thin fin portion of semiconductor material which forms the channel of the transistor and the circuit substrate. Doping particles are implanted in the substrate through a mask which is then subsequently used to form the thin fin portion of the channel. The channel of the finFET transistor is thus electrically insulated from the circuit substrate in the same manner as in MOS integrated circuits realized from bulk silicon substrates.
    Type: Grant
    Filed: July 15, 2010
    Date of Patent: June 14, 2011
    Assignees: STMicroelectronics (Crolles 2) SAS, Interuniversitair Micro-Electronica Centrum
    Inventor: Damien Lenoble
  • Publication number: 20110121306
    Abstract: The disclosed systems and method for non-periodic pulse sequential lateral solidification relate to processing a thin film. The method for processing a thin film, while advancing a thin film in a selected direction, includes irradiating a first region of the thin film with a first laser pulse and a second laser pulse and irradiating a second region of the thin film with a third laser pulse and a fourth laser pulse, wherein the time interval between the first laser pulse and the second laser pulse is less than half the time interval between the first laser pulse and the third laser pulse. In some embodiments, each pulse provides a shaped beam and has a fluence that is sufficient to melt the thin film throughout its thickness to form molten zones that laterally crystallize upon cooling. In some embodiments, the first and second regions are adjacent to each other. In some embodiments, the first and second regions are spaced a distance apart.
    Type: Application
    Filed: May 10, 2010
    Publication date: May 26, 2011
    Applicant: THE TRUSTEES OF COLUMBIA UNIVERSITY IN THE CITY OF NEW YORK
    Inventors: James S. Im, Ui-Jin Chung, Alexander B. Limanov, Paul C. Van Der Wilt
  • Publication number: 20110114957
    Abstract: A thin film transistor (TFT) and an organic light emitting display apparatus are provided. The TFT includes: a substrate; a gate electrode on the substrate; an active layer insulated from the gate electrode; source/drain electrodes electrically connected to the active layer; a first insulating film on the source/drain electrodes; a light blocking layer on the first insulating film; and a second insulating film on the light blocking layer.
    Type: Application
    Filed: November 10, 2010
    Publication date: May 19, 2011
    Inventors: Eun-Hyun Kim, Jong-Han Jeong, Yeon-Gon Mo
  • Patent number: 7943929
    Abstract: A thin film transistor and method of fabricating the same are provided. The thin film transistor includes: a metal catalyst layer formed on a substrate, and a first capping layer and a second capping layer pattern sequentially formed on the metal catalyst layer. The method includes: forming a first capping layer on a metal catalyst layer; forming and patterning a second capping layer on the first capping layer; forming an amorphous silicon layer on the patterned second capping layer; diffusing the metal catalyst; and crystallizing the amorphous silicon layer to form a polysilicon layer. The crystallization catalyst diffuses at a uniform low concentration to control a position of a seed formed of the catalyst such that a channel region in the polysilicon layer is close to a single crystal. Therefore, the characteristics of the thin film transistor device may be improved and uniformed.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: May 17, 2011
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Jin-Wook Seo, Ki-Yong Lee, Tae-Hoon Yang, Byoung-Keon Park
  • Publication number: 20110108847
    Abstract: A thin film transistor (TFT), a method of fabricating the same, an organic light emitting diode (OLED) display device having the same, and a method of fabricating the same. The TFT includes a substrate; a buffer layer disposed on the substrate; a semiconductor layer disposed on the buffer layer; a gate insulating layer disposed on the semiconductor layer; a gate electrode disposed on the gate insulating layer and corresponding to the semiconductor layer; and source and drain electrodes insulated from the gate electrode, and electrically connected to the semiconductor layer. Here, the semiconductor layer includes a plurality of seed regions separated from each other by a distance of 50 ?m or more.
    Type: Application
    Filed: August 16, 2010
    Publication date: May 12, 2011
    Applicant: Samsung Mobile Display Co., Ltd.
    Inventor: Yong-Woo PARK
  • Patent number: 7939822
    Abstract: The present invention provides a manufacturing process using a droplet-discharging method that is suitable for manufacturing a large substrate in mass production. A photosensitive material solution of a conductive film is selectively discharged by a droplet-discharging method, selectively exposed to laser light, and developed or etched, thereby allowing only the region exposed to laser light to be left and realizing a source wiring and a drain wiring having a more microscopic pattern than the pattern itself formed by discharging. One feature of the source wiring and the drain wiring is that the source wiring and the drain wiring cross an island-like semiconductor layer and overlap it.
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: May 10, 2011
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shinji Maekawa, Hideaki Kuwabara
  • Patent number: 7939826
    Abstract: A thin film semiconductor device is provided which includes an insulating substrate, a Si thin film formed over the insulating substrate, and a transistor with the Si thin film as a channel thereof. The Si thin film includes a polycrystal where a plurality of narrow, rectangular crystal grains are arranged. A surface of the polycrystal is flat at grain boundaries thereof. Also, an average film thickness of the boundaries of crystals of the Si thin film ranges from 90 to 110% of an intra-grain average film thickness.
    Type: Grant
    Filed: October 27, 2008
    Date of Patent: May 10, 2011
    Assignee: Hitachi Displays, Ltd.
    Inventors: Shinya Yamaguchi, Mutsuko Hatano, Mitsuharu Tai, Sedng-Kee Park, Takeo Shiba
  • Publication number: 20110101366
    Abstract: Paper embedded with a semiconductor device capable of communicating wirelessly is realized, whose unevenness of a portion including the semiconductor device does not stand out and the paper is thin with a thickness of less than or equal to 130 ?m. A semiconductor device is provided with a circuit portion and an antenna, and the circuit portion includes a thin film transistor. The circuit portion and the antenna are separated from a substrate used during manufacturing, and are interposed between a flexible base and a sealing layer and protected. The semiconductor device can be bent, and the thickness of the semiconductor device itself is less than or equal to 30 ?m. The semiconductor device is embedded in a paper in a papermaking process.
    Type: Application
    Filed: January 6, 2011
    Publication date: May 5, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Yoshitaka DOZEN, Tomoyuki AOKI, Hidekazu TAKAHASHI, Daiki YAMADA, Kaori OGITA, Naoto KUSUMOTO
  • Publication number: 20110101364
    Abstract: Systems, methods, and products of processes consistent with the innovations herein relate to aspects involving crystallization of layers on substrates. In one exemplary implementation, there is provided a method of fabricating a device. Moreover, such method may include placing an amorphous/poly material on a substrate and heating the material via a sub-melt laser anneal process to transform the material into crystalline form.
    Type: Application
    Filed: July 28, 2010
    Publication date: May 5, 2011
    Inventor: Venkatraman Prabhakar
  • Publication number: 20110089425
    Abstract: A method for manufacturing an insulating film, which is used as an insulating film used for a semiconductor integrated circuit, whose reliability can be ensured even though it has small thickness, is provided. In particular, a method for manufacturing a high-quality insulating film over a substrate having an insulating surface, which can be enlarged, at low substrate temperature, is provided. A monosilane gas (SiH4), nitrous oxide (N2O), and a rare gas are introduced into a chamber to generate high-density plasma at a pressure higher than or equal to 10 Pa and lower than or equal to 30 Pa so that an insulating film is formed over a substrate having an insulating surface. After that, the supply of a monosilane gas is stopped, and nitrous oxide (N2O) and a rare gas are introduced without exposure to the air to perform plasma treatment on a surface of the insulating film.
    Type: Application
    Filed: December 16, 2010
    Publication date: April 21, 2011
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Mitsuhiro ICHIJO, Kenichi OKAZAKI, Tetsuhiro TANAKA, Takashi OHTSUKI, Seiji YASUMOTO, Shunpei YAMAZAKI
  • Publication number: 20110084283
    Abstract: A thin film transistor and a manufacturing method thereof are provided. An insulating pattern layer having at least one protrusion is formed on a substrate. Afterwards, at least one spacer and a plurality of amorphous semiconductor patterns separated from each other are formed on the insulating pattern layer. The spacer is formed at one side of the protrusion and connected between the amorphous semiconductor patterns. Later, the spacer and the amorphous semiconductor patterns are crystallized. Subsequently, the protrusion and the insulating pattern layer below the spacer are removed so that a beam structure having a plurality of corners is formed and suspended over the substrate. Then, a carrier tunneling layer, a carrier trapping layer and a carrier blocking layer are sequentially formed to compliantly wrap the corners of the beam structure. Hereafter, a gate is formed on the substrate to cover the beam structure and wrap the carrier blocking layer.
    Type: Application
    Filed: January 12, 2010
    Publication date: April 14, 2011
    Applicant: CHUNGHWA PICTURE TUBES, LTD.
    Inventors: Huang-Chung Cheng, Ta-Chuan Liao, Sheng-Kai Chen, Ying-Hui Chen, Chi-Neng Mo
  • Publication number: 20110073860
    Abstract: A thin film transistor comprising an insulating film, a gate electrode embedded in a superficial portion of the insulating film, a gate insulating film on the gate electrode and the insulating film, a semiconductor film on the gate insulating film, a channel protection film on a portion of the semiconductor film with end surfaces which have a forward tapered slope, a first electrode on the semiconductor film which mounts onto one tapered side of the channel protection film, and a second electrode on the semiconductor film which mounts onto the other tapered side of the channel protection film, where an edge of the gate electrode closest to the first electrode is offset towards the second electrode from the point where the first electrode abuts the semiconductor film.
    Type: Application
    Filed: September 21, 2010
    Publication date: March 31, 2011
    Applicant: SONY CORPORATION
    Inventors: Michihiro Kanno, Takahiro Kawamura
  • Patent number: 7915689
    Abstract: A thin film transistor, a display device, and a manufacturing method thereof. The thin film transistor includes a control electrode, a semiconductor overlapping the control electrode, and an input electrode and an output electrode disposed on or under the semiconductor and opposite to each other. The semiconductor includes a first portion disposed between the input electrode and the output electrode and having a first crystallinity, and a second portion connected with the first portion, which overlaps the input electrode or the output electrode, and having a second crystallinity. The first crystallinity is higher than the second crystallinity.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: March 29, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sung-Haeng Cho, Ki-Hun Jeong, Jun-Ho Song, Joo-Han Kim, Hyung-Jun Kim, Seung-Hwan Shim
  • Publication number: 20110068342
    Abstract: A laser method is provided for minimizing variations in transistor threshold voltages. The method supplies a wafer with a laser-crystallized active semiconductor film having a top surface with a first surface roughness. The method laser anneals the active semiconductor film, and in response to the laser annealing, melts the top surface of the active semiconductor film. The result is a top surface with a second roughness, less than the first roughness. More explicitly, the wafer active semiconductor film is crystallized using a laser with a first fluence, and then laser annealed with a second fluence, less than the first fluence. As compared with complementary metal-oxide-semiconductor field-effect (CMOSFET) thin-film transistor (TFT) structures formed in unprocessed regions of the active semiconductor film, the TFT threshold voltage standard deviation for TFTs in laser annealed portions of the active film are 60% less for n-channel and 30% less for p-channel TFTs.
    Type: Application
    Filed: September 18, 2009
    Publication date: March 24, 2011
    Inventors: Themistokles Afentakis, Robert S. Sposili, Steven R. Droes
  • Publication number: 20110068343
    Abstract: To achieve TFT having a high light-resistance characteristic with a suppressed light leak current at low cost by simplifying the manufacturing processes. The TFT basically includes: a light-shielding film formed on a glass substrate that serves as an insulating substrate; an insulating film formed on the light-shielding film; a semiconductor film formed on the insulating film; and a gate insulating film formed on the semiconductor film. Each layer of a laminate that is configured with three layers of the light-shielding film, the insulating film, and the semiconductor film is patterned simultaneously. Further, each layer of the laminate is configured with silicon or a material containing silicon.
    Type: Application
    Filed: November 26, 2010
    Publication date: March 24, 2011
    Applicant: NEC LCD TECHNOLOGIES, LTD.
    Inventor: Hiroshi TANABE
  • Patent number: 7910923
    Abstract: A semiconductor device with superior long-term reliability is disclosed that alleviates current concentration into a switch structure arranged at an outermost portion. The semiconductor device comprises hetero semiconductor regions formed of polycrystalline silicon having a band gap width different from that of a drift region and hetero-adjoined with the drift region, a gate insulation film, a gate electrode adjoined to the gate insulation film, a source electrode connected to a source contact portion of the hetero semiconductor regions and an outermost switch structure and a repeating portion switch structure with a drain electrode connected to a substrate region. In a conduction state, the outermost switch structure comprises a mechanism in which the current flowing at the outermost switch structure becomes smaller than the current flowing at the repeating portion switch structure.
    Type: Grant
    Filed: December 20, 2007
    Date of Patent: March 22, 2011
    Assignee: Nissan Motor Co., Ltd.
    Inventors: Tetsuya Hayashi, Masakatsu Hoshi, Hideaki Tanaka, Shigeharu Yamagami
  • Publication number: 20110057195
    Abstract: A thin film transistor comprises an Si-based channel having a nonlinear electron-moving path, a source and a drain disposed at both sides of the channel, a gate disposed above the channel, an insulator interposed between the channel and the gate, and a substrate supporting the channel and the source and the drain disposed at either side of the channel respectively.
    Type: Application
    Filed: November 16, 2010
    Publication date: March 10, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Huaxiang YIN, Takashi NOGUCHI, Hyuk LIM, Wenxu XIANYU, Hans S. CHO
  • Patent number: 7888682
    Abstract: A thin film transistor comprises a substrate; a semiconductor layer disposed on the substrate, the semiconductor layer having a source region, a drain region, and a channel region between the source region and the drain region; a gate insulating layer disposed on the semiconductor layer and on the substrate; a gate electrode disposed on the insulating layer over the channel region; an passivation layer disposed on the gate electrode and the gate insulating layer; a source electrode disposed in contact with upper, lower and side surfaces of the source region via a first contact hole through passivation layer, the gate insulating layer and the semiconductor layer; and a drain electrode disposed in contact with upper, lower and side surfaces of the drain region via a second contact hole through the passivation layer, the gate insulating layer and the semiconductor layer.
    Type: Grant
    Filed: December 11, 2008
    Date of Patent: February 15, 2011
    Assignee: LG Display Co., Ltd.
    Inventor: Jae-Bum Park
  • Patent number: 7879658
    Abstract: A semiconductor device includes a silicon crystal layer on an insulating layer, the silicon crystal layer containing a crystal lattice mismatch plane, a memory cell array portion on the silicon crystal layer, the memory cell array portion including memory strings, each of the memory strings including nonvolatile memory cell transistors connected in series in a first direction, the memory strings being arranged in a second direction orthogonal to the first direction, the crystal lattice mismatch plane crossing the silicon crystal along the second direction without passing under gates of the nonvolatile memory cell transistors as viewed from a top of the silicon crystal layer, or crossing the silicon crystal along the first direction with passing under gates of the nonvolatile memory cell transistors as viewed from the top of the silicon crystal layer.
    Type: Grant
    Filed: February 29, 2008
    Date of Patent: February 1, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshio Ozawa, Ichiro Mizushima, Takashi Suzuki, Hirokazu Ishida, Yoshitaka Tsunashima
  • Publication number: 20110017997
    Abstract: Semiconductor devices on a diffusion barrier coated metal substrates, and methods of making the same are disclosed. The semiconductor devices include a metal substrate, a diffusion barrier layer on the metal substrate, an insulator layer on the diffusion barrier layer, and a semiconductor layer on the insulator layer. The method includes forming a diffusion barrier layer on the metal substrate, forming an insulator layer on the diffusion barrier layer; and forming a semiconductor layer on the insulator layer. Such diffusion barrier coated substrates prevent diffusion of metal atoms from the metal substrate into a semiconductor device formed thereon.
    Type: Application
    Filed: May 28, 2010
    Publication date: January 27, 2011
    Inventors: Arvind Kamath, Michael Kocsis, Kevin McCarthy, Gloria Man Ting Wong
  • Publication number: 20110017998
    Abstract: The semiconductor device of the present invention includes a semiconductor region made of a material to which conductive impurities are added, an insulating film formed on a surface of the semiconductor region, and an electroconductive gate electrode formed on the insulating film. The gate electrode is made of a material whose Fermi level is closer to a Fermi level of the semiconductor region than a Fermi level of Si in at least a portion contiguous to the insulating film.
    Type: Application
    Filed: July 20, 2010
    Publication date: January 27, 2011
    Applicant: ROHM CO., LTD.
    Inventors: Yuki NAKANO, Ryota Nakamura, Katsuhisa Nagao
  • Patent number: 7863113
    Abstract: A transistor for active matrix display and a method for producing the transistor (1). The transistor (1) includes a microcrystalline silicon film (5) and an insulator (3). The crystalline fraction of the microcrystalline silicon film (5) is above 80%. According to the invention, the transistor (1) includes a plasma treated interface (4) located between the insulator (3) and the microcrystalline silicon film (5) so that the transistor (1) has a linear mobility equal or superior to 1.5 cm2V?1s?1, shows threshold voltage stability and wherein the microcrystalline silicon film (5) includes grains (6) whose size ranges between 10 nm and 400 nm. The invention concerns as well a display unit having a line-column matrix of pixels that are actively addressed, each pixel comprising at least a transistor as described above.
    Type: Grant
    Filed: February 6, 2004
    Date of Patent: January 4, 2011
    Assignees: Centre National de la Recherche Scientifique, Ecole Polytechnique
    Inventors: Pere Roca I Cabarrocas, RĂ©gis Vanderhaghen, Bernard Drevillon
  • Publication number: 20100327285
    Abstract: Disclosed is a method of manufacturing a semiconductor device including: forming a photothermal conversion layer in a second area where a semiconductor layer is formed other than a first area where line is formed; and heating the semiconductor layer with the photothermal conversion layer by irradiating light on the first area and the second area.
    Type: Application
    Filed: June 22, 2010
    Publication date: December 30, 2010
    Applicant: Casio Computer Co., Ltd.
    Inventors: Kazuto YAMAMOTO, Katsuhiko Morosawa
  • Publication number: 20100314624
    Abstract: The invention relates to a nonvolatile semiconductor memory device including a semiconductor layer which has a source region, a drain region, and a channel forming region which is provided between the source region and the drain region; and a first insulating layer, a first gate electrode, a second insulating layer, and a second gate electrode which are layered over the semiconductor layer in that order. Part or all of the source and drain regions is formed using a metal silicide layer. The first gate electrode contains a noble gas element.
    Type: Application
    Filed: August 24, 2010
    Publication date: December 16, 2010
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventor: Kengo AKIMOTO
  • Patent number: 7851807
    Abstract: A layer-stacked wiring made up of a microcrystalline silicon thin film and a metal thin film is provided which is capable of suppressing an excessive silicide formation reaction between the microcrystalline silicon thin film and metal thin film, thereby preventing peeling of the thin film. In a polycrystalline silicon TFT (Thin Film Transistor) using the layer-stacked wiring, the microcrystalline silicon thin film is so configured that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 60% or more of a film thickness of the microcrystalline silicon thin film amount to 15% or less of total number of crystal grains or that its crystal grains each having a length of the microcrystalline silicon thin film in a direction of a film thickness being 50% or less of a film thickness of the microcrystalline silicon thin film amount to 85% or more of the total number of crystal grains making up the microcrystalline silicon thin film.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: December 14, 2010
    Assignee: NEC LCD Technologies, Ltd.
    Inventors: Jun Tanaka, Hiroshi Kanoh
  • Publication number: 20100295053
    Abstract: The present invention provides a thin film transistor substrate and a display device in which a decrease in the dry etching rate of a source electrode and drain electrode is not caused; no etching residues are generated; and a barrier metal can be eliminated between a semiconductor layer and metal wires such as the source and drain electrodes. The present invention is a thin film transistor substrate having a semiconductor layer 1, a source electrode 2, a drain electrode 3, and a transparent conductive film 4, in which the source electrode 2 and drain electrode 3 are formed by patterning by means of dry etching and comprises an Al alloy thin film comprising 0.1 to 1.5 atom % of Si and/or Ge, 0.1 to 3.0 atom % of Ni and/or Co, and 0.1 to 0.5 atom % of La and/or Nd, and the thin film transistor is directly connected with the semiconductor layer 1.
    Type: Application
    Filed: January 15, 2009
    Publication date: November 25, 2010
    Applicant: Kabushiki Kaisha Kobe Seiko Sho (Kobe Steel, Ltd.)
    Inventors: Mototaka Ochi, Nobuyuki Kawakami, Katsufumi Tomihisa, Hiroshi Goto