Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of 10 nm or less. This method further comprises removing at least a portion of the Ge layer to form a void beneath the Si layer, and filling the void at least partially with a dielectric material. In this way, the semiconductor layer becomes an extremely thin semiconductor-on-insulator layer. In one embodiment, after the void is filled with the dielectric material, in-situ doped source and drain regions are grown on the semiconductor layer. In one embodiment, the method further comprises annealing said source and drain regions to form doped extension regions in the semiconductor layer.

Abstract: A thin film transistor includes a layer structure having a gate electrode, a gate insulation layer and a channel layer. A source line may contact the channel layer, and may extend along a direction crossing over the gate electrode. The source line may partially overlap the gate electrode so that both sides of the source line overlapping the gate electrode may be entirely positioned between both sides of the gate electrode. A drain line may make contact with the channel layer and may be spaced apart from the source line by a channel length. The drain line may have a structure symmetrical to that of the source line. Overlap areas among the gate electrode, the source line and the drain line may be reduced, so that the thin film transistor may ensure a high cut-off frequency.

Abstract: A thin film transistor (TFT) comprises; an active layer formed on a substrate; a gate insulating layer formed on the active layer; a gate electrode including a first gate region and a second gate region, formed on portions of the gate insulating layer and spaced apart with a separation region interposed therebetween; an interlayer insulating layer formed on the gate insulating layer and the gate electrode, and having an opening formed to expose portions of the gate insulating layer and the gate electrode around the separation region; a gate connection electrode formed on the interlayer insulating layer and connected to the first gate region and the second gate region through the opening; and source and drain electrodes formed on the interlayer insulating layer. The TFT and the OLED display device have excellent driving margin without a spatial loss.

Abstract: On each of wiring conversion parts connected to a first conductive film and a second conductive film each functioning as a wiring, a first transparent conductive film does not cover an end surface of the second conductive film in proximity to a corner of the first transparent conductive film, and has a portion covering the end surface of the second conductive film on a portion other than the proximity of the corners. A second transparent conductive film as an upper layer of the first transparent conductive film is connected to the first conductive film and the second conductive film, so that the first conductive film and the second conductive film are electrically connected.

Abstract: A thin-film transistor array substrate and a fabrication method thereof according to an embodiment of the present invention are disclosed to form an interlayer insulating layer, thereby reducing a failure occurred during the process subsequent to a gate electrode. The thin-film transistor disclosed according to the present invention may include a substrate, a gate electrode formed on the substrate, a planarized insulating layer formed at a lateral surface portion of the gate electrode and at an upper portion of the substrate, a gate insulating layer formed on the planarized insulating layer containing an upper portion of the gate electrode, an active layer formed at an upper portion of the planarized insulating layer located at an upper side of the gate electrode, and a source electrode and a drain electrode formed on the active layer and separated from each other based on a channel region.

Abstract: An extremely-thin silicon-on-insulator transistor includes a buried oxide layer above a substrate. The buried oxide layer, for example, has a thickness that is less than 50 nm. A silicon layer is above the buried oxide layer. A gate stack is on the silicon layer includes at least a gate dielectric formed on the silicon layer and a gate conductor formed on the gate dielectric. A gate spacer has a first part on the silicon layer and a second part adjacent to the gate stack. A first raised source/drain region and a second raised source/drain region each have a first part that includes a portion of the silicon layer and a second part adjacent to the gate spacer. At least one embedded stressor is formed at least partially within the substrate that imparts a predetermined stress on a silicon channel region formed within the silicon layer.

Abstract: There is provided a method for manufacturing a flexible semiconductor device. The method of the present invention comprises the steps of: (A) providing a metal foil; (B) forming an insulating layer on the metal foil, the insulating layer having a portion serving as a gate insulating film; (C) forming a supporting substrate on the insulating layer; (D) etching away a part of the metal foil to form a source electrode and a drain electrode therefrom; (E) forming a semiconductor layer in a clearance portion located between the source electrode and the drain electrode by making use of the source and drain electrodes as a bank member; and (F) forming a resin film layer over the insulating layer such that the resin film layer covers the semiconductor layer, the source electrode and the drain electrode. In the step (F), a part of the resin film layer interfits with the clearance portion located between the source and drain electrodes.

Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of 10 nm or less. This method further comprises removing at least a portion of the Ge layer to form a void beneath the Si layer, and filling the void at least partially with a dielectric material. In this way, the semiconductor layer becomes an extremely thin semiconductor-on-insulator layer. In one embodiment, after the void is filled with the dielectric material, in-situ doped source and drain regions are grown on the semiconductor layer. In one embodiment, the method further comprises annealing said source and drain regions to form doped extension regions in the semiconductor layer.

Abstract: A thin film field effect transistor is disclosed which provides improved time-based channel stability. The field effect transistor includes first and second disordered semiconductor layers separated by an insulator. In an embodiment a carrier injection terminal is provided in a thin semiconductor layer closest to the gate terminal. An electric field is established in the thin semiconductor layer. At sufficient field strength, the electric field extends into the second semiconductor layer, which is in contact with the source and drain terminals. At sufficient field strength a channel is established in the second semiconductor layer, permitting current to flow between source and drain terminals. Above a certain gate voltage, there is sufficient free charge is induced in the first semiconductor layer so that the field does not extend into the second semiconductor, effectively shutting off current between source and drain. Single-device transition detection (as well as other applications) may be obtained.

Abstract: Disclosed is a method of fabricating a display device that includes forming a buffer layer; forming a gate electrode of extrinsic polycrystalline silicon, a gate insulating layer, an active layer of intrinsic polycrystalline silicon and an auxiliary active layer of intrinsic amorphous silicon on the buffer layer; forming an ohmic contact layer of extrinsic amorphous silicon and contacting the auxiliary active layer, source and drain electrodes and a data line; patterning a first passivation layer, an insulating interlayer and the gate insulating layer to form a gate contact hole exposing the gate electrode; forming a gate line on the first passivation layer, made of a metal material, and contacting the gate electrode through the gate contact hole; forming a second passivation layer on the gate line; patterning the first and second passivation layers to form a drain contact hole exposing the drain electrode; and forming a pixel electrode on the second passivation layer in the pixel region and contacting the dr

Abstract: A MOSFET device is formed on top of a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness ranging from 3 nm to 20 nm. A stair-shape raised extension, a raised source region and a raised drain region (S/D) are formed on top of the SOI substrate. The thinner raised extension region abuts at a thin gate sidewall spacer, lowering the extension resistance without significantly increasing the parasitic resistance. A single epitaxial growth forms the thinner raised extension and the thicker raised S/D preferably simultaneously, reducing the fabrication cost as well as the contact resistance between the raised S/D and the extension. A method of forming the aforementioned MOSFET device is also provided.

Abstract: A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.

Abstract: A thin film transistor includes a layer structure having a gate electrode, a gate insulation layer and a channel layer. A source line may contact the channel layer, and may extend along a direction crossing over the gate electrode. The source line may partially overlap the gate electrode so that both sides of the source line overlapping the gate electrode may be entirely positioned between both sides of the gate electrode. A drain line may make contact with the channel layer and may be spaced apart from the source line by a channel length. The drain line may have a structure symmetrical to that of the source line. Overlap areas among the gate electrode, the source line and the drain line may be reduced, so that the thin film transistor may ensure a high cut-off frequency.

Abstract: The invention relates to a memory cell having an FET transistor with a source, a drain and a floating body between the source and the drain, and an injector that can be controlled to inject a charge into the floating body of the FET transistor. The injector includes a bipolar transistor having an emitter, a base and a collector formed by the body of the FET transistor. Specifically, in the memory cell, the emitter of the bipolar transistor is arranged so that the source of the FET transistor serves as the base for the bipolar transistor. The invention also includes a memory array comprising a plurality of memory cells according to the first aspect of the invention, and to methods of controlling such memory cells.

Abstract: A method of forming a SOI substrate, diodes in the SOI substrate and electronic devices in the SOI substrate and an electronic device formed using the SOI substrate. The method of forming the SOI substrate includes forming an oxide layer on a silicon first substrate; ion-implanting hydrogen through the oxide layer into the first substrate, to form a fracture zone in the substrate; forming a doped dielectric bonding layer on a silicon second substrate; bonding a top surface of the bonding layer to a top surface of the oxide layer; thinning the first substrate by thermal cleaving of the first substrate along the fracture zone to form a silicon layer on the oxide layer to formed a bonded substrate; and heating the bonded substrate to drive dopant from the bonding layer into the second substrate to form a doped layer in the second substrate adjacent to the bonding layer.

Abstract: A semiconductor device and a method of fabricating a semiconductor device are disclosed. In one embodiment, the method comprises providing a semiconductor substrate, epitaxially growing a Ge layer on the substrate, and epitaxially growing a semiconductor layer on the Ge layer, where the semiconductor layer has a thickness of 10 nm or less. This method further comprises removing at least a portion of the Ge layer to form a void beneath the Si layer, and filling the void at least partially with a dielectric material. In this way, the semiconductor layer becomes an extremely thin semiconductor-on-insulator layer. In one embodiment, after the void is filled with the dielectric material, in-situ doped source and drain regions are grown on the semiconductor layer. In one embodiment, the method further comprises annealing said source and drain regions to form doped extension regions in the semiconductor layer.

Abstract: Solutions for forming an extremely thin semiconductor-on-insulator (ETSOI) layer are disclosed. In one embodiment, a method includes providing a wafer including a plurality of semiconductor-on-insulator (SOI) layer regions separated by at least one shallow trench isolation (STI); amorphizing the plurality of SOI layer regions by implanting the plurality of SOI layer regions with an implant species; and removing a portion of the amorphized SOI layer region to form at least one recess in the amorphized SOI layer region.

Abstract: A method of fabricating a semiconductor device is provided. The method forms a fin arrangement on a semiconductor substrate, the fin arrangement comprising one or more semiconductor fin structures. The method continues by forming a gate arrangement overlying the fin arrangement, where the gate arrangement includes one or more adjacent gate structures. The method proceeds by forming an outer spacer around sidewalls of each gate structure. The fin arrangement is then selectively etched, using the gate structure and the outer spacer(s) as an etch mask, resulting in one or more semiconductor fin sections underlying the gate structure(s). The method continues by forming a stress/strain inducing material adjacent sidewalls of the one or more semiconductor fin sections.

Abstract: A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.

Abstract: A method of forming a SOI substrate, diodes in the SOI substrate and electronic devices in the SOI substrate and an electronic device formed using the SOI substrate. The method of forming the SOI substrate includes forming an oxide layer on a silicon first substrate; ion-implanting hydrogen through the oxide layer into the first substrate, to form a fracture zone in the substrate; forming a doped dielectric bonding layer on a silicon second substrate; bonding a top surface of the bonding layer to a top surface of the oxide layer; thinning the first substrate by thermal cleaving of the first substrate along the fracture zone to form a silicon layer on the oxide layer to formed a bonded substrate; and heating the bonded substrate to drive dopant from the bonding layer into the second substrate to form a doped layer in the second substrate adjacent to the bonding layer.

Abstract: A semiconductor device which includes: a semiconductor layer formed over an insulating layer over a semiconductor substrate; a gate electrode disposed over the semiconductor layer through a gate insulator; a sidewall insulator formed along the gate insulating film and a sidewall of the gate electrode; a source/drain layer including an alloy layer whose bottom surface is in contact with the insulating layer; and an impurity-doped layer which is segregated in a self-aligned manner in an interface between the alloy layer and the semiconductor layer and has a face for junction with a channel region formed along a crystal orientation plane of the semiconductor layer.

Abstract: To provide a semiconductor device which achieves a high ON current and a low OFF current at the same time, and a fabrication method thereof. A semiconductor device of the present invention includes a glass substrate 1, an island-shaped semiconductor layer 4 which includes a first region 4c, a second region 4a, and a third region 4c, a source region 5a and a drain region 5b, a source electrode 6a, a drain electrode 6b, and a gate electrode 2 for controlling the conductivity of the first region 4c. The upper surface of the first region 4c is closer to the glass substrate 1 than the upper surfaces of ends of the second region 4a and the third region 4b adjacent to the first region 4c are. The distances between the upper surfaces of the ends of the second region 4a and the third region 4b and the upper surface of the first region 4c along the thickness direction of the semiconductor layer 4 are each independently not less than one time and not more than seven times the thickness of the first region 4b.

Abstract: To provide a method for manufacturing a large semiconductor device which easily operates normally and has excellent current characteristics. A first single-crystal semiconductor layer is provided over an insulating substrate. Then, the first single-crystal semiconductor layer is processed into an island shape. After that, a second single-crystal semiconductor layer is provided over the insulating substrate so as to overlap with part of a region where the first single-crystal semiconductor layer is provided. After that, the second single-crystal semiconductor layer is processed into an island shape. Thus, defects at joint portions in the case of providing the single-crystal semiconductor layers can be reduced.

Abstract: A thin film transistor in which deterioration at initial operation is not likely to be caused and a manufacturing method thereof. A transistor which includes a gate insulating layer at least whose uppermost surface is a silicon nitride layer, a semiconductor layer over the gate insulating layer, and a buffer layer over the semiconductor layer and in which the concentration of nitrogen in the vicinity of an interface between the semiconductor layer and the gate insulating layer, which is in the semiconductor layer is lower than that of the buffer layer and other parts of the semiconductor layer. Such a thin film transistor can be manufactured by exposing the gate insulating layer to an air atmosphere and performing plasma treatment on the gate insulating layer before the semiconductor layer is formed.

Abstract: A thin film transistor whose threshold voltage can be controlled and which has a favorable switching characteristic is provided. The thin film transistor includes a first gate electrode layer; a semiconductor layer; a first gate insulating layer provided between the first gate electrode layer and the semiconductor layer; source electrode and drain electrode layers which are provided over the semiconductor layer; a conductive layer covered by the first gate insulating layer and the semiconductor layer and provided so as to overlap with part of the first gate electrode layer; a second gate insulating layer provided so as to cover at least a back channel portion of the semiconductor layer; and a second gate electrode layer provided over the second gate insulating layer so as to overlap with the back channel portion of the semiconductor layer.

Abstract: In one embodiment, the present invention includes a double gate transistor having a silicon fin formed on a buried oxide layer and first and second insulation layers formed on a portion of the silicon fin, where at least the second insulation layer has a pair of portions extending onto respective first and second portions of the silicon fin to each act as a self-aligned spacer structure. Other embodiments are described and claimed.

Abstract: A semiconductor device includes a single crystal silicon substrate an insulating layer partially formed on the single crystal silicon substrate, a single crystal silicon layer formed on the single crystal silicon substrate and the insulating layer, and containing a defect layer resulting from an excessive group IV element, and a plurality of first gate structures for memory cells, each including a first gate insulating film formed on the single crystal silicon layer, a charge storage layer formed on the first gate insulating film, a second gate insulating film formed on the charge storage layer, and a control gate electrode formed on the second gate insulating film.

Abstract: A poly-silicon thin film transistor array substrate includes a gate line and a gate electrode over a substrate, a semiconductor layer having source/drain regions doped with impurity ions, a data line crossing the gate line, and source/drain electrodes connected to the source/drain regions, and a pixel electrode connected to the drain electrode, wherein the semiconductor layer is poly-silicon except for a amorphous silicon region below the gate line.

Abstract: A floating body dynamic random access memory (DRAM) structure has a shallow source (first source portion) and a deep source (second source portion), of which the deep source is thicker. A portion of the floating body extends beneath the shallow source to provide extra capacitance. Optionally, the portion of the floating body beneath the shallow source may be more heavily doped than the depletion zone of the body to further enhance the capacitance. Also, by forming a raised portion of the source without raising the drain, the same implantation energy may be used to dope the raised source and the regular drain. The resulting floating body DRAM structure has an enhanced source to floating body capacitance and stores more charges. Operating margins for write and sense operations are increased and the performance and stability of the floating body DRAM are enhanced.

Abstract: A method of trimming hard mask is provided. The method includes providing a substrate, a hard mask layer, and a tri-layer stack on the substrate. The tri-layer stack includes a top photo resist layer, a silicon photo resist layer, and a bottom photo resist layer. The top photo resist layer, the silicon photo resist layer, the bottom photo resist layer, and the hard mask layer are patterned sequentially. A trimming process is performed on the hard mask layer. The bottom photo resist layer of the present invention is thinner and loses some height in the etching process, so the bottom photo resist layer will not collapse.

Abstract: A method of manufacturing an electronic device comprising a thin film transistor (42), comprises forming a hydrogen-containing layer (22) over a semiconductor layer (10;20), irradiating the hydrogen-containing layer so as to hydrogenate the semiconductor layer, and then forming electrodes (24;26,28) over the semiconductor layer. A short diffusion length and direct path is provided for the hydrogen thus allowing rapid hydrogenation of the semiconductor layer using relatively few, high-fluence laser pulses. The supporting substrate (12) is not heated significantly making the method particularly useful for TFTs on polymer substrates. Crystallisation and hydrogenation of the semiconductor layer can be executed in the same irradiation step.

Abstract: A nonvolatile memory cell is disclosed, having first and second semiconductor islands at the same horizontal level and spaced a predetermined distance apart, the first semiconductor island providing a control gate and the second semiconductor island providing source and drain terminals; a gate dielectric layer on at least part of the first semiconductor island; a tunneling dielectric layer on at least part of the second semiconductor island; a floating gate on at least part of the gate dielectric layer and the tunneling dielectric layer; and a metal layer in electrical contact with the control gate and the source and drain terminals. In one advantageous embodiment, the nonvolatile memory cell may be manufactured using an “all-printed” process technology.