Abstract: An electronic device is provided. The electronic device includes a housing, a display viewed through at least a portion of a front surface of the housing, a rear cover disposed on a rear surface of the housing, a first electrode disposed on a lateral surface of the housing, and second and third electrodes disposed at different positions on the rear cover. The first electrode, the second electrode, and the third electrode may include a conductive material that is a compound containing titanium (Ti), aluminum (Al), chromium (Cr), silicon (Si), carbon (C), and nitrogen (N).

Abstract: A display apparatus includes: a substrate; a display unit disposed on the substrate; a barrier unit disposed between the substrate and the display unit; and a buffer unit disposed between the barrier unit and the display unit, wherein a sum of a thickness of the barrier unit and a thickness of the buffer unit is in the range from 0.9 ?m to 3 ?m.

Abstract: A method of fabricating a semiconductor structure having multiple semiconductor device layers is provided. The method comprises providing a bulk substrate and growing a first channel material on the bulk substrate wherein the lattice constant of the first channel material is different from the lattice constant of the bulk substrate to introduce strain to the first channel material. The method further comprises fabricating a first semiconductor device layer on the bulk substrate with the strained first channel material, fabricating a buffer layer comprising dielectric material with a blanket top surface above the first semiconductor layer, bonding to the blanket top surface a bottom surface of a second substrate comprising a buried oxide with a second channel material above the buried oxide, and fabricating a second semiconductor device layer on the second substrate.

Abstract: A fingerprint sensor includes: a thin film transistor disposed on a substrate; a first insulating layer disposed on the thin film transistor; a first sensing electrode disposed on the first insulating layer and connected to the thin film transistor; a second insulating layer disposed on the first sensing electrode and including an opening exposing the first sensing electrode; a sensing semiconductor layer disposed in the opening of the second insulating layer and on the first sensing electrode, and including an N-type semiconductor layer, an I-type semiconductor layer, and a P-type semiconductor layer, and a second sensing electrode disposed on the sensing semiconductor layer. An upper surface of the sensing semiconductor layer and an upper surface of the second insulating layer are coplanar.

Abstract: Embodiments relate to a display device including pixels that compensate a threshold voltage of a driving transistor using the body effect. Pixel data for the driving transistor increases the source-bulk voltage of the driving transistor during a compensation period as a result of the body effect. A separate reference voltage is not received at the pixel for the purpose of compensating the threshold voltage of the driving transistor. The increased source-bulk voltage is then used in an emission period of the pixel to compensate for the threshold voltage of the driving transistor.

Abstract: Various embodiments of the present invention provide for systems and apparatus directed toward using a contact lens and deflection optics to process display information and non-display information. In one embodiment of the invention, a display panel assembly is provided, comprising: a transparent substrate that permits light to pass through substantially undistorted; a reflector disposed on the transparent substrate; and a display panel aimed toward the reflector and substantially away from a human visual system, wherein the reflector reflects light emitted from the display panel toward the human visual system. The reflector may comprise a narrow band reflector or a polarization reflector.

Abstract: A radio frequency (RF) semiconductor device may include a semiconductor-on-insulator substrate, and an RF ground plane layer on the semiconductor-on-insulator substrate including a conductive superlattice. The conductive superlattice may include stacked groups of layers, with each group of layers comprising stacked doped base semiconductor monolayers defining a doped base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent doped base semiconductor portions. The RF semiconductor device may further include a body above the RF ground plane layer, spaced apart source and drain regions adjacent the body and defining a channel region in the body, and a gate overlying the channel region.

Abstract: Methods of forming contacts for source/drain regions and a contact plug for a gate stack of a finFET device are disclosed herein. Methods include etching a contact opening through a dielectric layer to expose surfaces of a first source/drain contact and repairing silicon oxide structures along sidewall surfaces of the contact opening and along planar surfaces of the dielectric layer to prevent selective loss defects from occurring during a subsequent selective deposition of conductive fill materials and during subsequent etching of other contact openings. The methods further include performing a selective bottom-up deposition of conductive fill material to form a second source/drain contact. According to some of the methods, once the second source/drain contact has been formed, the contact plug may be formed over the gate stack.

Abstract: The present invention relates to copolymers, particularly to copolymers comprising a photoactive unit, the copolymers being particularly suitable for ophthalmic devices. The copolymers include one or more different polymer units in addition to the photoactive unit, such as polymerized units derived from ethylene, propylene, an acrylate, a methacrylate, or a styrene.

Abstract: A transistor structure is disclosed. The transistor structure includes a dielectric layer that has a thinner portion over a first doped well and a second doped well, and a thicker portion adjacent the thinner portion and over the second doped well. The thicker portion has a height greater than the thinner portion above the doped wells. The transistor includes a first gate structure on the thinner portion and a second gate structure on the thicker portion of the dielectric layer. The transistor may include a third gate structure on the thicker portion.

Abstract: An object is to provide a highly reliable light emitting device which is thin and is not damaged by external local pressure. Further, another object is to manufacture a light emitting device with a high yield by preventing defects of a shape and characteristics due to external stress in a manufacture process. A light emitting element is sealed between a first structure body in which a fibrous body is impregnated with an organic resin and a second structure body in which a fibrous body is impregnated with an organic resin, whereby a highly reliable light emitting device which is thin and has intensity can be provided. Further, a light emitting device can be manufactured with a high yield by preventing defects of a shape and characteristics in a manufacture process.

Abstract: A system is provided for maintaining a safe operating area while also providing a suitable forward bias voltage to drive a laser diode. The system can monitor a voltage that is applied to a laser diode driver using a threshold that is based on the fabrication process of the laser diode driver. For example, a system can utilize a first threshold for a laser diode driver that is fabricated utilizing a 10 nm process and utilize a second threshold for another laser diode driver that is fabricated utilizing a 20 nm process. The threshold can also be based on a color of the laser or a desired operation mode. The system can monitor a voltage applied to a laser diode using different thresholds while controlling a bleed current to ensure that the laser diode is forward biased while mitigating the risk of silicon breakdown of the laser diode driver.

Abstract: When a semiconductor device including a transistor in which a gate electrode layer, a gate insulating film, and an oxide semiconductor film are stacked and a source and drain electrode layers are provided in contact with the oxide semiconductor film is manufactured, after the formation of the gate electrode layer or the source and drain electrode layers by an etching step, a step of removing a residue remaining by the etching step and existing on a surface of the gate electrode layer or a surface of the oxide semiconductor film and in the vicinity of the surface is performed. The surface density of the residue on the surface of the oxide semiconductor film or the gate electrode layer can be 1×1013 atoms/cm2 or lower.

Abstract: A curved screen and a display device are disclosed. The curved screen includes a first substrate, a second substrate, and a liquid crystal layer disposed between the first and second substrates. The curved screen is bent and concave along the first substrate. The first substrate includes a substrate and a planarization layer disposed on a concave side of the substrate. A plurality of grooves are defined in the planarization layer and arranged at intervals along a direction of a bending edge of the curved screen, and extend in parallel along a direction of a non-bending edge. The depth of each groove before bending is greater than after bending.

Abstract: By using a conductive layer including Cu as a long lead wiring, increase in wiring resistance is suppressed. Further, the conductive layer including Cu is provided in such a manner that it does not overlap with the oxide semiconductor layer in which a channel region of a TFT is formed, and is surrounded by insulating layers including silicon nitride, whereby diffusion of Cu can be prevented; thus, a highly reliable semiconductor device can be manufactured. Specifically, a display device which is one embodiment of a semiconductor device can have high display quality and operate stably even when the size or definition thereof is increased.

Abstract: A dimming glass includes: a first base substrate and a second base substrate that are oppositely disposed, a dye liquid crystal layer disposed between the first base substrate and the second base substrate, and at least one temperature sensor disposed between the first base substrate and the second base substrate. The at least one temperature sensor is configured to detect a temperature of the dye liquid crystal layer.

Abstract: The disclosure relates to a method for making a photocatalytic structure, the method comprising: providing a carbon nanotube structure comprising a plurality of carbon nanotubes intersected with each other; a plurality of openings being defined by the plurality of carbon nanotubes; forming a photocatalytic active layer on the surface of the carbon nanotube structure; applying a metal layer pre-form on the surface of the photocatalytic active layer; and annealing the metal layer pre-form.

Abstract: Provided are a thin film transistor array substrate and an electronic device including the same. The thin film transistor array substrate includes a first active layer disposed on a substrate, a first gate insulating film disposed on the first active layer, a first gate electrode disposed on the first gate insulating film to overlap a part of the first active layer, a first insulating film disposed on the first gate electrode, a second active layer disposed on the first insulating film to overlap the first active layer and the first gate electrode, a second gate insulating film disposed on the second active layer, and a second gate electrode disposed on the second gate insulating film to overlap a part of the second active layer. The first gate electrode and the second gate electrode overlap each other, and thus it is possible to reduce an area occupied by transistors.

Abstract: A method of manufacturing a semiconductor structure includes the following operations. A wafer includes a crystal orientation represented by a family of Miller indices comprising <lmn>, wherein l2+m2+n2=1. A first chip and a second chip are over the wafer. A first edge of the first chip and a second edge of the second chip are adjacent to each other. A boundary extending in a direction between the first edge and the second edge is formed. A first included angle between the first direction and the crystal orientation is greater than or equal to 0 degree and less than 45 degrees.

Abstract: A RAMO4 substrate that does not easily crack during or after the formation of group III nitride crystal includes a single crystal represented by general formula RAMO4 (wherein R represents one or more trivalent elements selected from the group consisting of Sc, In, Y, and lanthanoid elements, A represents one or more trivalent elements selected from the group consisting of Fe(III), Ga, and Al, and M represents one or more divalent elements selected from the group consisting of Mg, Mn, Fe(II), Co, Cu, Zn, and Cd). The RAMO4 substrate has a crystal plane with a curvature radius r of 52 m or more, and a square value of correlation coefficient ? of 0.81 or more. The curvature radius r is calculated as an absolute value from X-ray peak position ?i and measurement position Xi after the measurements of X-ray peak positions ?i at a plurality of positions Xi lying on a straight line passing through the center of the RAMO4 substrate.

Abstract: An object is to provide a semiconductor device with high aperture ratio or a manufacturing method thereof. Another object is to provide semiconductor device with low power consumption or a manufacturing method thereof. A light-transmitting conductive layer which functions as a gate electrode, a gate insulating film formed over the light-transmitting conductive layer, a semiconductor layer formed over the light-transmitting conductive layer which functions as the gate electrode with the gate insulating film interposed therebetween, and a light-transmitting conductive layer which is electrically connected to the semiconductor layer and functions as source and drain electrodes are included.

Abstract: According to one embodiment, a semiconductor device manufacturing method includes depositing a silicon film above a semiconductor substrate, forming an insulating film which includes silicon oxide or silicon nitride on the silicon film, forming a physical guide having a depressed portion above the insulating film, forming a directed self-assembly material layer which includes a first polymer and a second polymer in the depressed portion of the physical guide, phase-separating the directed self-assembly material layer into a first region which includes the first polymer and a second region which includes the second polymer, removing the second region, processing the insulating film by using the physical guide and the first region as masks, and transferring a pattern corresponding to the second region to the insulating film. Further, the silicon film is processed by using the pattern transferred onto the insulating film as a mask.

Abstract: To provide an oxide semiconductor film including a low-resistance region, which can be applied to a transistor. To provide a transistor including the oxide semiconductor film, which can perform at high speed. To provide a high-performance semiconductor device including the transistor including the oxide semiconductor film, which can perform at high speed, with high yield. A film having a reducing property is formed over the oxide semiconductor film. Next, part of oxygen atoms are transferred from the oxide semiconductor film to the film having a reducing property. Next, an impurity is added to the oxide semiconductor film through the film having a reducing property and then, the film having a reducing property is removed, so that a low-resistance region is formed in the oxide semiconductor film.

Abstract: Disclosed are polymer-based dielectric compositions (e.g., formulations) and materials (e.g. films) and associated devices. The polymers generally include photocrosslinkable pendant groups; for example, the polymers can include one or more coumarin-containing pendant groups.

Abstract: A method of manufacturing an array substrate for a fringe field switching mode liquid crystal display includes: forming an auxiliary insulating layer on a second passivation layer and having a first thickness; forming first and second photoresist patterns on the auxiliary insulating layer and having second and third thicknesses, respectively, the second thickness greater than the third thickness; etching the auxiliary insulating layer, the second passivation layer and a first passivation layer to form a drain contact hole; performing an ashing to remove the second photoresist pattern and expose the auxiliary insulating layer therebelow; performing a dry etching to remove the auxiliary insulating layer not covered by the first photoresist pattern and expose the first passivation layer and to form an insulating pattern below the first photoresist pattern, the insulating pattern and the first photoresist pattern forming an undercut shape; forming a transparent conductive material layer having a fourth thickness

Abstract: A thin film transistor substrate and a method for fabricating the same are disclosed. A thin film transistor substrate includes a substrate comprising a plurality of grooves having different depths, respectively, to have a multi-step structure; gate and data lines alternatively crossed in the grooves to form a plurality of pixel areas; thin film transistors formed in the grooves of the substrate to be formed in cross portion of the gate and data lines, wherein active layers of the thin transistors are formed along the gate lines and gate electrodes, the active layers separated from active layers of neighboring pixel areas with the data line located there between.

Abstract: A semiconductor device in which improvement of a property of holding stored data can be achieved. Further, power consumption of a semiconductor device is reduced. A transistor in which a wide-gap semiconductor material capable of sufficiently reducing the off-state current of a transistor (e.g., an oxide semiconductor material) in a channel formation region is used and which has a trench structure, i.e., a trench for a gate electrode and a trench for element isolation, is provided. The use of a semiconductor material capable of sufficiently reducing the off-state current of a transistor enables data to be held for a long time. Further, since the transistor has the trench for a gate electrode, the occurrence of a short-channel effect can be suppressed by appropriately setting the depth of the trench even when the distance between the source electrode and the drain electrode is decreased.

Abstract: Semiconductor devices having germanium active layers with underlying parasitic leakage barrier layers are described. For example, a semiconductor device includes a first buffer layer disposed above a substrate. A parasitic leakage barrier is disposed above the first buffer layer. A second buffer layer is disposed above the parasitic leakage barrier. A germanium active layer is disposed above the second buffer layer. A gate electrode stack is disposed above the germanium active layer. Source and drain regions are disposed above the parasitic leakage barrier, on either side of the gate electrode stack.

Abstract: A semiconductor device comprises a thin film transistor provided over a substrate having an insulating surface, and an electrode penetrating the substrate. The thin film transistor is provided between a first structural body and a second structural body, which has a higher rigidity than the first structural body, which serve as protectors because the structural bodies have resistance to a pressing force such as a tip of a pen or bending stress applied from outside so malfunction due to the pressing force and the bending stress can be prevented.

Abstract: Three-dimensional germanium-based semiconductor devices formed on globally or locally isolated substrates are described. For example, a semiconductor device includes a semiconductor substrate. An insulating structure is disposed above the semiconductor substrate. A three-dimensional germanium-containing body is disposed on a semiconductor release layer disposed on the insulating structure. The three-dimensional germanium-containing body includes a channel region and source/drain regions on either side of the channel region. The semiconductor release layer is under the source/drain regions but not under the channel region. The semiconductor release layer is composed of a semiconductor material different from the three-dimensional germanium-containing body. A gate electrode stack surrounds the channel region with a portion disposed on the insulating structure and laterally adjacent to the semiconductor release layer.

Abstract: A thin film transistor array panel and a manufacturing method therefor. A shorting bar for connecting a thin film transistor with data lines is formed separate from the data lines, and then the data lines and the shorting bar are connected through a connecting member. As a result, all the data lines are floated during manufacture, so that variation in etching speed between data lines does not occur. Since variation in etching speed between the data lines can be prevented, performance deterioration of the transistor caused by a thickness difference in the lower layer of the data line can be prevented, as can resulting deterioration in display quality. Also, the influence of static electricity can be reduced or eliminated. Furthermore, since the data lines and the shorting bar are connected to each other, the generation of static electricity can be prevented or reduced, and quality testing is more readily performed.

Abstract: A thin film transistor array panel according to an exemplary embodiment of the invention includes: a substrate; a gate line positioned on the substrate and including a gate electrode; a gate insulating layer positioned on the gate line; an oxide semiconductor layer positioned on the substrate; a source electrode and a drain electrode positioned on the oxide semiconductor layer; a first insulating layer positioned on the source electrode and the drain electrode and including a first contact hole; a data line positioned on the first insulating layer and intersecting the gate line; and a pixel electrode over the first insulating layer. The source electrode and the drain electrode each comprise a metal oxide. The data line is electrically connected to the source electrode through the first contact hole.

Abstract: In a liquid crystal display device, a first substrate includes electrical wirings and a semiconductor integrated circuit which has TFTs and is connected electrically to the electrical wirings, and a second substrate includes a transparent conductive film on a surface thereof. A surface of the first substrate that the electrical wirings are formed is opposite to the transparent conductive film on the second substrate. Also, in a liquid crystal display device, a first substrate includes a matrix circuit and a peripheral driver circuit, and a second substrate is opposite to the first substrate. Spacers are provided between the first and second substrates. A seal material is formed outside the matrix circuits and the peripheral driver circuits in the first and second substrates. A protective film is formed on the peripheral driver circuit has substantially a thickness equivalent to an interval between the substrates which is formed by the spacers.

Abstract: A method of manufacturing a semiconductor device, comprises the steps of: forming a first insulating film on a first substrate; forming a second insulating film on the first insulating film; forming an amorphous silicon film on the second insulating film; holding a metal element that promotes the crystallization of silicon in contact with a surface of the amorphous silicon film; crystallizing the amorphous silicon film through a heat treatment to obtain a crystalline silicon film; forming a thin-film transistor using the crystalline silicon film; forming a sealing layer that seals the thin-film transistor; bonding a second substrate having a translucent property to the sealing layer; and removing the first insulating film to peel off the first substrate.

Abstract: A thin film transistor substrate and a method for fabricating the same are disclosed. A thin film transistor substrate includes a substrate comprising a plurality of grooves having different depths, respectively, to have a multi-step structure; gate and data lines alternatively crossed in the grooves to form a plurality of pixel areas; thin film transistors formed in the grooves of the substrate to be formed in cross portion of the gate and data lines, wherein active layers of the thin transistors are formed along the gate lines and gate electrodes, the active layers separated from active layers of neighboring pixel areas with the data line located there between.

Abstract: An inkjet ink capable of forming a polyimide film having, for example, strong mechanical strength, is provided. The inkjet ink contains: a polyamic acid (A) having a weight-average molecular weight of 50,000-500,000; one or more of an amic acid compound (B1) and an amic acid compound (B2), in which the amic acid compound (B1) is prepared from a compound (a3) having two or more anhydride groups and a monoamine (a5), and the amic acid compound (B2) is prepared from a diamine (a4) and a compound (a6) having one anhydride group; and a solvent (C).

Abstract: A transistor includes a substrate, a source terminal and a drain terminal, each terminal being supported by the substrate, and the source and drain terminal being separated by a portion of the substrate, a layer of semiconductive material deposited so as to cover the portion of the substrate and to connect the source terminal to the drain terminal, a layer of dielectric material deposited so as to cover at least a portion of the layer of semiconductive material, and a layer of electrically conductive material deposited so as to cover at least a portion of the layer of dielectric material. The layer of electrically conductive material providing a gate terminal to which a potential may be applied to control a conductivity of the layer of semiconductive material connecting the source and drain terminals.

Abstract: Disclosed is a method of forming a semiconductor-on-insulator (SOI) structure on bulk semiconductor starting wafer. Parallel semiconductor bodies are formed at the top surface of the wafer. An insulator layer is deposited and recessed. Exposed upper portions of the semiconductor bodies are used as seed material for growing epitaxial layers of semiconductor material laterally over the insulator layer, thereby creating a semiconductor layer. This semiconductor layer can be used to form one or more SOI devices (e.g., single-fin or multi-fin MUGFET, multiple series-connected single-fin, multi-fin MUGFETs). However, placement of SOI device components in and/or on portions of the semiconductor layer should be predetermined to avoid locations which might impact device performance (e.g., placement of any FET gate on a semiconductor fin formed from the semiconductor layer can be predetermined to avoid interfaces between joined epitaxial semiconductor material sections).

Abstract: The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.

Abstract: It is an object to provide an element structure of a semiconductor device for having a sufficient contact area between an electrode in contact with a source region or a drain region and the source region or the drain region, and a method for manufacturing the semiconductor device with the element structure. An upper electrode is formed over a high-concentration impurity region (the source region or the drain region). A contact hole passing through an interlayer insulating film is formed overlapping with a region where the upper electrode and the high-concentration impurity region are stacked.

Abstract: A semiconductor device 100 has such a structure that a semiconductor chip 110 is flip-chip mounted on a wiring board 120. The wiring board 120 has a multilayer structure in which a plurality of wiring layers and a plurality of insulating layers are arranged, and has a structure in which insulating layers of a first layer 122, a second layer 124, a third layer 126 and a fourth layer 128 are provided. The first layer 122 has a first insulating layer 121 and a second insulating layer 123. A protruded portion 132 which is protruded in a radial direction (a circumferential direction) from an outer periphery at one surface side of a first electrode pad 130 is formed on a whole periphery over a boundary surface between the first insulating layer 121 and the second insulating layer 123.

Abstract: A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.

Abstract: A method of manufacturing a solar cell by providing a first substrate; depositing on the first substrate a sequence of layers of semiconductor material forming a solar cell including a top subcell and a bottom subcell; forming a metal back contact over the bottom subcell; forming a group of discrete, spaced-apart first bonding elements over the surface of the back metal contact; attaching a surrogate substrate on top of the back metal contact using the bonding elements; and removing the first substrate to expose the surface of the top subcell.

Abstract: A semiconductor device comprises a thin film transistor provided over a substrate having an insulating surface, and an electrode penetrating the substrate. The thin film transistor is provided between a first structural body and a second structural body, which has a higher rigidity than the first structural body, which serve as protectors because the structural bodies have resistance to a pressing force such as a tip of a pen or bending stress applied from outside so malfunction due to the pressing force and the bending stress can be prevented.

Abstract: A semiconductor device having at least one transistor covered by an ultra-stressor layer, and method for fabricating such a device. In an NMOS device, the ultra-stressor layer includes a tensile stress film over the source and drain regions, and a compressive stress film over the poly region. In a PMOS device, the ultra-stressor layer includes a compressive stress film over the source and drain regions and a tensile stress film over the poly region. In a preferred embodiment, the semiconductor device includes a PMOS transistor and an NMOS transistor forming a CMOS device and covered with an ultra stressor layer.

Abstract: A semiconductor device having a highly responsive thin film transistor (TFT) with low subthreshold swing and suppressed decrease in the on-state current and a manufacturing method thereof are demonstrated. The TFT of the present invention is characterized by its semiconductor layer where the thickness of the source region or the drain region is larger than that of the channel formation region. Manufacture of the TFT is readily achieved by the formation of an amorphous semiconductor layer on a projection portion and a depression portion, which is followed by subjecting the melting process of the semiconductor layer, resulting in the formation of a crystalline semiconductor layer having different thicknesses. Selective addition of impurity to the thick portion of the semiconductor layer provides a semiconductor layer in which the channel formation region is thinner than the source or drain region.

Abstract: Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe.

Abstract: A stack pad layers including a first pad oxide layer, a pad nitride layer, and a second pad oxide layer are formed on a semiconductor-on-insulator (SOI) substrate. A deep trench extending below a top surface or a bottom surface of a buried insulator layer of the SOI substrate and enclosing at least one top semiconductor region is formed by lithographic methods and etching. A stress-generating insulator material is deposited in the deep trench and recessed below a top surface of the SOI substrate to form a stress-generating buried insulator plug in the deep trench. A silicon oxide material is deposited in the deep trench, planarized, and recessed. The stack of pad layer is removed to expose substantially coplanar top surfaces of the top semiconductor layer and of silicon oxide plugs. The stress-generating buried insulator plug encloses, and generates a stress to, the at least one top semiconductor region.

Abstract: Structures and a method for detecting ionizing radiation using silicon-on-insulator (SOI) technology are disclosed. In one embodiment, the invention includes a substrate having a buried insulator layer formed over the substrate and an active layer formed over the buried insulator layer. Active layer may be fully depleted. A transistor is formed over the active layer, and includes a first gate conductor, a first gate dielectric and source/drain diffusion regions. The first gate conductor may include a material having a substantially (or fully) depleted doping concentration such that it has a resistivity higher than doped polysilicon such as intrinsic polysilicon. A second gate conductor is formed below the buried insulator layer and provides a second gate dielectric corresponding to the second gate conductor. A channel region between the first gate conductor and the second gate conductor is controlled by the second gate conductor (back gate) such that it acts as a radiation detector.

Abstract: A thin film transistor, which has a first passivation layer and a second passivation layer to maintain high reliability while preventing hydrogen from being induced to a semiconductor layer, and a method for fabricating the thin film transistor are provided. The method includes providing a substrate including an insulation substrate, forming a gate electrode on the substrate, forming a gate insulation layer on the substrate and the gate electrode, forming a semiconductor layer on the gate insulation layer, forming source/drain electrodes on the semiconductor layer to expose a portion of a top portion of the semiconductor layer, forming a first passivation layer to cover exposed top portions of the gate insulation layer, the semiconductor layer and the source/drain electrodes, and forming a second passivation layer on the first passivation layer, wherein the forming of the second passivation layer comprises performing deposition at a higher temperature than the forming of the first passivation layer.