Abstract: A method is provided for fabricating transistors of first and second types in a single substrate. First and second active zones of the substrate are delimited by lateral isolation trench regions, and a portion of the second active zone is removed so that the second active zone is below the first active zone. First and second layers of semiconductor material are formed on the second active zone, so that the second layer is substantially in the same plane as the first active zone. Insulated gates are produced on the first active zone and the second layer. At least one isolation trench region is selectively removed, and the first layer is selectively removed so as to form a tunnel under the second layer. The tunnel is filled with a dielectric material to insulate the second layer from the second active zone of the substrate. Also provided is such an integrated circuit.

Abstract: An image display device capable of high-resolution and smooth moving image display, equipped with TFTs in an n-type (or p-type) semiconductor layer with a high on-off ratio and a low resistance. In polysilicon crystallization by laser annealing, an n-type (or p-type) semiconductor layer with a low resistance is produced by performing the following processes in order: implanting nitrogen (N) ions into an amorphous silicon precursor semiconductor film; laser crystallization; implanting n-type (or p-type) dopant ions; and annealing for dopant activation. When fabricating TFTs, this low-resistance semiconductor layer is used to form a source and a drain. Since C, N, and O impurities decrease the mobility of the TFTs, polysilicon is used in which the contaminants concentrations meet the following conditions: carbon concentration ?3×1019 cm?3, nitrogen concentration ?5×1017 cm?3, and oxygen concentration ?3×1019 cm?3.

Abstract: When a semi-conductor film is irradiated with conventional pulsed laser light, unevenness, which is called as ridge, is caused on the surface of the semiconductor film. In the case of a top-gate type TFT, element characteristics are changed depending on the ridge. In particular, there is a problem in that variation in the plural thin film transistors electrically connected in parallel with one another. According to the present invention, in manufacturing a circuit including plural thin film transistors, the width LP of a region (not including a microcrystal region) that is melted by irradiating a semiconductor film with light of a continuous wave laser is enlarged, and active layers of a plurality of thin film transistors (that are electrically connected in parallel with one another) are arranged in one region.

Abstract: Embodiments of the invention provide an asymmetrical transistor device comprising a semiconductor substrate, a source region, a drain region and a channel region. The channel region is provided between the source and drain regions, the source, drain and channel regions being provided in the substrate. The device has a layer of a buried insulating medium provided below the source region and not below the drain region thereby forming an asymmetrical structure. The layer of buried insulating medium is provided in abutment with a lower surface of the source region.

Abstract: The present disclosure provides a thin film transistor which includes a source electrode, a drain electrode, a semiconducting layer, an insulating layer and a gate electrode. The drain electrode is spaced apart from the source electrode. The semiconducting layer is electrically connected with the source electrode and the drain electrode. The gate electrode is insulated from the source electrode, the drain electrode, and the semiconducting layer by the insulating layer. At least one of the gate electrode, the drain electrode, the source electrode includes a carbon nanotube composite layer.

Abstract: In a manufacturing method of a SOI type high withstand voltage semiconductor device formed on a support substrate via an insulation film, a small-sized semiconductor device having small dispersion of withstand voltage is manufactured by introducing impurities into the whole surface of a p-type or n-type SOI substrate having an impurity concentration of 2E14 cm?3 or less and serving as an active layer of the semiconductor device with an ion implantation method and thereby forming a drift layer.

Abstract: Methods and apparatus for producing a thin film transistor (TFT) result in: a glass or glass ceramic substrate; a single crystal semiconductor layer; a source structure disposed on the single crystal semiconductor layer; a drain structure disposed on the single crystal semiconductor layer; and a gate structure located with respect to the drain structure defining a lightly doped drain region therein, wherein a lateral length of the lightly doped drain region is such that the TFT exhibits a relatively low carrier mobility and moderate sub-threshold slope suitable for OLED display applications.

Abstract: A semiconductor device in which a semiconductor layer is formed on an insulating substrate with a front-end insulating layer interposed between the semiconductor layer and the insulating substrate is provided which is capable of preventing action of an impurity contained in the insulating substrate on the semiconductor layer and of improving reliability of the semiconductor device. In a TFT (Thin Film Transistor), boron is made to be contained in a region located about 100 nm or less apart from a surface of the insulating substrate so that boron concentration decreases at an average rate being about 1/1000-fold per 1 nm from the surface of the insulating substrate toward the semiconductor layer.

Abstract: A method of fabricating semiconductor components in-situ and in a continuous integrated sequence includes the steps of providing a single crystal semiconductor substrate, epitaxially growing a first layer of rare earth insulator material on the semiconductor substrate, epitaxially growing a first layer of semiconductor material on the first layer of rare earth insulator material, epitaxially growing a second layer of rare earth insulator material on the first layer of semiconductor material, and epitaxially growing a second layer of semiconductor material on the second layer of rare earth insulator material. The first layer of rare earth insulator material, the first layer of semiconductor material, the second layer of rare earth insulator material, and the second layer of semiconductor material form an in-situ grown structure of overlying layers. The in-situ grown structure is etched to define a semiconductor component and electrical contacts are deposited on the semiconductor component.

Abstract: A light emitting display device includes a light emitting diode and a thin film transistor on a substrate, the light emitting diode and thin film transistor being electrically coupled to each other, and a photo diode on the substrate, the photo diode including an intrinsic region and a P-type doping region coupled to each other.

Abstract: Device and design structures for memory cells in a non-volatile random access memory (NVRAM). The device structure includes a semiconductor body in direct contact with the insulating layer, a control gate electrode, and a floating gate electrode in direct contact with the insulating layer. The semiconductor body includes a source, a drain, and a channel between the source and the drain. The floating gate electrode is juxtaposed with the channel of the semiconductor body and is disposed between the control gate electrode and the insulating layer. A first dielectric layer is disposed between the channel of the semiconductor body and the floating gate electrode. A second dielectric layer is disposed between the control gate electrode and the floating gate electrode.

Abstract: Provided is an organic thin film transistor, method of forming the same, and a memory device employing the same. The organic thin film transistor includes a substrate, a source electrode and a drain electrode on the substrate, an active layer on the substrate between the source electrode and the drain electrode, a gate electrode controlling the active layer, and an organic dielectric layer between the active layer and the gate electrode. The organic dielectric layer includes nanoparticles, a hydrophilic polymer surrounding the nanoparticles, and a hydrophobic polymer.

Abstract: The disclosure concerns a method of manufacturing a semiconductor device including forming a plurality of fins made of a semiconductor material on an insulating layer; forming a gate insulating film on side surfaces of the plurality of fins; and forming a gate electrode on the gate insulating film in such a manner that a compressive stress is applied to a side surface of a first fin which is used in an NMOSFET among the plurality of fins in a direction perpendicular to the side surface and a tensile stress is applied to a side surface of a second fin which is used in a PMOSFET among the plurality of fins in a direction perpendicular to the side surface.

Abstract: A method of forming a transistor structure on a substrate (SOI) is disclosed, wherein the substrate comprises a supporting Si layer, a buried insulating layer, and a top Si layer. The method comprises forming a gate region of the transistor structure on the top Si layer, wherein the gate region is separated from the top Si layer by a dielectric layer, and wherein the top Si layer comprises a high dopant level. The method further comprises forming an open area on the top Si layer demarcated by a demarcating oxide and/or resist layer region, forming high level impurity or heavily-damaged regions by ion implantation, and exposing the open area to an ion beam, wherein the ion beam comprises a combination of beam energy and dose, and wherein the demarcating layer region and the gate region act as an implantation mask.

Abstract: A structure, memory devices using the structure, and methods of fabricating the structure. The structure includes: an array of nano-fins, each nano-fin comprising an elongated block of semiconductor material extending axially along a first direction, the nano-fins arranged in groups of at least two nano-fins each, wherein ends of nano-fins of each adjacent group of nano-fins are staggered with respect to each other on both a first and a second side of the array; wherein nano-fins of each group of nano-fins are electrically connected to a common contact that is specific to each group of nano-fins such that the common contacts comprise a first common contact on the first side of the array and a second common contact on the second side of the array; and wherein each group of nano-fins has at least two gates that electrically control the conductance of nano-fins of the each group of nano-fins.

Abstract: A technique for forming a TFT element over a substrate having flexibility typified by a flexible plastic film is tested. When a structure in which a light-resistant layer or a reflective layer is employed to prevent the damage to the delamination layer, it is difficult to fabricate a transmissive liquid crystal display device or a light emitting device which emits light downward. A substrate and a delamination film are separated by a physical means, or a mechanical means in a state where a metal film formed over a substrate, and a delamination layer comprising an oxide film including the metal and a film comprising silicon, which is formed over the metal film, are provided. Specifically, a TFT obtained by forming an oxide layer including the metal over a metal film; crystallizing the oxide layer by heat treatment; and performing delamination in a layer of the oxide layer or at both of the interface of the oxide layer is formed.

Abstract: The shape of a tip of an insulating material of an insulating isolation region is provided as being a concave one recessed below the back surface of an n-semiconductor substrate. This reduces the electric field strength at the corner at which the bottom of the n-semiconductor substrate is in contact with the insulating isolation region to allow an excellent breakdown voltage to be obtained. Moreover, by forming a high impurity concentration region such as a field-stop layer on the back surface of the n-semiconductor substrate, a depletion layer extending from the top surface is prevented from reaching the back surface. This eliminates an influence of a surface state introduced in the interface between the insulator film formed on the back surface and the n-semiconductor substrate, by which an excellent breakdown voltage can be obtained.

Abstract: A semiconductor device of which manufacturing steps can be simplified by doping impurities at a time, and a manufacturing method thereof.

Abstract: An uneven portion is formed on a substrate extending in a linear shape stripe pattern, convex portions of an insulating film that intersects with a crystalline semiconductor film divided into island shapes are removed, and an amorphous semiconductor film is formed on the insulating film. The semiconductor film is melted and flows into concave portions of the insulating film, where it crystallizes, and the semiconductor film that remains on the convex portions of the insulating film is removed. A semiconductor film divided into island shapes is then formed from the semiconductor film formed in the concave portions, the convex portions of the insulating film are removed in portions where channel forming regions are to be formed, thus exposing side surface portions of the semiconductor film. A gate insulating film and a gate electrode contacting the side surface portions and upper surface portions of the semiconductor film are then formed.

Abstract: In an insulating film pattern, a first pattern part is formed at one surface of the insulating film pattern to form a source electrode, a drain electrode, and a semiconductor layer of the thin film transistor. The first pattern part is recessed in one surface of the insulating film pattern. The insulating film pattern is formed on a substrate through an imprint scheme, and is deposited on a base substrate having a gate electrode and a gate line through a contact print scheme. A source electrode, drain electrode, and semiconductor layer of a thin film transistor are formed through an inkjet print scheme using a first pattern part of the insulating film pattern.

Abstract: A microstructure which forms a micromachine is formed by using a silicon wafer as a mainstream, conventionally. In view of this, the invention provides a manufacturing method of a micromachine in which a microstructure is formed over an insulating substrate. The invention provides a micromachine including a layer containing polycrystalline silicon which is crystallized by thermal crystallization or laser crystallization using a metal element and including a space over or under the layer. Such polycrystalline silicon can be formed over an insulating surface and has high strength, therefore, it can be used as a microstructure as well. As a result, a microstructure formed over an insulating substrate or a micromachine provided with a microstructure can be provided.

Abstract: A base substrate for chip scale package includes a carrier member made of electrical conductive metals with a first through opening; an active member laminated by a base layer made of electrical conductive metal and an intermediate layer made of electrical insulating or dielectric material, the active member having a through opening with a diameter larger that the diameter of the through opening of the base metal member; the active member being coupled with the carrier member in such a way that the intermediate layer is adhered to an upper surface of the carrier member, and these through openings are aligned to define a shoulder around the through opening of the base metal plate.

Abstract: A semiconductor device includes a Si substrate, an insulating film formed on onepart of the Si substrate, a bulk Si region grown on other part of the Si substrate other than the insulating film, Si1-xGex (0<x?1) thin film formed on the insulating film in direct contact with the insulating film, and substantially flush with top of the bulk Si region, a first field effect transistor fabricated in the bulk Si region, and a second field effect transistor fabricated in the Si1-xGex thin film.

Abstract: A self-aligned Silicon on Insulator (SOI) Schottky Body Tie structure includes: a source region comprising a silicide layer disposed on a top surface of the source region; a drain region comprising a silicide layer disposed on a top surface of the drain region; a gate region disposed above a channel formed by the drain and source regions; and a gate oxide layer disposed between the gate region and the channel formed by the drain and source regions, wherein when silicidation is performed on the diffusion region it forms a metal-silicon alloy contact such that the silicide layer extends into and directly touches the channel.

Abstract: An insulating film having depressions and projections are formed on a substrate. A semiconductor film is formed on the insulating film. Thus, for crystallization by using laser light, a part where stress concentrates is selectively formed in the semiconductor film. More specifically, stripe or rectangular depressions and projections are provided in the semiconductor film. Then, continuous-wave laser light is irradiated along the stripe depressions and projections formed in the semiconductor film or in a direction of a major axis or minor axis of the rectangle.

Abstract: A method for peeling off a thin film semiconductor element over an insulating surface by using a void, and a method for manufacturing a semiconductor device by transferring the peeled semiconductor element. According to the peeling method of the invention, a first base layer having a plurality of recessed portions is formed over a substrate, and a second base layer having a plurality of voids is formed on the recessed portions of the first base layer. On the second base layer, a third base layer is formed and a semiconductor element is formed thereon. Then, by separating the second base layer at an intersecting surface with the voids, the semiconductor element is peeled off from the substrate.

Abstract: A semiconductor device having a semiconductor element (a thin film transistor, a thin film diode, a photoelectric conversion element of silicon PIN junction, or a silicon resistor element) which is light-weight, flexible (bendable), and thin as a whole is provided as well as a method of manufacturing the semiconductor device. In the present invention, the element is not formed on a plastic film. Instead, a flat board such as a substrate is used as a form, the space between the substrate (third substrate (17)) and a layer including the element (peeled layer (13)) is filled with coagulant (typically an adhesive) that serves as a second bonding member (16), and the substrate used as a form (third substrate (17)) is peeled off after the adhesive is coagulated to hold the layer including the element (peeled layer (13)) by the coagulated adhesive (second bonding member (16)) alone. In this way, the present invention achieves thinning of the film and reduction in weight.

Abstract: A method of forming a thin-film layered electronic device over a flexible substrate comprises the steps of depositing a buffer layer over the flexible substrate, heating the substrate and buffer layer stack to a temperature at which plastic deformation of the buffer layer takes place, cooling the stack, then forming the thin-film electronic device over the plastically deformed buffer layer without further plastic deformation of the buffer layer. The heating and cooling to cause plastic deformation of the buffer layer is referred to as annealing. The thin-film electronic device is formed by a process according to which all steps are performed at a temperature below that at which further plastic deformation of the buffer layer occurs. In-process strain and runout are reduced, improving device yield on flexible substrates. An optional metal base layer may be formed over the buffer layer prior annealing.

Abstract: An SOI device includes an SOI substrate composed of a stack structure of a silicon substrate, a buried oxide layer, and a silicon layer. Grooves are defined in the silicon layer each exposing the buried oxide layer. A barrier layer is formed on the lower portion of the sidewall of each of the grooves. An epi-silicon layer is formed to fill the grooves and cover the barrier layer. Gates are formed on the epi-silicon layer, and junction areas are formed in the silicon layer on both sides of the gates.

Abstract: In fabricating a thin film transistor, an active layer comprising a silicon semiconductor is formed on a substrate having an insulating surface. Hydrogen is introduced into The active layer. A thin film comprising SiOxNy is formed to cover the active layer and then a gate insulating film comprising a silicon oxide film formed on the thin film comprising SiOxNy. Also, a thin film comprising SiOxNy is formed under the active layer. The active layer includes a metal element at a concentration of 1×1015 to 1×1019 cm?3 and hydrogen at a concentration of 2×1019 to 5×1021 cm?3.

Abstract: In one embodiment, the invention is a complementary metal-oxide-semiconductor device with an embedded stressor. One embodiment of a field effect transistor includes a silicon on insulator channel, a gate electrode coupled to the silicon on insulator channel, and a stressor embedded in the silicon on insulator channel and spaced laterally from the gate electrode, where the stressor is formed of a silicon germanide alloy whose germanium content gradually increases in one direction.

Abstract: Some embodiments include formation of at least one cavity in a first semiconductor material, followed by epitaxially growing a second semiconductor material over the first semiconductor material and bridging across the at least one cavity. The cavity may be left open, or material may be provided within the cavity. The material provided within the cavity may be suitable for forming, for example, one or more of electromagnetic radiation interaction components, transistor gates, insulative structures, and coolant structures. Some embodiments include one or more of transistor devices, electromagnetic radiation interaction components, transistor devices, coolant structures, insulative structures and gas reservoirs.

Abstract: A method and resulting structure for fabricating a FET transistor for an integrated circuit on a silicon oxide (SOI) substrate comprising the steps of forming recesses in a substrate on both sides of a gate on the substrate, implanting oxygen ions into the recesses, and annealing the substrate to convert the oxygen ions into a SOI layer below each recess.

Abstract: An integrated circuit including pairs of strained complementary CMOS field-effect devices consisting of n-FET and p-FET transistors on a substrate. The n-FET is provided with a compressive dielectric stressor, while the p-FET is provided with a tensile stressed dielectric. Each dielectric stressor includes a discrete horizontal segment on a surface overlying and contacting the gate of the respective FET. The stress enhancement is insensitive to PC pitch, and by reducing the height of the polysilicon stack, the scalability which is achieved contributes to a performance improvement. The n-FET leverages higher stress values that are obtainable in the compressive liners are greater than 3 GPa compared to less than 1.5 GPa for tensile liners.

Abstract: A semiconductor device, comprises: a transistor having structured to include a gate electrode formed on a semiconductor layer on a semiconductor substrate via a gate insulating film, and a source layer and a drain layer formed on the semiconductor layer sandwiching the gate electrode; a hollow portion existing between the source layer and the semiconductor substrate, and between the drain layer and the semiconductor substrate, respectively; and the hollow portion in absence between the semiconductor layer under the gate electrode and the semiconductor substrate.

Abstract: A method is provided to fabricate a semiconductor device, where the method includes providing a substrate comprised of crystalline silicon; implanting a ground plane in the crystalline silicon so as to be adjacent to a surface of the substrate, the ground plane being implanted to exhibit a desired super-steep retrograde well (SSRW) implant doping profile; annealing implant damage using a substantially diffusionless thermal annealing to maintain the desired super-steep retrograde well implant doping profile in the crystalline silicon and, prior to performing a shallow trench isolation process, depositing a silicon cap layer over the surface of the substrate. The substrate may be a bulk Si substrate or a Si-on-insulator substrate. The method accommodates the use of an oxynitride gate stack structure or a high dielectric constant oxide/metal (high-K/metal) gate stack structure.

Abstract: A semiconductor device which has a substrate formed as a rigid body, includes stress relaxation layers formed by filling in concave portions defined in a first main surface of the substrate, and a device forming layer which covers part of the first main surface and is formed in the substrate. The substrate is made up of a material larger than the stress relaxation layers and the device forming layer in thermal expansion coefficient. Side faces of the device forming layer are electrically connected to their corresponding upper surfaces of the stress relaxation layers in an electrically non-conducting state via insulative stress transfer layers formed on the upper surfaces.

Abstract: OFF current of a TFT is reduced. There is provided a semiconductor device comprising: a substrate; a shielding film formed so as to be in contact with the substrate; a planarization insulating film formed on the substrate so as to cover the shielding film; and a semiconductor layer formed so as to be in contact with the planarization insulating film. The semiconductor device is characterized in that the shielding film overlaps the semiconductor layer with the planarization insulating film sandwiched therebetween, and that the planarization insulating film is polished by CMP before the semiconductor layer is formed.

Abstract: A method of fabricating semiconductor components in-situ and in a continuous integrated sequence includes the steps of providing a single crystal semiconductor substrate, epitaxially growing a first layer of rare earth insulator material on the semiconductor substrate, epitaxially growing a first layer of semiconductor material on the first layer of rare earth insulator material, epitaxially growing a second layer of rare earth insulator material on the first layer of semiconductor material, and epitaxially growing a second layer of semiconductor material on the second layer of rare earth insulator material. The first layer of rare earth insulator material, the first layer of semiconductor material, the second layer of rare earth insulator material, and the second layer of semiconductor material form an in-situ grown structure of overlying layers. The in-situ grown structure is etched to define a semiconductor component and electrical contacts are deposited on the semiconductor component.

Abstract: A semiconductor device according to an embodiment includes: a semiconductor substrate; a gate electrode formed on the semiconductor substrate via a gate insulating film; a channel region formed in a region of the semiconductor substrate below the gate electrode; an epitaxial crystal layer containing a conductive impurity, which is formed sandwiching the channel region and has a function as a source region and a drain region, and formed on a recess in the semiconductor substrate; and a growth suppressing portion formed on the recess in the semiconductor substrate, and configured to suppress an epitaxial growth of a crystal in the epitaxial layer from the semiconductor substrate.

Abstract: A method is provided for fabricating transistors of first and second types in a single substrate. First and second active zones of the substrate are delimited by lateral isolation trench regions, and a portion of the second active zone is removed so that the second active zone is below the first active zone. First and second layers of semiconductor material are formed on the second active zone, so that the second layer is substantially in the same plane as the first active zone. Insulated gates are produced on the first active zone and the second layer. At least one isolation trench region is selectively removed, and the first layer is selectively removed so as to form a tunnel under the second layer. The tunnel is filled with a dielectric material to insulate the second layer from the second active zone of the substrate. Also provided is such an integrated circuit.

Abstract: An intermediate semiconductor structure is disclosed. The semiconductor structure includes a substrate; a relaxed Si1-xGex layer on the substrate, the relaxed Si1-xGex layer having at least one trench; an un-etched Si layer portion on the substrate and beneath the relaxed Si1-xGex layer along a periphery of the substrate providing structural support for the relaxed Si1-xGex layer along the periphery of the substrate; and at least one void between the relaxed Si1-xGex layer and the substrate, wherein the void encompasses an entire surface area of the substrate but for a portion of the substrate in contact with the un-etched Si layer portion.

Abstract: An object is to provide a structure for forming a circuit for which high-speed operation and low-voltage operation are required and a circuit for which sufficient reliability is required at the time of high voltage application in a circuit group provided over one substrate in a semiconductor device, and a manufacturing method thereof. A semiconductor device is provided with a plurality of kinds of transistors which include single-crystal semiconductor layers with different thicknesses, which are separated from a single-crystal semiconductor substrate and bonded, over one substrate. The single-crystal semiconductor layer of a transistor for which high-speed operation is required is formed thinner than that of a transistor for which high resistance to a voltage is required, so that the thickness of the single-crystal semiconductor layer is made to be thin.

Abstract: Disclosed is a method of manufacturing a thin film transistor, in which a semiconductor layer and a gate insulating film may be formed through ink jet printing using a single bank, thereby simplifying the manufacturing process and decreasing the manufacturing cost, leading to more economical thin film transistors. The thin film transistor manufactured using the method of example embodiments may be used as a switching element for sensors, memory devices, optical devices, and active matrix flat panel displays.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract: An array substrate for a display device includes an insulating substrate, a buffer layer which is disposed on the insulating substrate and is formed of silicon oxide with a refractive index equal to a refractive index of the insulating substrate, a first insulation layer which is disposed on the buffer layer and formed of silicon nitride, a second insulation layer which is disposed on the first insulation layer and formed of silicon oxide, a switching element including a semiconductor layer disposed on the second insulation layer, and a pixel electrode connected to the switching element.

Abstract: An integrated thin-film capacitor includes a dielectric disposed between a first electrode and a second electrode. The thin-film capacitor includes a dielectric disposed upon the first electrode, and the dielectric exhibits a substantially uniform heat-altered morphology along a line defined by a characteristic dimension thereof. A computing system is also disclosed that includes the thin-film capacitor.

Abstract: The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication.

Abstract: According to various exemplary embodiments of this invention, a method of producing a semiconductor structure is provided that includes providing a layered structure on a first substrate, the layered structure including a silicon layer that is provided over a first dielectric layer, a first dielectric layer that is provided over an etch-stop layer, the etch-stop layer provided over a buffer layer, the buffer layer provided over a sacrificial layer, and a sacrificial layer provided over a first substrate. Moreover, various exemplary embodiments of the methods of this invention provide for a second substrate over the layered structure, separating the first substrate and the sacrificial layer from the buffer layer, separating the buffer layer and the etch-stop layer from the first dielectric layer and providing a drain electrode and a source electrode over the layered structure.

Abstract: A non-planar microelectronic device, a method of fabricating the device, and a system including the device. The non-planar microelectronic device comprises: a substrate body including a substrate base and a fin, the fin defining a device portion at a top region thereof; a gate dielectric layer extending at a predetermined height on two laterally opposing sidewalls of the fin, the predetermined height corresponding to a height of the device portion; a device isolation layer on the substrate body and having a thickness up to a lower limit of the device portion; a gate electrode on the device isolation layer and further extending on the gate dielectric layer; an isolation element extending on the two laterally opposing sidewalls of the fin up to a lower limit of the gate dielectric layer, the isolation element being adapted to reduce any fringe capacitance between the gate electrode and regions of the fin extending below the device portion.