Comprising Group Iii-v Or Ii-vi Compound, Or Of Se, Te, Or Oxide Semiconductor (epo) Patents (Class 257/E29.296)
  • Publication number: 20080277656
    Abstract: Provided are a method of manufacturing a ZnO semiconductor layer for an electronic device, which can control the size of crystals of the ZnO semiconductor layer and the number of carriers using a surface chemical reaction between precursors, and a thin film transistor (TFT) including the ZnO semiconductor layer.
    Type: Application
    Filed: January 8, 2008
    Publication date: November 13, 2008
    Inventors: Sang Hee PARK, Chi Sun HWANG, Hye Yong CHU, Jeong Ik LEE
  • Publication number: 20080258143
    Abstract: A method of manufacturing a thin film transistor (“TFT”) substrate includes forming a first conductive pattern group including a gate electrode on a substrate, forming a gate insulating layer on the first conductive pattern group, forming a semiconductor layer and an ohmic contact layer on the gate insulating layer by patterning an amorphous silicon layer and an oxide semiconductor layer, forming a second conductive pattern group including a source electrode and a drain electrode on the ohmic contact layer by patterning a data metal layer, forming a protection layer including a contact hole on the second conductive pattern group, and forming a pixel electrode on the contact hole of the protection layer. The TFT substrate including the ohmic contact layer formed of an oxide semiconductor is further provided.
    Type: Application
    Filed: April 10, 2008
    Publication date: October 23, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sung-Ryul KIM, Sung-Hoon YANG, Byoung-June KIM, Czang-Ho LEE, Jae-Ho CHOI, Hwa-Yeul OH, Yong-Mo CHOI
  • Publication number: 20080213956
    Abstract: The present invention relates to a semiconductor structure such as a field effect transistors (FETs) in which the channel region of each of the FETs is composed of an array of more than one electrically isolated channel. In accordance with the present invention, the distance between each of the channels present in the channel region is within a distance of no more than twice their width from each other. The FETs of the present invention are fabricated using methods in which self-assembled block copolymers are employed in forming the channel.
    Type: Application
    Filed: October 16, 2007
    Publication date: September 4, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Charles T. Black, Ricardo Ruiz
  • Publication number: 20080003752
    Abstract: A method for fabricating a transistor having a Group III-V semiconductor substrate with an oxygen-free dielectric disposed between the substrate and a gate is described.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Matthew V. Metz, Mark L. Doczy, Suman Datta
  • Patent number: 7259409
    Abstract: A thin film device includes a metal sulfide layer formed on a single crystal silicon substrate by epitaxial growth; and a compound thin film with ionic bonding, which is formed on the metal sulfide layer by epitaxial growth. Alternatively, a thin film device includes a metal sulfide layer formed on a single crystal silicon substrate by epitaxial growth; and at least two compound thin films with ionic bonding, which are formed on the metal sulfide layer by epitaxial growth. For example, (11 20) surface AlN/MnS/Si (100) thin films formed by successively stacking a MnS layer (about 50 nm thick) and an AlN layer (about 1000 nm thick) on a single crystal Si (100) substrate, are used as a substrate, and a (11 20) surface GaN layer (about 100 nm thick) operating as a light emitting layer is formed on the substrate, thereby fabricating a thin film device.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: August 21, 2007
    Assignee: Tokyo Institute of Technology
    Inventors: Hideomi Koinuma, Jeong-Hwan Song, Toyohiro Chikyo, Young Zo Yoo, Parhat Ahmet, Yoshinori Konishi, Yoshiyuki Yonezawa