Abstract: Provided are a capacitor of a semiconductor device using a TiO2 dielectric layer and a method of fabricating the capacitor. The capacitor includes a Ru bottom electrode formed on a semiconductor substrate, an rutile-structures RuO2 pretreated layer which is formed by oxidizing the Ru bottom electrode, a TiO2 dielectric layer which has a rutile crystal structure corresponding to the rutile crystal structure of the RuO2 pretreated layer and is doped with an impurity, and a top electrode formed on the TiO2 dielectric layer. The method includes forming a Ru bottom electrode on a semiconductor substrate, forming a rutile-structured RuO2 pretreated layer by oxidizing a surface of the Ru bottom electrode, forming a TiO2 dielectric layer to have a rutile crystal structure corresponding to the rutile crystal structure of the RuO2 pretreated layer on the a RuO2 pretreated layer and doping the TiO2 dielectric layer with an impurity, and forming a top electrode on the TiO2 dielectric layer.

Abstract: As for electrode pads for a semiconductor integrated circuit element, some of electrode pads for signal transmission are coupled to Ti films. Others of the electrode pads for signal transmission are coupled to electrode pads through wiring routed in multilayer wiring. Electrode pads for power supply are coupled to electrode pads to which power lines at potentials different from each other are coupled through wiring. The electrode pads are also coupled to Al foils (anodes). Electrode pads for grounding are coupled to electrode pads to which ground lines are coupled through wiring. The electrode pads are also coupled to conductive polymer films (cathodes).

Abstract: A process of making a stud capacitor structure is disclosed. The process includes embedding the stud in a dielectric stack. In one embodiment, the process includes forming an electrically conductive seed film in a contact corridor of the dielectric stack. A storage cell stud is also disclosed. The storage cell stud can be employed in a dynamic random-access memory device. An electrical system is also disclosed that includes the storage cell stud.

Abstract: The present disclosure provides on-chip decoupling capacitor structures having trench capacitors integrated with a passive capacitor formed in the back-end-of-line wiring to provide an improved overall capacitance density. In some embodiments, the structure includes at least one deep trench capacitor and a passive capacitor formed in at least two back-end-of-line wiring levels. The trench and passive capacitors are in electrical communication through one of the wiring levels. In other embodiments, the structure includes at least one deep trench capacitor, a first back-end-of-line wiring level, and a second back-end-of-line wiring level. The deep trench capacitor with a dielectric that has an upper edge that terminates at a lower surface of a shallow trench isolation region. The first wiring level is in electrical communication with the trench capacitor. The second wiring level is vertically electrically connected to the first wiring level by vertical connectors so as to form a passive capacitor.

Abstract: An FeRAM is produced by a method including the steps of forming a lower electrode layer (24), forming a first ferroelectric film (25a) on the lower electrode layer (24), forming on the first ferroelectric film (25a) a second ferroelectric film (25b) in an amorphous state containing iridium inside, thermally treating the second ferroelectric film (25b) in an oxidizing atmosphere to crystallize the second ferroelectric film (25b) and to cause iridium in the second ferroelectric film (25b) to diffuse into the first ferroelectric film (25a), forming an upper electrode layer (26) on the second ferroelectric film (25b), and processing each of the upper electrode layer (26), the second ferroelectric film (25b), the first ferroelectric film (25a), and the lower electrode layer (24) to form the capacitor structure.

Abstract: A photoelectric conversion device comprising a semiconductor substrate of a first conduction type, and a photoelectric conversion element having an impurity region of the first conduction type and a plurality of impurity regions of a second conduction type opposite to the first conduction type. The plurality of second-conduction-type impurity regions include at least a first impurity region, a second impurity region provided between the first impurity region and a surface of the substrate, and a third impurity region provided between the second impurity region and the surface of the substrate. A concentration C1 corresponding to a peak of the impurity concentration in the first impurity region, a concentration C2 corresponding to a peak of the impurity concentration in the second impurity region and a concentration C3 corresponding to a peak of the impurity concentration in the third impurity region satisfy the following relationship: C2<C3<C1.

Abstract: The present invention discloses a structure of a buried word line, which comprises a semiconductor substrate having a U-shape trench, a U-shape gate dielectric layer in the U-shape trench, a polysilicon layer on the U-shape gate dielectric layer, a conducting layer on the polysilicon layer, and a cover dielectric layer on the conducting layer. The semiconductor structure may have a minimized size and when recess channels are formed thereby, the integration is accordingly improved without suffering from the short channel effect.

Abstract: There is provided a semiconductor device including, a semiconductor substrate having a circuit forming region and a peripheral region, a base insulating film formed over the semiconductor substrate, a capacitor formed of a lower electrode, a capacitor dielectric film made of a ferroelectric material, and an upper electrode in this order over the base insulating film in the circuit forming region, an uppermost interlayer insulating film formed over the capacitor, a seal ring formed over the semiconductor substrate in the peripheral region, the seal ring having a height that reaches at least the upper surface of the interlayer insulating film, and surrounding the circuit forming region, a block film formed over the seal ring and over the interlayer insulating film in the circumference of the seal ring, and an electrode conductor pattern which is formed over the interlayer insulating film in the peripheral region, the electrode conductor pattern having an electrode pad, and having a cross-section exposed to a di

Abstract: A ferroelectric memory that stores information by using a hysteresis characteristic of a ferroelectric, has a semiconductor substrate; a lower electrode formed above said semiconductor substrate; a ferroelectric film formed on said lower electrode; and an upper electrode formed on said ferroelectric film, wherein said upper electrode includes an AOx-type conductive oxide film formed on said ferroelectric film and an “A” metal film formed on said AOx-type conductive oxide film, and said “A” metal is a noble metal selected from among Ir, Ru, Rh, Pt, Os and Pd.

Abstract: A capacitor device includes a dielectric layer configured to have a composition represented as (Ba1-x, Srx)Ti1-zScyO3+? (0<x<1, 0.01<z<0.3, 0.005<y<0.02, ?0.5<?<0.5) and an in-plane deformation ? of crystal that satisfies ?0.4<<0.4, an upper electrode and a lower electrode that are placed on respective sides of the dielectric layer, and a substrate on which the upper electrode, the lower electrode, and the dielectric layer are disposed.

Abstract: This disclosure concerns a semiconductor device comprising an insulating film provided on a semiconductor substrate; a lower contact formed in the insulating film; a ferroelectric capacitor including a first lower electrode provided on the lower contact and connected to the lower contact, a second lower electrode provided on the first lower electrode and made of SRO (Strontium Ruthenium Oxide), a ferroelectric film including crystals, and an upper electrode provided on the ferroelectric film, grain diameters of the crystals being set to 30 nm to 150 nm by forming the ferroelectric film on the second lower electrode; and a wiring connected to the upper electrode.

Abstract: A method of enhanced atomic layer deposition is described. In an embodiment, the enhancement is the use of plasma. Plasma begins prior to flowing a second precursor into the chamber. The second precursor reacts with a prior precursor to deposit a layer on the substrate. In an embodiment, the layer includes at least one element from each of the first and second precursors. In an embodiment, the layer is TaN. In an embodiment, the precursors are TaF5 and NH3. In an embodiment, the plasma begins during the purge gas flow between the pulse of first precursor and the pulse of second precursor. In an embodiment, the enhancement is thermal energy. In an embodiment, the thermal energy is greater than generally accepted for ALD (>300 degrees Celsius). The enhancement assists the reaction of the precursors to deposit a layer on a substrate.

Abstract: A high-k dielectric film, a method of forming the high-k dielectric film, and a method of forming a related semiconductor device are provided. The high-k dielectric film includes a bottom layer of metal-silicon-oxynitride having a first nitrogen content and a first silicon content and a top layer of metal-silicon-oxynitride having a second nitrogen content and a second silicon content. The second nitrogen content is higher than the first nitrogen content and the second silicon content is higher than the first silicon content.

Abstract: Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer.

Abstract: A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.

Abstract: A semiconductor device has a ferro-electric capacitor with small leak current and less process deterioration even upon miniaturization.

Abstract: A capacitor includes a lower electrode, a first dielectric layer formed over the lower electrode, a second dielectric layer formed over the first dielectric layer, wherein the second dielectric layer includes an amorphous high-k dielectric material, a third dielectric layer formed over the second dielectric layer, and an upper electrode formed over the third dielectric layer.

Abstract: After a ferroelectric capacitor (1) is formed and before a wiring (15) to be a pad is formed, an alumina film (11) is formed as a diffusion suppressing film suppressing diffusion of hydrogen and moisture. Subsequently, the wiring (15) is formed and an SOG film (16) is formed thereon. Then, a silicon nitride film (17) is formed on the SOG film (16).

Abstract: A semiconductor device including: a substrate; an insulating film formed over the substrate; a copper interconnect, having a plurality of hillocks formed over the surface thereof, buried in the insulating film; a first insulating interlayer formed over the insulating film and the copper interconnect; a second insulating interlayer formed over the first insulating interlayer; and an electroconductive layer formed over the second insulating interlayer, wherein the top surface of at least one hillock highest of all hillocks is brought into contact with the lower surface of the second insulating interlayer is provided.

Abstract: Method of manufacturing a trench capacitor includes providing a substrate having a memory array region and a logic region, performing a shallow trench isolation (STI) process for forming at least a STI in the substrate within each of the memory array regions and the logic regions, forming a patterned hard mask and the hard mask exposing a portion of the STI and a portion of the substrate surrounding the STI on the substrate, performing a first etching process to form first deep trenches through the patterned hard mask, performing a second etching process to form second deep trenches extending downwardly from the first deep trenches respectively, and forming a capacitor structure in each of the first deep trenches and the second deep trenches.

Abstract: A metal-insulator-metal (MIM) capacitor that includes a silicon nitride (SiN) dielectric film is disclosed. The MIM capacitor includes a bottom electrode, a top electrode and a dielectric layer positioned between the bottom electrode and the top electrode. The dielectric layer includes a silicon nitride film that has a plurality of silicon-hydrogen bonds and a plurality of nitride-hydrogen bonds. A ratio of silicon-hydrogen bonds to nitride-hydrogen bonds is equal to or smaller than 0.5. Accordingly, the nitrogen-rich and compressive silicon nitride film can improve the breakdown voltage of the MIM capacitor.

Abstract: Various integrated circuit devices, including a lateral DMOS transistor, a quasi-vertical DMOS transistor, a junction field-effect transistor (JFET), a depletion-mode MOSFET, and a diode, are formed inside an isolation structure which includes a floor isolation region and a trench extending from the surface of the substrate to the floor isolation region. The trench may be filled with a dielectric material or may have a conductive material in a central portion with a dielectric layer lining the walls of the trench. Various techniques for terminating the isolation structure by extending the floor isolation region beyond the trench, using a guard ring, and a forming a drift region are described.

Abstract: A semiconductor device has a ferroelectric capacitor having a ferroelectric film, an interlayer insulating film having a first layer formed on the ferroelectric capacitor, a plug and a wiring connecting to the ferroelectric capacitor, and a dummy plug in the vicinity of the ferroelectric capacitor.

Abstract: There is provided a method for manufacturing a semiconductor device, including, forming a first insulating film on a semiconductor substrate, forming a capacitor on the first insulating film, forming a second insulating film covering the capacitor, forming a metal wiring on the second insulating film, forming a first capacitor protective insulating film covering the metal wiring and the second insulating film, forming an insulating sidewall on a side of the metal wiring, forming a third insulating film on the insulating sidewall, forming a hole by etching the third insulating film under a condition that an etching rate of the insulating sidewall would be lower than that of the third insulating film, and forming a conductive plug inside the hole.

Abstract: A semiconductor device with a first insulating film formed on a semiconductor substrate; a capacitor formed on the first insulating film and including a lower electrode, a ferroelectric film and an upper electrode; a second insulating film formed on the capacitor and the first insulating film; a first contact hole formed in the second insulating film; and a first conductive plug formed in the first contact hole and having a multilayer structure and including a first aluminum film.

Abstract: The present invention relates to a method for depositing a dielectric material comprising a transition metal oxide. In an initial step, a substrate is provided. In a further step, a first precursor comprising a transition metal containing compound, and a second precursor predominantly comprising at least one of water vapor, ozone, oxygen, or oxygen plasma are sequentially applied for depositing above the substrate a layer of a transition metal containing material. In another step, a third precursor comprising a dopant containing compound, and a fourth precursor predominantly comprising at least one of water vapor, ozone, oxygen, or oxygen plasma are sequentially applied for depositing above the substrate a layer of a dopant containing material. The transition metal comprises at least one of zirconium and hafnium. The dopant comprises at least one of barium, strontium, calcium, niobium, bismuth, magnesium, and cerium.

Abstract: A capacitor having a suitably large value for decoupling applications is formed in a trench defined by isolation structures such as recessed isolation or shallow trench isolation. The capacitor provides a contact area coextensive with an active area and can be reliably formed individually or in small numbers. Plate contacts are preferably made through implanted regions extending to or between dopant diffused regions forming a capacitor plate. The capacitor can be formed by a process subsequent to formation of isolation structures such that preferred soft mask processes can be used to form the isolation structures and process commonality and compatibility constraint are avoided while the capacitor forming processes can be performed in common with processing for other structures.

Abstract: A method for fabricating a semiconductor device including preparing a substrate provided with a first storage node contact, forming a second storage node contact over the first storage node contact, the second storage node contact leaning to one side, and forming a storage node of a capacitor over the second storage node contact.

Abstract: A method for fabricating a semiconductor device is disclosed. The semiconductor device includes a capacitor and a support insulator. The capacitor includes a cylindrical electrode. The cylindrical electrode comprises upper and lower sections. The lower section has a roughened inner surface and an outer surface supported by the support insulator. The upper section upwardly projects from the support insulator. An initial cylindrical electrode is formed, wherein the initial cylindrical electrode comprises an initial upper section and an initial lower section which correspond to the upper section and the lower section of the cylindrical electrode, respectively. The initial upper section is supported by the support insulator. Specific impurities are implanted into the initial upper section, wherein the specific impurities serve to prevent the initial upper section from being roughened.

Abstract: A micromechanical component includes a substrate, on which at least one layer sequence is situated, which includes at least one micromechanical functional element, and on which at least one layer sequence is situated that is able to act as at least one macroelectronic, passive component.

Abstract: A substrate with an embedded passive element and methods for manufacturing the same are provided, wherein the substrate includes an interlayer circuit board having a first conductive circuit, a dielectric layer, a first electrode, a second electrode, and a second conductive circuit. The dielectric layer formed on the interlayer circuit board has a first recess and a second recess for respectively accommodating the first electrode and the second electrode. The embedded passive element is formed by the first electrode, the second electrode, and the dielectric layer between the first electrode and the second electrode. The second conductive circuit electrically connects the first electrode and the second electrode.

Abstract: A thin film capacitor including a substrate, a capacitor portion having an upper conductor, a lower conductor, and a dielectric thin film, and a resin protective layer for protecting the capacitor portion. A barrier layer is interposed between the capacitor portion and the resin protective layer. The barrier layer includes a crystalline dielectric barrier layer formed in contact with the capacitor portion and having the same composition system as the dielectric thin film, and an amorphous inorganic barrier layer formed on the surface of the crystalline dielectric barrier layer and composed of silicon nitride having non-conductivity. The inorganic barrier layer prevents deterioration in the properties of the dielectric thin film by blocking diffusion of the constituent elements of the inorganic barrier layer toward the capacitor portion.

Abstract: A first device includes a micrometer-scale or smaller geometry first conductor. A second device includes a micrometer-scale or smaller second conductor. An actuator the first and second devices relative to each other between first and second positions. Signals are substantially coupled between the first and second conductors in the first position and not in the second position.

Abstract: A method of forming a dielectric layer in a capacitor adapted for use in a semiconductor device is disclosed. The method includes forming a first ZrO2 layer, forming an interfacial layer using a plasma treatment on the first ZrO2 layer, and forming a second ZrO2 layer on the interfacial layer.

Abstract: Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer, forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.

Abstract: According to an aspect of the present invention, there is provided a semiconductor storage apparatus including: a semiconductor substrate; and a ferroelectric capacitor including: a bottom electrode disposed above the semiconductor substrate, a ferroelectric layer disposed on the bottom electrode, and a top electrode disposed on the ferroelectric layer. The ferroelectric capacitor includes: a first sidewall portion located on a position where the top electrode is in contact with the ferroelectric layer, and a second sidewall portion located above the first sidewall portion. The first sidewall portion forms a first angle with a top face of the ferroelectric layer. The second sidewall portion forms a second angle with the top face. The first angle is larger than the second angle.

Abstract: Example embodiments relate to a capacitor including p-type doped silicon germanium and a method of manufacturing the capacitor. The capacitor may include a lower electrode, a dielectric layer, an upper electrode, a barrier layer and a capping layer. The lower electrode may have a cylindrical shape. The dielectric layer may be on the lower electrode. The dielectric layer may have a uniform thickness. The upper electrode may be on the dielectric layer. The upper electrode may have a more uniform thickness. The capping layer may be on the upper electrode. The capping layer may include a silicon germanium layer doped with p-type impurities. The barrier layer may be between the upper electrode and the capping layer to prevent (or reduce) the p-type impurities from infiltrating into the dielectric layer.

Abstract: The invention includes methods of forming rugged electrically conductive surfaces. In one method, a layer is formed across a substrate and subsequently at least partially dissociated to form gaps extending to the substrate. An electrically conductive surface is formed to extend across the at least partially dissociated layer and within the gaps. The electrically conductive surface has a rugged topography imparted by the at least partially dissociated layer and the gaps. The topographically rugged surface can be incorporated into capacitor constructions. The capacitor constructions can be incorporated into DRAM cells, and such DRAM cells can be incorporated into electrical systems.

Abstract: A semiconductor device includes an interlayer insulating film, a first interconnect material, and a second interconnect material. The interlayer insulating film is formed on a semiconductor substrate including an effective chip. The first interconnect material is formed in an interconnect pattern in the interlayer insulating film. The interconnect pattern is made in a region above the effective chip. The second interconnect material is formed in a groove pattern in the interlayer insulating film. The groove pattern is made between the region above the effective chip and a region above an edge of the semiconductor substrate. The second interconnect material separates the interlayer insulating film into an inner circumferential portion which includes the region above the effective chip and an outer circumferential portion which does not include the region above the effective chip.

Abstract: A thin film capacitor comprising a lower electrode formed on a predetermined surface, a dielectric layer formed on the lower electrode, and an upper electrode formed on the dielectric layer, wherein the end portion of the lower electrode is further covered by an insulator other than the dielectric layer.

Abstract: A multi-layer PrxCa1-xMnO3 (PCMO) thin film capacitor and associated deposition method are provided for forming a bipolar switching thin film. The method comprises: forming a bottom electrode; depositing a nanocrystalline PCMO layer; depositing a polycrystalline PCMO layer; forming a multi-layer PCMO film with bipolar switching properties; and forming top electrode overlying the PCMO film. If the polycrystalline layers are deposited overlying the nanocrystalline layers, a high resistance can be written with narrow pulse width, negative voltage pulses. The PCMO film can be reset to a low resistance using a narrow pulse width, positive amplitude pulse. Likewise, if the nanocrystalline layers are deposited overlying the polycrystalline layers, a high resistance can be written with narrow pulse width, positive voltage pulses, and reset to a low resistance using a narrow pulse width, negative amplitude pulse.

Abstract: A process of making a stud capacitor structure is disclosed. The process includes embedding the stud in a dielectric stack. In one embodiment, the process includes forming an electrically conductive seed film in a contact corridor of the dielectric stack. A storage cell stud is also disclosed. The storage cell stud can be employed in a dynamic random-access memory device. An electrical system is also disclosed that includes the storage cell stud.

Abstract: A process of making a stud capacitor structure is disclosed. The process includes embedding the stud in a dielectric stack. In one embodiment, the process includes forming an electrically conductive seed film in a contact corridor of the dielectric stack. A storage cell stud is also disclosed. The storage cell stud can be employed in a dynamic random-access memory device. An electrical system is also disclosed that includes the storage cell stud.

Abstract: A semiconductor device and a fabrication method thereof provides a plug structure composed of a diffusion barrier layer formed at the bottom and on the sides of a contact hole and an oxidation barrier layer formed on the diffusion barrier layer that fills up the inside of the contact hole. This invention prevents contact resistance of a bottom electrode and a plug from increasing as well as implementing high-speed operation and improving the reliability of the semiconductor device.

Abstract: A semiconductor device including a semiconductor substrate, a capacitor formed above the semiconductor substrate, a first interlayer insulating film formed above the capacitor and having a trench, a wiring formed above the capacitor and formed in the trench, the wiring have a top surface flush with a top surface of the first interlayer insulating film, a first hydrogen barrier film formed in contact with the top surface of the wiring and the top surface of the first interlayer insulating film and preventing hydrogen from diffusing into the capacitor and a second interlayer insulating film formed on the first hydrogen barrier film.

Abstract: A capacitor with a nano-composite dielectric layer and a method for fabricating the same are provided. A dielectric layer of a capacitor includes a nano-composite layer formed by mixing X number of different sub-layers, X being a positive integer greater than approximately 1. A method for forming a dielectric layer of a capacitor includes: forming a nano-composite layer by mixing X number of different sub-layers in the form of a nano-composition, X being a positive integer greater than approximately 1; and densifying the nano-composite layer.