Circuit Arrangement Of General Character For Device (epo) Patents (Class 257/E31.113)
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Publication number: 20110244625Abstract: An improved, lower cost method of processing substrates, such as to create solar cells, is disclosed. The doped regions are created on the substrate, using a mask or without the use of lithography or masks. After the implantation is complete, visual recognition is used to determine the exact region that was implanted. This information can then be used by subsequent process steps to crate a suitable metallization layer and provide alignment information. These techniques can also be used in other ion implanter applications. In another aspect, a dot pattern selective emitter is created and imaging is used to determine the appropriate metallization layer.Type: ApplicationFiled: April 6, 2010Publication date: October 6, 2011Applicant: VARIAN SEMICONDUCTOR EQUIPMENT ASSOCIATES, INC.Inventors: Benjamin Riordon, Russell Low, Atul Gupta, William Weaver
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Publication number: 20110227184Abstract: An apparatus of one aspect includes a photodetector array, and a peripheral region at a periphery of the photodetector array. A thinner interconnect line corresponding to the photodetector array is disposed within one or more insulating layers. A thicker interconnect line corresponding to the peripheral region is disposed within the one or more insulating layers. Other apparatus, methods, and systems are also disclosed.Type: ApplicationFiled: March 18, 2010Publication date: September 22, 2011Inventors: Duli Mao, Vincent Venezia, Howard Rhodes, Hsin Chih Tai, Yin Qian
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Publication number: 20110221018Abstract: An electronic device package comprises a substrate 110 having a first surface 110a and a second surface 110b opposite the first surface. An electronic device 120, 130 is positioned on the first surface 110a. An isolation layer 140 extends over at least a portion of the top surface of the electronic device. A redistribution layer 145 having one or more I/O lines extends over the isolation layer and the top surface of the electronic device. The RDL layer connects the electronic device to one or more first vias 160 which pass through the substrate 110 to the second surface 110b thereof. The electronic device may be an image sensor. A microlens 220 and protective parylene layer 230 may be fabricated over the image sensor. A method of manufacturing the electronic device package is also disclosed.Type: ApplicationFiled: March 15, 2010Publication date: September 15, 2011Inventors: Xunqing Shi, Dan Yang, Pui Chung Simon Law
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Publication number: 20110223705Abstract: A process for assembling a camera module is provided. Firstly, a first conductive bump and a second conductive bump are placed on a signal terminal of a substrate and a contact pad of an image sensing chip, respectively. Then, the substrate and the image sensing chip are laminated, so that the first conductive bump and the second conductive bump are combined together and the signal terminal of the substrate and the contact pad of the image sensing chip are electrically connected with each other. Then, an underfill is applied to a region between the substrate and the image sensing chip. Since the two conductive bumps are connected with each other by the assembling process, the quality of the camera module of the present invention is enhanced.Type: ApplicationFiled: August 2, 2010Publication date: September 15, 2011Applicant: PRIMAX ELECTRONICS LTD.Inventors: Chien-Nan Yu, Chung-Feng Tsao, Ying-Chieh Chen, Szu-Hao Lyu, Ching-Lung Jao, Hang-Kau Khor
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Publication number: 20110198719Abstract: An electronic device having a plurality of electronic components placed on a substrate, each component being constituted by a portion of a layer of active material joined mechanically to the substrate by an electrically conductive joining element pertinent to it, the layer of active material having at least one trench delimiting, at least in part, groups of electronic components each having at least two components and forming successive strips, two successive strips having a common boundary.Type: ApplicationFiled: July 6, 2009Publication date: August 18, 2011Applicant: ETAT FRANCAIS REPRESENTE PAR LE DELEGUE GENERAL POUR L'ARMEMENTInventor: Pierre Burgaud
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Patent number: 7989907Abstract: Provided is a backside-illuminated solid-state image pickup device capable of allowing peripheral circuits to produce stable waveforms and thereby achieving image characteristics with less noise, the device including: a first-conductivity-type semiconductor layer having a first principal surface and a second principal surface opposed to the first principal surface and also having a pixel area and an analog circuit area; a first P type area formed to lie between the second principal surface and the first principal surface in the analog circuit area; a metal layer formed at least partially on the second principal surface of the first P type area; a VSS electrode electrically connected to the metal layer; a photo-conversion area formed in the pixel area and used to accumulate electric charges generated by photoelectric conversion; and a microlens provided on the second principal surface in the pixel area so as to correspond to the photo-conversion area.Type: GrantFiled: October 16, 2009Date of Patent: August 2, 2011Assignee: Kabushiki Kaisha ToshibaInventor: Ikuko Inoue
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Publication number: 20110162694Abstract: A carrier for a plurality of solar cells has a dedicated holding location for each cell for the purpose of mounting it. The carrier is designed like a plate and substantially as a closed plate, each holding location having suction means for a mounted solar cell. A plurality of small holes or passages are provided per holding location in order to come at a mounted solar cell or to reach the latter even from the other side of the carrier at its underside mounted thereon, for example in order to carry out contact soldering.Type: ApplicationFiled: February 28, 2011Publication date: July 7, 2011Applicant: Schmid Technology Systems GmbHInventors: Jens Kalmbach, Walter Feist, Gerhard Klingebiel, Patrik Müller
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Publication number: 20110162701Abstract: A photovoltaic cell is provided herein. The photovoltaic cell includes a substrate whereby at least one interconnects may be formed over the substrate to facilitate energy conversion of the photovoltaic cell. In this embodiment, a conformal layer may be deposited over the interconnects, the conformal layer having a thickness of up to about 100 nm, and whereby the conformal layer is designed to permit external radiation to pass through to the interconnects so as to enhance the efficiency of energy conversion by at least about 25% as measured at standard test condition. In another embodiment, the interconnects of the photovoltaic cell may have tapered profile as to facilitate collection of diffused external radiation. In some instances, the tapered profile may facilitate in diverting the diffused external radiation to the interconnects for enhancing energy conversion of the photovoltaic cell. A method for method of manufacturing a photovoltaic cell is also provided.Type: ApplicationFiled: January 3, 2010Publication date: July 7, 2011Inventors: Claudio Truzzi, Steve Lerner
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Publication number: 20110146759Abstract: A solar cell mode and a method for manufacturing the same are disclosed. The solar battery module in accordance with the present invention includes a plurality of solar cells arranged in row and column directions; and a conductive ribbon electrically connecting the plurality of solar cells, wherein each of the solar cells has a structure in which a first photoelectric element including a polycrystalline semiconductor layer and a second photoelectric element including an amorphous semiconductor layer are stacked.Type: ApplicationFiled: August 17, 2009Publication date: June 23, 2011Inventors: Yoo Jin Lee, Dong Jee Kim, Seok Pil Jang, Young Ho Lee, Byung Lee, II, Taek Yong Jang
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Publication number: 20110139238Abstract: A process for the production of a MWT silicon solar cell comprising the steps: (1) providing a p-type silicon wafer with (i) holes forming vias between the front-side and the back-side of the wafer and (ii) an n-type emitter extending over the entire front-side and the inside of the holes, (2) applying a conductive metal paste to the holes of the silicon wafer to provide at least the inside of the holes with a metallization, (3) drying the applied conductive metal paste, and (4) firing the dried conductive metal paste, whereby the wafer reaches a peak temperature of 700 to 900° C., wherein the conductive metal paste has no or only poor fire-through capability and comprises (a) at least one particulate electrically conductive metal selected from the group consisting of silver, copper and nickel and (b) an organic vehicle.Type: ApplicationFiled: December 8, 2010Publication date: June 16, 2011Applicant: E. I. DU PONT DE NEMOURS AND COMPANYInventors: Kenneth Warren Hang, Giovanna Laudisio, Alistair Graeme Prince, Richard John Sheffield Young
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Publication number: 20110140225Abstract: In a first interlevel insulating film, a first region which is made of the first interlevel insulating film and in which first wiring films are not provided is formed to be located above a first light receiving part of the plurality of light receiving parts, and a second region which is made of the first interlevel insulating film and in which the first wiring films are not provided is formed to be located above a second light receiving part of the plurality of light receiving parts which is adjacent to the first light receiving part. A space between ones of the first wiring films with the first region interposed therebetween is larger than a space between ones of the first wiring films with the second region interposed therebetween.Type: ApplicationFiled: November 19, 2010Publication date: June 16, 2011Inventor: Masafumi TSUTSUI
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Publication number: 20110140223Abstract: A light detecting apparatus includes an SOI substrate. In the SOI substrate, a semiconductor layer and a silicon substrate are laminated via an insulating layer. The semiconductor layer has a light receiving unit and a circuit unit formed therein. The light detecting apparatus also includes an interlayer insulating film formed on a first main surface of the SOI substrate. The light detecting apparatus also includes a front surface circuit wiring embedded in the interlayer insulating film. The light detecting apparatus also includes a front surface pseudo-wiring having a grid unit. The grid unit has at least one opening allowing passage of a light of a predetermined wavelength range to the light receiving unit. The light detecting apparatus also includes a rear surface circuit wiring and a rear surface pseudo-wiring formed on a second main surface of the SOI substrate.Type: ApplicationFiled: November 22, 2010Publication date: June 16, 2011Applicant: OKI SEMICONDUCTOR CO., LTD.Inventor: Noriyuki MIURA
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Publication number: 20110133057Abstract: An anti-eclipse circuit for an imager is formed from pixel circuitry over the same semiconductor substrate as the imaging pixels. More specifically, two adjacent pixel circuits are modified to form an amplifier. One input of the amplifier is adapted to receive a reset signal from one of the pixel circuits while another input is adapted to be set at a predetermined offset voltage from the output of the amplifier. The amplifier is preferably a unity gain amplifier, so that the output of the amplifier set to a voltage level equal to the predetermined offset from the voltage level of the reset signal. Accordingly, the anti-eclipse circuit outputs a reference voltage at predetermined level from the reset voltage of a pixel and does not need to be calibrated for fabrication related variances in reset voltages.Type: ApplicationFiled: February 17, 2011Publication date: June 9, 2011Inventor: Espen A. Olsen
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Patent number: 7956347Abstract: A novel package that integrates components for a modulating retro reflector into a single package is disclosed according to various embodiments. According to some embodiments the package is configured to secure a retro reflector, a quantum well modulator and photodiode. In some embodiments, the package may include interconnects to surface mount to a circuit board. Such interconnects may be coupled with the photodiode and/or the quantum well modulator. In some embodiments, the package may be constructed of liquid crystal polymers and/or may include one or more windows.Type: GrantFiled: July 11, 2008Date of Patent: June 7, 2011Assignee: Cubic CorporationInventors: Mahyar Dadkhah, Tony Maryfield, Thomas Davidson
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Patent number: 7948014Abstract: The invention relates to an electronic device having a semiconductor die comprising at least one RF-transistor (RFT) occupying a total RF-transistor active area (ARFT) on the die (DS). The total RF-transistor active area (ARFT) includes at least one transistor channel (C) having a channel width (W) and a channel length (L), and at least one bias cell (BC) for biasing the RF-transistor (RFT). The total bias cell active area (ABC) includes at least one transistor channel (C) having a channel width (W) and a channel length (L). The at least one bias cell (BC) occupies a total bias cell active area (ABC) on the die (SD). The total RF-transistor active area (ARFT) is substantially greater than the total bias cell active area (ABC). The total bias cell active area (ABC) has a common centre of area (COABC). The total RF-transistor active area (ARFT) has a common centre of area (COARF).Type: GrantFiled: May 11, 2006Date of Patent: May 24, 2011Assignee: NXP B.V.Inventor: Josephus Henricus Bartholomeus Van Der Zanden
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Patent number: 7944010Abstract: The present invention is to provide an electromagnetic wave detecting element that can suppress a decrease in utilization efficiency of electromagnetic waves at sensor portions. An upper electrode of each of plural sensor portions, that are provided in correspondence with intersection portions of plural scan lines and plural signal lines disposed to intersect one another, is electrically connected to any other adjacent upper electrode. At each group of sensor portions whose upper electrodes are electrically connected, a common electrode line and the upper electrode of any sensor portion belonging to that group of sensor portions are connected by a contact pad via a contact hole formed in an insulating film and at a connection place of a number that is less than a number of sensor portions belonging to that group of sensor portions.Type: GrantFiled: February 26, 2009Date of Patent: May 17, 2011Assignee: FUJIFILM CorporationInventor: Yoshihiro Okada
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Publication number: 20110089515Abstract: A semiconductor light receiving device includes: a first semiconductor light receiving element that is provided on a semiconductor substrate and has a mesa structure having an upper electrode to be coupled to an electrode wiring of a mounting carrier and a lower electrode; a first mesa that is provided on the semiconductor substrate and has an upper electrode coupled electrically to a lower electrode of the first semiconductor light receiving element with a wiring provided on the semiconductor substrate; and a second mesa that is provided on the semiconductor substrate and has an upper electrode that has a same electrical potential as the upper electrode of the first semiconductor light receiving element when coupled to the electrode wiring on the mounting carrier.Type: ApplicationFiled: September 29, 2010Publication date: April 21, 2011Applicant: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.Inventor: Yuji Koyama
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Publication number: 20110073971Abstract: A MOS solid-state imaging device having: a semiconductor substrate provided with a pair of source and drain regions in a pixel area, the pair of source and drain regions constituting part of a transistor in the pixel area; an insulating film formed over the semiconductor substrate; a wiring layer formed over the insulating film; and a contact plug penetrating through the insulating film to connect either one of the pair of source and drain regions with the wiring layer, wherein a surface area of said one of the pair of source and drain regions is silicided, the surface area contacting with the contact plug, and a width of the surface area is equal to a width of the contact plug.Type: ApplicationFiled: September 29, 2010Publication date: March 31, 2011Inventor: Tomotsugu TAKEDA
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Publication number: 20110068429Abstract: An image sensor array includes a substrate layer, a metal layer, an epitaxial layer, a plurality of imaging pixels, and a contact dummy pixel. The metal layer is disposed above the substrate layer. The epitaxial layer is disposed between the substrate layer and the metal layer. The imaging pixels are disposed within the epitaxial layer and each include a photosensitive element for collecting an image signal. The contact dummy pixel is dispose within the epitaxial layer and includes an electrical conducting path through the epitaxial layer. The electrical conducting path couples to the metal layer above the epitaxial layer.Type: ApplicationFiled: August 2, 2010Publication date: March 24, 2011Applicant: OMNIVISION TECHNOLOGIES, INC.Inventors: Vincent Venezia, Duli Mao, Hsin-Chih Tai, Yin Qian, Howard E. Rhodes
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Patent number: 7911019Abstract: A reflowable camera module has a set of solder joints formed on a bottom surface of the camera module that provide electrical signal and power connections between the camera module and a printed circuit substrate. The solder joints are susceptible to failure caused by shear forces, particularly in corner regions. Additional localized mechanical supports are provided to protect those solder joints carrying power and electrical signals for the camera module. The localized mechanical supports are formed outside of a region containing the solder joints carrying power and electrical signals. The localized mechanical supports may include dummy solder joints formed in corner regions and/or dummy leads used to support the camera module. Solder joint reliability is enhanced without requiring the use of an underfill encapsulant.Type: GrantFiled: March 16, 2010Date of Patent: March 22, 2011Assignee: OmniVision Technologies, Inc.Inventors: Jari Hiltunen, Ian Montandon
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Publication number: 20110062541Abstract: The present invention relates to novel compounds that are useful as ligands in organometallic dyes. More particularly, the invention relates to dyes comprising the compounds, said dyes being sensitizing dyes useful in solar cell technology. According to an embodiment, the present invention discloses new ruthenium dyes and their application in dye-sensitized solar cells (DSC). The referred ruthenium dyes with new structural features can be easily synthesized, show more than 85% light-to-electricity conversion efficiency and a higher than 9% cell efficiency.Type: ApplicationFiled: February 27, 2009Publication date: March 17, 2011Inventors: Feifei Gao, Yuan Wang, Jing Zhang, Peng Wang, shaik Mohammad Zakeeruddin, Michael Graetzel
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Publication number: 20110062336Abstract: A novel pixel circuit and multi-dimensional array for receiving and detecting black body radiation in the SWIR, MWIR or LWIR frequency bands. An electromagnetic thermal sensor and imaging system is provided based on the treatment of thermal radiation as an electromagnetic wave. The thermal sensor and imager functions essentially as an electromagnetic power sensor/receiver, operating in the SWIR (200-375 THz), MWIR (60-100 THz), or LWIR (21-38 THz) frequency bands. The thermal pixel circuit of the invention is used to construct thermal imaging arrays, such as 1D, 2D and stereoscopic arrays. Various pixel circuit embodiments are provided including balanced and unbalanced, biased and unbiased and current and voltage sensing topologies. The pixel circuit and corresponding imaging arrays are constructed on a monolithic semiconductor substrate using in a stacked topology. A metal-insulator-metal (MIM) structure provides rectification of the received signal at high terahertz frequencies.Type: ApplicationFiled: September 13, 2010Publication date: March 17, 2011Inventor: David Ben-Bassat
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Publication number: 20110049336Abstract: A solid-state imaging device includes: a plurality of substrates stacked via a wiring layer or an insulation layer; a light sensing section that is formed in a substrate, of the plurality of substrates, disposed on a light incident side and that generates a signal charge in accordance with an amount of received light; and a contact portion that is connected to a non-light incident-surface side of the substrate in which the light sensing section is formed and that supplies a desired voltage to the substrate from a wire in a wiring layer disposed on a non-light incident side of the substrate.Type: ApplicationFiled: August 20, 2010Publication date: March 3, 2011Applicant: SONY CORPORATIONInventor: Takeshi Matsunuma
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Publication number: 20110042765Abstract: An image sensor including a first region where a pad is to be formed, and a second region where a light-receiving element is to be formed. A pad is formed over a substrate of the first region. A passivation layer is formed over the substrate of the first and second regions to expose a portion of the pad. A color filter is formed over the passivation layer of the second region. A microlens is formed over the color filter. A bump is formed over the pad. A protective layer is formed between the bump and the pad to expose the portion of the pad.Type: ApplicationFiled: August 4, 2010Publication date: February 24, 2011Inventor: Sang Hyuk Park
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Publication number: 20110036390Abstract: Provided are novel photovoltaic module structures and fabrication techniques that include a composite encapsulant disposed and substantially filling voids between at least one sealing sheet and one or more photovoltaic cells. The composite encapsulant contains a bulk encapsulant and filler uniformly distributed throughout the bulk encapsulant. In certain embodiments, at least about 30% by weight of the composite encapsulant is the filler. Adding certain fillers into polymer-based bulk encapsulants in such large amounts reduces encapsulation costs and improves certain performance characteristics of the resulting composite encapsulants. In certain embodiments, the composite encapsulants have better temperature stability, UV stability, mechanical integrity, and/or adhesion than traditional encapsulants. Also, in certain embodiments, the added fillers do not substantially alter the optical properties of initial bulk encapsulants.Type: ApplicationFiled: July 16, 2010Publication date: February 17, 2011Applicant: MIASOLEInventors: Donald S. Nelson, Todd Krajewski
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Publication number: 20110037134Abstract: In a solid-state image sensor device, the efficiency of light collection to a light-receiving region of a photodiode PD through a microlens is enhanced by arranging a wiring line configuration. Each of the first metal layer and the second metal layer is arranged to have a ring-like portion formed along a profile of the light-receiving region of the photodiode PD in a fashion that an upper position over the photodiode PD is surrounded by the first and second metal layers and a third metal layer.Type: ApplicationFiled: July 23, 2010Publication date: February 17, 2011Applicant: Hitachi, Ltd.Inventors: Shinya SUGINO, Satoshi Sakai, Yusuke Nonaka, Tomohiro Saito, Tomoyasu Furukawa, Hiroyuki Hayashi
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Publication number: 20110024866Abstract: An integrated circuit includes a substrate having a bonding pad region and a non-bonding pad region. A relatively large via, called a “big via,” is formed on the substrate in the bonding region. The big via has a first dimension in a top view toward the substrate. The integrated circuit also includes a plurality of vias formed on the substrate in the non-bonding region. The plurality of vias each have a second dimension in the top view, the second dimension being substantially less than the first dimension.Type: ApplicationFiled: July 29, 2009Publication date: February 3, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Uway Tseng, Lin-June Wu, Yu-Ting Lin
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Publication number: 20110029246Abstract: An instrument for performing measurements downhole includes: at least one gamma-ray detector with azimuthal sensitivity equipped for discriminating energy of incident gamma-rays. This instrument is equipped with or without a neutron or gamma-ray source. A method and computer program product providing the azimuthal sensitivity of the instrument is provided.Type: ApplicationFiled: July 30, 2010Publication date: February 3, 2011Applicant: BAKER HUGHES INCORPORATEDInventors: Anton Nikitin, Alexandr A. Vinokurov, Richard R. Pemper
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Publication number: 20110024867Abstract: An integrated circuit includes a substrate having a bonding pad region and a non-bonding pad region. A relatively large via, called a “big via,” is formed on the substrate in the bonding region. The big via has a first dimension in a top view toward the substrate. The integrated circuit also includes a plurality of vias formed on the substrate in the non-bonding region. The plurality of vias each have a second dimension in the top view, the second dimension being substantially less than the first dimension.Type: ApplicationFiled: November 11, 2009Publication date: February 3, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Uway Tseng, Lin-June Wu, Yu-Ting Lin
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Publication number: 20110017284Abstract: A geometric diode, method and device applications are described. The geometric diode is produced including a device body formed from an electrically conductive material having an equilibrium mobile charge density, and having a device surface configuration. The material has a charge carrier mean free path with a mean free path length and the device body size is selected based on said the free path length to serve as an electrically conductive path between first and second electrodes delimited by the device surface configuration that is asymmetric with respect to a forward flow of current in a forward direction from the first electrode to the second electrode as compared to a reverse current flow in an reverse direction from the second electrode to the first electrode. A system includes an antenna for receiving electromagnetic radiation coupled with the geometric diode antenna to receive the electromagnetic radiation to produce an electrical response.Type: ApplicationFiled: July 17, 2009Publication date: January 27, 2011Inventor: Garret Moddel
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Publication number: 20110019050Abstract: According to one embodiment, a solid-state imaging device includes a pixel region which is configured such that a photoelectric conversion unit and a signal scanning circuit unit are included in a semiconductor substrate, and a matrix of unit pixels is disposed, and a driving circuit region which is configured such that a device driving circuit for driving the signal scanning circuit unit is disposed on the semiconductor substrate, wherein the photoelectric conversion unit is provided on a back surface side of the semiconductor substrate, which is opposite to a front surface of the semiconductor substrate where the signal scanning circuit unit is formed, and the unit pixel includes an insulation film which is provided in a manner to surround a boundary part with the unit pixel that neighbors and defines a device isolation region.Type: ApplicationFiled: August 27, 2010Publication date: January 27, 2011Inventor: Hirofumi YAMASHITA
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Publication number: 20110019709Abstract: The present invention provides a method of manufacturing a semiconductor device realizing improved yield. The semiconductor device includes: a substrate having a top face, an under face, and side faces; an optical function unit formed on the top face; a plurality of electrode pads formed on the under face; and a wiring formed on at least the side face and electrically connecting the optical function unit and at least one of the plurality of electrode pads.Type: ApplicationFiled: July 8, 2010Publication date: January 27, 2011Applicant: Sony CorporationInventors: Yuji Masui, Takahiro Arakida, Naoki Jogan, Rintaro Koda, Kouichi Kondo
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Publication number: 20110019063Abstract: A solid-state imaging device includes a pixel including a buried photodiode formed inside a substrate, a buried floating diffusion formed at a depth equal to that of the buried photodiode in the substrate so as to face a bottom of a trench portion formed in the substrate, and a buried gate electrode formed at the bottom of the trench portion in order to transfer a signal charge from the buried photodiode to the buried floating diffusion.Type: ApplicationFiled: July 20, 2010Publication date: January 27, 2011Applicant: SONY CORPORATIONInventors: Taiichiro Watanabe, Kazufumi Watanabe
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Publication number: 20110020974Abstract: A stacked photovoltaic device which includes a first photovoltaic unit having an amorphous silicon layer 8 as a photoelectric conversion layer, and a second photovoltaic unit having a microcrystalline silicon layer 5 as a photoelectric conversion layer and succeeding backwardly from the first photovoltaic unit closer to a light incidence plane. The microcrystalline silicon layer 5 serving as the photoelectric conversion layer in the second photovoltaic unit has a ratio ?2 (?I(Si—O)/I(Si—H)) greater than a ratio ?1 (?I(Si—O)/I(Si—H)) of the amorphous silicon layer 8 serving as the photoelectric conversion layer in the first photovoltaic unit, where I(Si—O) is a peak area for the Si—O stretching mode of each silicon layer and I(Si—H) is a peak area for the Si—H stretching mode of each silicon layer when the amorphous and microcrystalline silicon layers 8 and 5 are measured by infrared absorption spectroscopy.Type: ApplicationFiled: October 7, 2010Publication date: January 27, 2011Applicant: SANYO ELECTRIC CO., LTD.Inventor: Masaki SHIMA
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Publication number: 20110011437Abstract: A solar cell includes a plurality of unit cells connected in series and a first partition portion. Each of the unit cells includes a substrate, a first electrode layer formed on the substrate, a semiconductor layer formed on the first electrode layer, and a second electrode layer formed on the semiconductor layer. The first partition portion has insulation properties and partitions the first electrode layers of the unit cells on the substrate with each the first electrode layers being disposed respectively in a region partitioned by the first partition portion.Type: ApplicationFiled: July 6, 2010Publication date: January 20, 2011Applicant: SEIKO EPSON CORPORATIONInventors: Atsushi DENDA, Hiromi SAITO
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Publication number: 20110011458Abstract: A method is for manufacturing a solar cell having a plurality of unit cells connected in series, each of the unit cells including a substrate, a first electrode layer formed on the substrate, a semiconductor layer formed on the first electrode layer, and a second electrode layer formed on the semiconductor layer. The method includes forming a fluid-repellent partition portion on the substrate to partition a plurality of regions respectively corresponding to the first electrode layers of the unit cells, and applying a liquid material including a first electrode material for forming the first electrode layers on the regions of the substrate that are partitioned by the partition portion, and baking the applied liquid material to form the first electrode layers.Type: ApplicationFiled: July 6, 2010Publication date: January 20, 2011Applicant: SEIKO EPSON CORPORATIONInventors: Atsushi DENDA, Hiromi SAITO
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Publication number: 20110005582Abstract: A photovoltaic device is disclosed. In one aspect, the device is formed in a semiconductor substrate. It has a radiation receiving front surface and a rear surface. The device may have a first region of one conductivity type, a second region with the opposite conductivity type adjacent to the front surface, and an antireflection layer. The rear surface is covered by a dielectric layer covering also an inside surface of the via. The front surface has current collecting conductive contacts. The rear surface has conductive contacts extending through the dielectric. A conductive path is in the via for photogenerated current from the front surface. By having the dielectric all over, no aligning and masking is needed. The same dielectric serves to insulate, provide thermal protection, and helps in surface and bulk passivation. It also avoids the need for a junction region near the via, hence reducing unwanted recombination currents.Type: ApplicationFiled: June 2, 2010Publication date: January 13, 2011Applicants: IMEC, PhotovoltechInventors: Jozef Szlufcik, Christophe Allebe, Frederic Dross, Guy Baucarne
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Publication number: 20100314703Abstract: An exemplary image sensor package includes a base substrate, an image sensor, and a number of wires. The base substrate contains carbon nanotubes and alumina, and includes a number of base pads. The image sensor is mounted on the base substrate, and includes a sensing portion and a number of contacts. The wires electrically connect the base pads to the respective contacts.Type: ApplicationFiled: December 9, 2009Publication date: December 16, 2010Applicant: HON HAI PRECISION INDUSTRY CO., LTD.Inventor: GA-LANE CHEN
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Publication number: 20100314705Abstract: A semiconductor device module is provided, including a number of n semiconductor devices formed on a substraten being an integer?2; each semiconductor device having a stack of a first contact layer region, a semiconductor layer region, and a second contact layer region wherein the first contact layer region of each (n?1)th semiconductor device is connected to the second contact layer region of the nth semiconductor device by an interconnection; and wherein, of the first and second contact layer regions, at least the first contact layer region of at least one of the semiconductor devices has a varying thickness, the thickness being maximum at the interconnection.Type: ApplicationFiled: June 17, 2009Publication date: December 16, 2010Applicant: APPLIED MATERIALS, INC.Inventors: Tobias Repmann, Axel Straub
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Publication number: 20100308430Abstract: A semiconductor device comprises a semiconductor substrate, and a multilayer wiring structure arranged on the semiconductor substrate, the multilayer wiring structure including a plurality of first electrically conductive lines, an insulating film covering the plurality of first electrically conductive lines, and a second electrically conductive line arranged on the insulating film so as to intersect the plurality of first electrically conductive lines, wherein the insulating film has gaps in at least some of a plurality of regions where the plurality of first electrically conductive lines and the second electrically conductive line intersect each other, and a width of the gap in a direction along the second electrically conductive line is not larger than a width of the first electrically conductive line.Type: ApplicationFiled: May 19, 2010Publication date: December 9, 2010Applicant: CANON KABUSHIKI KAISHAInventor: Takeshi Aoki
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Publication number: 20100307557Abstract: A multi junction photoelectric conversion device that can be manufactured by a simple method is provided. In addition, a photoelectric conversion device whose mechanical strength is increased without complicating a manufacturing process is provided. A photoelectric conversion device includes a first cell having a photoelectric conversion function, a second cell having a photoelectric conversion function, and a structure body including a fibrous body, which firmly attaches and electrically connects the first cell and the second cell to each other. Accordingly, a multi-junction photoelectric conversion device in which semiconductor junctions are connected in series and sufficient electrical connection between p-i-n junctions is ensured can be provided.Type: ApplicationFiled: May 27, 2010Publication date: December 9, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei YAMAZAKI, Yukie SUZUKI, Kazuo NISHI
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Publication number: 20100301444Abstract: Photoelectric conversion elements are arranged in a pixel area. A circuit area is arranged around the pixel area. An interconnect including copper is arranged in the pixel area and circuit area. A cap layer is arranged on the interconnect. Wherein the cap layer except a part on the interconnect is removed from the pixel area and circuit area.Type: ApplicationFiled: March 17, 2010Publication date: December 2, 2010Inventor: Hidetoshi KOIKE
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Publication number: 20100304526Abstract: Photovoltaic module comprising a transparent substrate (1), a transparent front electrode layer (2), a semiconducting layer (3) of microcrystalline or micromorphous silicon and a rear electrode layer (4), said layers structured to form cells (C1, C2, C3) electrically separated by separating lines (5, 6, 7) and electrically connected in series. A laser beam (14) is used to generate at least in rear electrode layer (4) separating line sections (18, 18?) interconnected to form continuous separating lines (7) by connecting sections (19, 20) extending at an angle (?) to separating line sections (18, 18?).Type: ApplicationFiled: May 20, 2010Publication date: December 2, 2010Inventors: Walter Psyk, Joerg Reuner, Hermann Wagner
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Patent number: 7843021Abstract: The MEMS package has a mounting substrate on which one or more transducer chips are mounted wherein the mounting substrate has an opening. A top cover is attached to and separated from the mounting substrate by a spacer forming a housing enclosed by the top cover, the spacer, and the mounting substrate and accessed by the opening. Electrical connections are made between the one or more transducer chips and the mounting substrate and/or between the one or more transducer chips and the top cover. A bottom cover can be mounted on a bottom surface of the mounting substrate wherein a hollow chamber is formed between the mounting substrate and the bottom cover, wherein a second opening in the bottom cover is not aligned with the first opening. Pads on outside surfaces of the top and bottom covers can be used for further attachment to printed circuit boards. The top and bottom covers can be a flexible printed circuit board folded under the mounting substrate.Type: GrantFiled: February 28, 2008Date of Patent: November 30, 2010Assignee: Shandong Gettop Acoustic Co. Ltd.Inventors: Wang Zhe, Chong Ser Choong
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Publication number: 20100297800Abstract: A solar cell panel and method of forming a solar cell panel. The method includes a: forming an electrically conductive bus bar on a top surface of a bottom cover plate; forming an electrically conductive contact frame proximate to a bottom surface of a top cover plate, the top cover plate transparent to visible light; and placing an array of rows and columns of solar cell chips between the bottom cover plate and the top cover plate, each solar cell chip of the array of solar cell chips comprising an anode adjacent to a top surface and a cathode adjacent to a bottom surface of the solar cell chip, the bus bar electrically contacting each anode of each solar cell chip of the array of solar cell chips and the contact frame contacting each anode of each solar cell chip of the array of solar cell chips.Type: ApplicationFiled: August 3, 2010Publication date: November 25, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Harold John Hovel, Rainer Klaus Krause, Xiaoyan Shao, Steven Erik Steen
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Publication number: 20100297801Abstract: Process for producing strip-shaped and/or point-shaped electrically conducting contacts on a semiconductor component like a solar cell, includes the steps of applying a moist material forming the contacts in a desired striplike and/or point-like arrangement on at least one exterior surface of the semiconductor component; drying the moist material by heating the semiconductor component to a temperature T1 and keeping the semiconductor element at temperature T1 over a time t1; sintering the dried material by heating the semiconductor component to a temperature T2 and keeping the semiconductor component at temperature T2 over a time t2; cooling the semiconductor component to a temperature T3 that is equal or roughly equal to room temperature, and keeping the semiconductor component at temperature T3 over a time T3; cooling the semiconductor component to a temperature T4 with T4??35° C.Type: ApplicationFiled: May 17, 2010Publication date: November 25, 2010Applicant: SCHOTT SOLAR GMBHInventors: Henning NAGEL, Wilfried SCHMIDT, Ingo SCHWIRTLICH, Dieter FRANKE
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Publication number: 20100295099Abstract: An image sensing device and packaging method thereof is disclosed. The packaging method includes the steps of a) providing an image sensing module, having a light-receiving region exposed, on a first substrate; b) forming a plurality of first contacts around the light-receiving region on the image sensing module; c) providing a second substrate, having a plurality of second contacts corresponding to the plurality of first contacts and an opening for allowing the light-receiving region to be exposed while the second substrate is placed over the image sensing module, the plurality of second contacts being disposed around the opening; d) connecting the plurality of first contacts and the plurality of second contacts; and e) disposing a transparent lid above the light-receiving region, on a side of the second substrate which is opposite to the plurality of second contacts.Type: ApplicationFiled: August 2, 2010Publication date: November 25, 2010Inventors: Chi-Chih HUANG, Chih-Yang Hsu
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Publication number: 20100289104Abstract: A photosensor package includes a substrate assembly, a photosensor chip mounted at the substrate assembly, a solder ball to electrically connect the photosensor chip, the substrate assembly and a printed circuit board, and a passive device mounted at the substrate assembly. Since the passive device is disposed on the substrate assembly of the photosensor package, it is possible to reduce the size of the printed circuit board compared to the convention technology where the passive device is disposed on the print circuit board. Furthermore, since it is possible to reduce a distance between the photosensor chip and the passive device, the electrical properties are also improved, and the number of processes may be reduced.Type: ApplicationFiled: May 13, 2010Publication date: November 18, 2010Applicant: OPTOPAC CO., LTD.Inventors: Jeong Seok RA, Jin Kwan KIM, Hui Tae KIM, Gi Tae LIM
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Publication number: 20100282291Abstract: A thin film photoelectric converter including a transparent conductive layer, a laser light absorption layer, a back electrode layer, a semiconductor photoelectric conversion layer and a transparent electrode layer stacked on a translucent substrate. The laser light absorption layer is parted into regions by first kind parting line grooves, and the photoelectric conversion layer is parted into regions by third kind parting line grooves penetrating the laser light absorption layer, the rear surface electrode layer and the photoelectric conversion layer. The transparent electrode layer is parted into regions by fourth kind parting line grooves penetrating the laser light absorption layer, the rear surface electrode layer, the photoelectric conversion layer and the transparent electrode layer. A receiving side transparent electrode region of one cell is electrically connected to a back electrode region of adjacent cell through the first kind groove, the transparent conductive layer and the third kind groove.Type: ApplicationFiled: December 5, 2008Publication date: November 11, 2010Applicant: KANEKA CORPORATIONInventors: Masahiro Goto, Wataru Yoshida, Toshiaki Sasaki
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Publication number: 20100282947Abstract: A semiconductor device is manufactured through steps in which a photoelectric conversion element and an amplifier circuit are formed over a first substrate with a release layer interposed therebetween, and the photoelectric conversion element and the amplifier circuit are separated from the first substrate. Output characteristics of the amplifier circuit are improved and the semiconductor device with high reliability is obtained.Type: ApplicationFiled: July 14, 2010Publication date: November 11, 2010Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.Inventors: Shunpei Yamazaki, Atsushi Hirose, Koji Ono, Hotaka Maruyama