Coatings (epo) Patents (Class 257/E31.119)
  • Publication number: 20080173903
    Abstract: A solid-state image pickup element equipped with a film stack, a color filter, and a microlens on a semiconductor substrate equipped with a light receiving section, comprises a first film with a high refractive index and a second film with a low refractive index adjacently arranged on the semiconductor substrate in this order viewing from the semiconductor substrate side, each of which has at least one layer respectively. Thereby it makes possible to reduce the loss of incident light, and to achieve the enhancement in photoelectric conversion efficiency.
    Type: Application
    Filed: December 28, 2007
    Publication date: July 24, 2008
    Applicant: FUJIFILM Corporation
    Inventors: Fumikazu Imai, Akihiro Anzai
  • Publication number: 20080176354
    Abstract: An electric device has a p-n diode, where the p-n diode is covered with a current modified layer (CML). With a resistance distribution of the CML, a current is decreased toward all directions from a point on a bonding pad between the CML and the p-n diode. Hence, a current is uniformly distributed on the CML by fine tuning the resistance distribution. Thus, an effectiveness of the electric device is improved.
    Type: Application
    Filed: April 23, 2007
    Publication date: July 24, 2008
    Applicant: National Central University
    Inventors: Cheng-yi Liu, Te-Yuan Chung, Pen-ko Chou, Ching-Liang Lin
  • Publication number: 20080169524
    Abstract: A method for forming an image sensor is provided. The method includes providing a semiconductor substrate having a pixel region and a peripheral circuit region, forming a photoelectric transformation section at the semiconductor substrate of the pixel region, forming a plurality of interlayer dielectrics over the semiconductor substrate with interconnections interposed therebetween, forming a passivation layer, partially patterning the passivation layer at the peripheral circuit region to form a via hole exposing the interconnection and removing the passivation layer and the underlying interlayer dielectric at the pixel region. The method further includes forming a conductive layer to fill the via hole and etching the conductive layer to remove the conductive layer at the pixel region and form a via plug and a conductive pad at the peripheral circuit region. The via plug fills the via hole and the conductive pad protrudes outwardly from the via hole.
    Type: Application
    Filed: March 13, 2008
    Publication date: July 17, 2008
    Inventor: KI-HONG KIM
  • Publication number: 20080157144
    Abstract: A method of fabricating a CMOS image sensor comprising forming an epitaxial layer on a semiconductor substrate, the epitaxial layer comprising a pixel and logic area, forming an STI layer in an insulating layer on the epitaxial layer, forming a plurality of wells and a gate pattern having a spacer on the insulating layer, forming a plurality of source and drain regions in the insulating layer using ion implantation, forming a salicide blocking layer on the insulating layer and gate pattern in the pixel area, forming a plurality of silicide layers in the logic area by performing a silicidation process, sequentially forming a PMD liner nitride layer and a PSG (phosphosilicate glass) layer on the salicide blocking layer in the pixel area and the insulating layer and gate pattern in the logic area, and forming a plurality of contacts connecting the PSG layer to the source and drain regions.
    Type: Application
    Filed: November 30, 2007
    Publication date: July 3, 2008
    Applicant: DONGBU HITEK CO., LTD.
    Inventor: Sang Gi LEE
  • Publication number: 20080157143
    Abstract: A CMOS image sensor comprising an epitaxial layer formed on a semiconductor layer, a device isolating layer formed on the epitaxial layer in order to divide the isolating layer into an active region and a device isolating region, the active region including a photo diode region and a transistor region, a drive transistor including a gate electrode formed on the epitaxial layer and a gate spacer formed on both side walls of the gate electrode, a floating diffusion region formed on the epitaxial layer, a trench hole formed in the device isolating layer and epitaxial layer in an area between the photo diode region and the floating diffusion region, a poly wiring formed in the trench hole which extends from the gate electrode to the drive transistor, and an impurity diffusion region formed by ion implanting the epitaxial layer on the side of the gate spacer.
    Type: Application
    Filed: November 30, 2007
    Publication date: July 3, 2008
    Applicant: DONGBU HITEK CO., LTD.
    Inventor: Keun Hyuk LIM
  • Patent number: 7384880
    Abstract: A method for making a semiconductor device is described. That method comprises converting a hydrophobic surface of a substrate into a hydrophilic surface, and forming a high-k gate dielectric layer on the hydrophilic surface.
    Type: Grant
    Filed: October 12, 2004
    Date of Patent: June 10, 2008
    Assignee: Intel Corporation
    Inventors: Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Suman Datta, Robert S. Chau
  • Publication number: 20070284685
    Abstract: The present invention relates to a semiconductor photodetector and the like that can be made adequately compact while maintaining mechanical strength. The semiconductor photodetector includes a structural body of layers and a glass substrate. The structural body of layers is arranged from an antireflection film, a high-concentration carrier layer of an n-type (first conductive type), a light absorbing layer of the n-type, and a cap layer of the n-type that are laminated successively. The glass substrate is adhered via a silicon oxide film onto the antireflection film side of the structural body of layers. The glass substrate is optically transparent to incident light.
    Type: Application
    Filed: November 30, 2004
    Publication date: December 13, 2007
    Applicant: Hamamatsu Photonics K.K.
    Inventor: Akimasa Tanaka
  • Publication number: 20070241416
    Abstract: A method of manufacturing a solid-state image pickup device comprises a process for forming a plurality of photoelectric conversion elements PD within a semiconductor substrate 4, a process for forming an interconnection portion, having an interconnection layer 8 in an insulating layer 7, on the surface side of the semiconductor substrate 4, a process for forming an adhesive layer, made of a material cured at a temperature lower than a deterioration starting temperature of the interconnection layer 8, on the surface of the interconnection portion and bonding a supporting substrate 30 to the surface side of the interconnection portion through the adhesive layer 9 by heat treatment at a temperature lower than the deterioration starting temperature of the interconnection layer 8 and a process for decreasing a thickness of the semiconductor substrate 4 from the back side.
    Type: Application
    Filed: June 11, 2007
    Publication date: October 18, 2007
    Applicant: Sony Corporation
    Inventor: Masafumi Muramatsu
  • Patent number: 7187019
    Abstract: Disclosed is a solid state image pickup device including a Si substrate, a conductive pattern such as transfer-accumulation electrodes and a buffer wiring formed above the Si substrate, an insulating film provided above the Si substrate in the state of covering the conductive pattern, and a shunt wiring composed of a metallic pattern formed above the insulating film in the state of being connected to the buffer wiring via a contact window formed in the insulating film. The portion of the shunt wiring in the vicinity of the bottom surface of the contact window contains at least one of silicon metal oxide or silicon metal nitride.
    Type: Grant
    Filed: July 11, 2005
    Date of Patent: March 6, 2007
    Assignee: Sony Corporation
    Inventor: Yasushi Maruyama
  • Publication number: 20060214251
    Abstract: A method of forming efficient photodiodes includes the steps of providing a substrate having a p-surface region on at least a portion thereof, implanting a shallow n-type surface layer into the surface region, and forming a multilayer first anti-reflective (AR) coating on the n-type surface layer. The surface layer is preferably an As or Sb surface layer. The forming the AR step include the steps of depositing or forming a thin oxide layer having a thickness of between 1.5 nm and 8 nm on the shallow surface layer, and depositing a second dielectric different from the thin oxide layer on the thin oxide layer, such as a silicon nitride layer.
    Type: Application
    Filed: March 17, 2006
    Publication date: September 28, 2006
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Perumal Ratnam, Dong Zheng
  • Patent number: 7078354
    Abstract: After a first gate oxide film (302) is formed on a substrate (301), a nitride layer (303) is formed by a first oxynitriding process. The first gate oxide film is selectively removed from a thinner film part area of the substrate. A second gate oxide film forming process forms a second gate oxide film (305A) in the thinner film part area and a third gate oxide film (305B) in a thicker film part area. By executing second oxynitriding process, nitride layers (306A and 306B) are formed at the thinner and the thicker part areas.
    Type: Grant
    Filed: May 12, 2004
    Date of Patent: July 18, 2006
    Assignee: Elpida Memory, Inc.
    Inventor: Takayuki Kanda