Multiple Quantum Well Structure (epo) Patents (Class 257/E33.008)
  • Patent number: 8735927
    Abstract: The invention provides a Group III nitride semiconductor light-emitting device which has a light extraction face at the n-layer side and which provides high light emission efficiency. The light-emitting device is produced through the laser lift-off technique. The surface of the n-GaN layer of the light-emitting device is roughened. On the n-GaN layer, a transparent film is formed. The transparent film satisfies the following relationship: 0.28?n×d1×2/??0.42 or 0.63?n×d1×2/??0.77, wherein n represents the refractive index of the transparent film, d1 represents the thickness of the transparent film in the direction orthogonal to an inclined face thereof, and ? represents the wavelength of the light emitted from the MQW layer.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: May 27, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventors: Yuhei Ikemoto, Naoki Arazoe
  • Patent number: 8729579
    Abstract: An illuminating device includes at least first and second nitride-based semiconductor light-emitting elements each having a semiconductor chip with an active layer region. The active layer region is at an angle of 1° or more with an m plane, and an angle formed by a normal line of a principal surface in the active layer region and a normal line of the m plane is 1° or more and 5° or less. The first and second nitride-based semiconductor light-emitting elements have thicknesses of d1 and d2, respectively, and emit the polarized light having wavelengths ?1 and ?2, respectively, where the inequalities of ?1<?2 and d1<d2 are satisfied.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: May 20, 2014
    Assignee: Panasonic Corporation
    Inventors: Toshiya Yokogawa, Akira Inoue, Masaki Fujikane, Mitsuaki Oya, Atsushi Yamada, Tadashi Yano
  • Patent number: 8723160
    Abstract: A light emitting diode (LED) die includes a first-type semiconductor layer, a multiple quantum well (MQW) layer and a second-type semiconductor layer. The light emitting diode (LED) die also includes a peripheral electrode on the first-type semiconductor layer located proximate to an outer periphery of the first-type semiconductor layer configured to spread current across the first-type semiconductor layer. A method for fabricating the light emitting diode (LED) die includes the step of forming an electrode on the outer periphery of the first-type semiconductor layer at least partially enclosing and spaced from the multiple quantum well (MQW) layer configured to spread current across the first-type semiconductor layer.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: May 13, 2014
    Assignee: SemiLEDS Optoelectronics Co., Ltd.
    Inventors: Chen-Fu Chu, Feng-Hsu Fan, Hao-Chun Cheng, Trung Tri Doan
  • Patent number: 8723159
    Abstract: A method for reducing dislocations or other defects in a light emitting device, such as light emitting diode (LED), by in-situ introducing nanoparticles into at least one of a defect-controlling layer, an n-type layer, a p-type layer, and a quantum well of the light emitting device. A light emitting device is provided, and nanoparticles are dispensed in-situ in at least one of a defect-controlling layer, an n-type layer, a p-type layer, and a quantum well of the light emitting device.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: May 13, 2014
    Assignee: InvenLux Corporation
    Inventors: Jianping Zhang, Hongmei Wang, Chunhui Yan
  • Publication number: 20140117306
    Abstract: A light-emitting device comprises a first type semiconductor layer, a multi-quantum well structure on the first type semiconductor layer, and a second type semiconductor layer on the multi-quantum well structure, wherein the multi-quantum well structure comprises a first portion near the first type semiconductor layer, a second portion near the second type semiconductor layer, and a strain releasing layer between the first portion and the second portion and comprising a first layer including Indium, a second layer including Aluminum on the first layer, and a third layer including Indium on the second layer, wherein the Indium concentration of the third layer is higher than that of the first layer.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 1, 2014
    Applicant: EPISTAR CORPORATION
    Inventors: YU-YAO LIN, Yen-Chih Chen, Chien-Yuan Tseng, Tsun-Kai Ko, Chun-Ta Yu, Shih-Chun Ling, Cheng-Hsiung Yen, Hsin-Hsien Wu
  • Patent number: 8709839
    Abstract: There is provided a method of fabricating a semiconductor light emitting device, including: forming a sacrificial layer having a plurality of nanostructures on a growth substrate; forming a protective layer to cover the sacrificial layer; forming a light emitting structure by allowing a first conductive semiconductor layer, an active layer and a second conductive semiconductor layer to be sequentially grown on the protective layer; etching the protective layer to expose the nanostructures; and separating the light emitting structure from the growth substrate by etching the exposed nanostructures, whereby damage and degradation of a light emitting structure at the time of the separation thereof may be prevented.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jong Hyun Lee, Dong Ju Lee, Young Sun Kim
  • Publication number: 20140103290
    Abstract: A light-emitting device comprises a first semiconductor layer; a second semiconductor layer; a light-emitting layer formed between the first semiconductor layer and the second semiconductor layer; a first electron blocking layer formed between the first semiconductor layer and the light-emitting layer; and a second electron blocking layer formed between the second semiconductor layer and the light-emitting layer, wherein the thickness of the second electron blocking layer is not equal to that of the first electron blocking layer, and/or the band gap energy of the second electron blocking layer is not equal to that of the first electron blocking layer.
    Type: Application
    Filed: October 16, 2012
    Publication date: April 17, 2014
    Applicant: Epistar Corporation
    Inventors: Sheng-Horng YEN, Ta-Cheng Hsu, Yu-Jiun Shen
  • Patent number: 8698123
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting part. The n-type semiconductor layer includes a nitride semiconductor. The p-type semiconductor layer includes a nitride semiconductor. The light emitting part is provided between the n-type and the p-type semiconductor layers and includes an n-side barrier layer and a first light emitting layer. The first light emitting layer includes a first barrier layer, a first well layer, and a first AlGaN layer. The first barrier layer is provided between the n-side barrier layer and the p-type semiconductor layer. The first well layer contacts the n-side barrier layer between the n-side and the first barrier layer. The first AlGaN layer is provided between the first well layer and the first barrier layer. A peak wavelength ?p of light emitted from the light emitting part is longer than 515 nanometers.
    Type: Grant
    Filed: August 19, 2011
    Date of Patent: April 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonari Shioda, Hisashi Yoshida, Naoharu Sugiyama, Shinya Nunoue
  • Patent number: 8698126
    Abstract: In the nitride semiconductor device of the present invention, an active layer 12 is sandwiched between a p-type nitride semiconductor layer 11 and an n-type nitride semiconductor layer 13. The active layer 12 has, at least, a barrier layer 2a having an n-type impurity, a well layer 1a made of a nitride semiconductor that includes In; and a barrier layer 2c that has a p-type impurity, or that has been grown without being doped. An appropriate injection of carriers into the active layer 12 becomes possible by arranging the barrier layer 2c nearest to the p-type layer side.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: April 15, 2014
    Assignee: Nichia Corporation
    Inventor: Tokuya Kozaki
  • Patent number: 8698192
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, a light emitting part, and a p-side electrode. The light emitting part is provided between the n-type and the p-type semiconductor layers, and includes a plurality of barrier layers and a plurality of well layers. The p-side electrode contacts the p-type semiconductor layer. The p-type semiconductor layer includes first, second, third, and fourth p-type layers. The first p-type layer contacts the p-side electrode. The second p-type layer contacts the light emitting part. The third p-type layer is provided between the first p-type layer and the second p-type layer. The fourth p-type layer is provided between the second p-type layer and the third p-type layer. The second p-type layer contains Al and contains a p-type impurity in a lower concentration lower than that in the first concentration.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: April 15, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Hajime Nago, Toshiki Hikosaka, Shigeya Kimura, Shinya Nunoue
  • Patent number: 8692228
    Abstract: A semiconductor light emitting device includes a first layer including at least one of n-type GaN and n-type AlGaN; a second layer including Mg-containing p-type AlGaN; and a light emitting section provided between the first and second layers. The light emitting section includes barrier layers of Si-containing AlxGa1-x-yInyN (0?x, 0?y, x+y?1), and a well layer provided between the barrier layers and made of GaInN or AlGaInN. The barrier layers have a nearest barrier layer nearest to the second layer among the barrier layers and a far barrier layer. The nearest barrier layer includes a first portion made of Si-containing AlxGa1-x-yInyN (0?x, 0?y, x+y?1), and a second portion provided between the first portion and the second layer and made of AlxGa1-x-yInyN (0?x, 0?y, x+y?1). The Si concentration in the second portion is lower than those in the first portion and in the far barrier layer.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: April 8, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kei Kaneko, Yasuo Ohba, Hiroshi Katsuno, Mitsuhiro Kushibe
  • Patent number: 8692287
    Abstract: According to one embodiment, a nitride semiconductor device includes: a stacked foundation layer, and a functional layer. The stacked foundation layer is formed on an AlN buffer layer formed on a silicon substrate. The stacked foundation layer includes AlN foundation layers and GaN foundation layers being alternately stacked. The functional layer includes a low-concentration part, and a high-concentration part provided on the low-concentration part. A substrate-side GaN foundation layer closest to the silicon substrate among the plurality of GaN foundation layers includes first and second portions, and a third portion provided between the first and second portions. The third portion has a Si concentration not less than 5×1018 cm?3 and has a thickness smaller than a sum of those of the first and second portions.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: April 8, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tomonari Shioda, Hung Hung, Jongil Hwang, Taisuke Sato, Naoharu Sugiyama, Shinya Nunoue
  • Patent number: 8686395
    Abstract: A bond type flip-chip light-emitting structure and method of manufacturing the same. Firstly, form a positive electrode and a negative electrode on an epitaxy layer. Next, deposit an insulation layer on parts of the positive electrode and negative electrode, to expose respectively a positive electrode via hole and a negative electrode via hole. Then, form a bonded metal layer on the insulation layer, the positive electrode via hole, and the negative electrode via hole, so that the positive electrode and the negative electrode are on a same plane by means of the bonded metal layer. Finally, on a substrate, bond the first metal layer and the second metal layer onto the corresponding first bonded metal unit and the second bonded metal unit of the bonded metal layer, to form into shape, thus realizing a bond type flip-chip light-emitting structure.
    Type: Grant
    Filed: February 25, 2013
    Date of Patent: April 1, 2014
    Assignee: Chang Gung University
    Inventors: Liann-Be Chang, Chen Xu, Kun Xu, Yunyun Zhang, How-Wen Chien
  • Patent number: 8685783
    Abstract: On a first structure having a first dielectric layer, a second dielectric layer, and a third dielectric layer a crown is formed through the third dielectric layer and the second dielectric layer. A fourth dielectric layer is deposited over the first structure and thereby is over the crown. A portion of the fourth dielectric layer is removed to form a first spacer having a remaining portion of the fourth dielectric layer. A portion of the third electric layer is also removed during the removal of the portion the fourth dielectric layer, resulting in a second spacer having a remaining portion of the third dielectric layer. A second structure is thereby formed. A phase change material layer is deposited over the second structure. An electrode layer is deposited over the phase change layer.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: April 1, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Huei Shen, Tsun Kai Tsao, Shih-Chang Liu, Chia-Shiung Tsai
  • Patent number: 8686397
    Abstract: A light emitting diode structure of (Al,Ga,In)N thin films grown on a gallium nitride (GaN) semipolar substrate by metal organic chemical vapor deposition (MOCVD) that exhibits reduced droop. The device structure includes a quantum well (QW) active region of two or more periods, n-type superlattice layers (n-SLs) located below the QW active region, and p-type superlattice layers (p-SLs) above the QW active region. The present invention also encompasses a method of fabricating such a device.
    Type: Grant
    Filed: June 11, 2012
    Date of Patent: April 1, 2014
    Assignee: The Regents of the University of California
    Inventors: Shuji Nakamura, Steven P. DenBaars, Shinichi Tanaka, Daniel F. Feezell, Yuji Zhao, Chih-Chien Pan
  • Patent number: 8679880
    Abstract: An electron transporting surfactant is added to a raw material solution such that the electron transporting surfactant is coordinated on the surfaces of quantum dots, and after the dispersion solvent is evaporated by vacuum drying, the immersion in a solvent containing a hole transporting surfactant prepares a quantum dot dispersed solution with a portion of the electron transporting surfactant replaced with the hole transporting surfactant. The quantum dot dispersed solution is applied onto a substrate to prepare a hole transport layer and a quantum dot layer at the same time, and thereby to achieve a thin film which has a two-layer structure.
    Type: Grant
    Filed: June 15, 2012
    Date of Patent: March 25, 2014
    Assignee: Murata Manufaaturing Co., Ltd.
    Inventor: Koji Murayama
  • Patent number: 8680508
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type layer, a p-type layer, and a light emitting unit provided between the n-type layer and the p-type layer and including barrier layers and well layers. At least one of the barrier layers includes first and second portion layers. The first portion layer is disposed on a side of the n-type layer. The second portion layer is disposed on a side of the p-type layer, and contains n-type impurity with a concentration higher than that in the first portion layer. At least one of the well layers includes third and fourth portion layers. The third portion layer is disposed on a side of the n-type layer. The fourth portion layer is disposed on a side of the p-type layer, and contains n-type impurity with a concentration higher than that in the third portion layer.
    Type: Grant
    Filed: August 31, 2011
    Date of Patent: March 25, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Toshiki Hikosaka, Koichi Tachibana, Hajime Nago, Shinya Nunoue
  • Patent number: 8680509
    Abstract: A nitride semiconductor device is provided, in which a superlattice strain buffer layer using AlGaN layers having a low Al content or GaN layers is formed with good flatness, and a nitride semiconductor layer with good flatness and crystallinity is formed on the superlattice strain buffer layer. A nitride semiconductor device includes a substrate; an AlN strain buffer layer made of AlN formed on the substrate; a superlattice strain buffer layer formed on the AlN strain buffer layer; and a nitride semiconductor layer formed on the superlattice strain buffer layer, and is characterized in that the superlattice strain buffer layer has a superlattice structure formed by alternately stacking first layers made of AlxGa1-xN (0?x?0.25), which further contain p-type impurity, and second layers made of AlN.
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: March 25, 2014
    Assignee: Dowa Electronics Materials Co., Ltd.
    Inventors: Yoshikazu Ooshika, Tetsuya Matsuura
  • Patent number: 8680514
    Abstract: An electric energy generator may include a semiconductor layer and a plurality of nanowires having piezoelectric characteristics. The electric energy generator may convert optical energy into electric energy if external light is applied and may generate piezoelectric energy if external pressure (e.g., sound or vibration) is applied.
    Type: Grant
    Filed: October 27, 2010
    Date of Patent: March 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-jun Park, Seung-nam Cha
  • Patent number: 8674375
    Abstract: A light emitting diode (LED) includes a p-type layer of material, an n-type layer of material and an active layer between the p-type layer and the n-type layer. A roughened layer of transparent material is adjacent one of the p-type layer of material and the n-type layer of material. The roughened layer of transparent material has a refractive index close to or substantially the same as the refractive index of the material adjacent the layer of transparent material, and may be a transparent oxide material or a transparent conducting material. An additional layer of conductive material may be between the roughened layer and the n-type or p-type layer.
    Type: Grant
    Filed: July 21, 2005
    Date of Patent: March 18, 2014
    Assignee: Cree, Inc.
    Inventors: Steven P. Denbaars, James Ibbetson, Shuji Nakamura
  • Patent number: 8674338
    Abstract: According to one embodiment, a semiconductor light emitting device includes an n-type semiconductor layer, a p-type semiconductor layer, and a light emitting portion. The light emitting portion is provided between the semiconductor layers and includes barrier layers and well layers alternately stacked. An n-side end well layer which is closest to the n-type semiconductor layer contains InwnGa1-wnN and has a layer thickness twn. An n-side end barrier layer which is closest to the n-type semiconductor layer contains InbnGa1-bnN and has a layer thickness tbn. A p-side end well layer which is closest to the p-type semiconductor layer contains InwpGa1-wpN and has a layer thickness twp. A p-side end barrier layer which is closest to the p-type semiconductor contains InbpGa1-bpN and has a layer thickness tbp. A value of (wp×twp+bp×tbp)/(twp+tbp) is higher than (wn×twn+bn×tbn)/(twn+tbn) and is not higher than 5 times (wn×twn+bn×tbn)/(twn+tbn).
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: March 18, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koichi Tachibana, Toshiki Hikosaka, Shigeya Kimura, Hajime Nago, Shinya Nunoue
  • Patent number: 8669546
    Abstract: A nitride group semiconductor light emitting device includes a substrate, n-type and p-type semiconductor layers, and an active region. The n-type and p-type semiconductor layers are formed on or above the substrate. The active region is interposed between the n-type and p-type semiconductor layers. The active region includes barrier layers that are included in a multiquantum well structure, and an end barrier layer that has a thickness greater than the barrier layer, and is arranged closest to the p-type semiconductor layer. The average thickness of the last two barrier layers that are arranged adjacent to the end barrier layer is smaller than the average thickness of the other barrier layers among the thicknesses of the barrier layers that are included in the multiquantum well structure.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: March 11, 2014
    Assignee: Nichia Corporation
    Inventor: Yasuhisa Kotani
  • Patent number: 8669545
    Abstract: A light emitting device includes an active layer including a quantum barrier and a quantum well, a first conductive type semiconductor layer disposed at one side of the active layer, and a second conductive type semiconductor layer disposed at the other side of the active layer, wherein the first conductive type semiconductor layer or the second conductive type semiconductor layer includes a main barrier layer, and the main barrier layer includes a plurality of sub barrier layers and a basal layer disposed between the plurality of sub barrier layers. The plurality of sub barrier layers includes a first section in which energy band gaps of the plurality of sub barrier layers are increased and a second section in which energy band gaps of the plurality of sub barrier layers are decreased.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: March 11, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Yong Seon Song, Yong Tae Moon
  • Patent number: 8664637
    Abstract: Disclosed herein is a quantum dot phosphor for light emitting diodes, which includes quantum dots and a solid substrate on which the quantum dots are supported. Also, a method of preparing the quantum dot phosphor is provided. Since the quantum dot phosphor of the current invention is composed of the quantum dots supported on the solid substrate, the quantum dots do not aggregate when dispensing a paste obtained by mixing the quantum dots with a paste resin for use in packaging of a light emitting diode. Thereby, a light emitting diode able to maintain excellent light emitting efficiency can be manufactured.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: March 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eun Joo Jang, Mi Yang Kim, Hyung Kun Kim, Shin Ae Jun, Yong Wan Jin, Seong Jae Choi
  • Patent number: 8664636
    Abstract: A nanostructured device according to the invention comprises a first group of nanowires protruding from a substrate where each nanowire of the first group of nanowires comprises at least one pn- or p-i-n-junction. A first contact, at least partially encloses and is electrically connected to a first side of the pn- or p-i-n-junction of each nanowire in the first group of nanowires. A second contacting means comprises a second group of nanowires that protrudes from the substrate, and is arranged to provide an electrical connection to a second side of the pn- or p-i-n-junction.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: March 4, 2014
    Assignee: GLO AB
    Inventors: Steven Louis Konsek, Yourii Martynov, Jonas Ohlsson, Peter Jesper Hanberg
  • Patent number: 8664681
    Abstract: Parallel plate slot emission array. In accordance with an embodiment of the present invention, an article of manufacture includes a side-emitting light emitting diode configured to emit light from more than two surfaces. The article of manufacture includes a first sheet electrically and thermally coupled to a first side of the light emitting diode, and a second sheet electrically and thermally coupled to a second side of the light emitting diode. The article of manufacture further includes a plurality of reflective surfaces configured to reflect light from all of the surfaces of the light emitting diode through holes in the first sheet. The light may be reflected via total internal reflection.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: March 4, 2014
    Assignee: Invensas Corporation
    Inventors: Ilyas Mohammed, Liang Wang, Steven D. Gottke
  • Patent number: 8658440
    Abstract: A nitride semiconductor light emitting device is formed by: forming a resist pattern on a first nitride semiconductor layer formed on a substrate, the resist pattern having a region whose inclination angle relative to a substrate surface changes smoothly as viewed in a cross section perpendicular to the substrate surface; etching the substrate by using the resist pattern as a mask to transfer the resist pattern to the first nitride semiconductor layer; and forming an light emitting layer on the patterned first nitride semiconductor layer. The nitride semiconductor light emitting device can emit near-white light or have a wavelength range generally equivalent to or near visible light range.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: February 25, 2014
    Assignee: Stanley Electric Co., Ltd.
    Inventors: Ji-Hao Liang, Masahiko Tsuchiya, Takako Chinone, Masataka Kajikawa
  • Patent number: 8659005
    Abstract: A light emitting device comprising a staggered composition quantum well (QW) has a step-function-like profile in the QW, which provides higher radiative efficiency and optical gain by providing improved electron-hole wavefunction overlap. The staggered QW includes adjacent layers having distinctly different compositions. The staggered QW has adjacent layers Xn wherein X is a quantum well component and in one quantum well layer n is a material composition selected for emission at a first target light regime, and in at least one other quantum well layer n is a distinctly different composition for emission at a different target light regime. X may be an In-content layer and the multiple Xn-containing a step function In-content profile.
    Type: Grant
    Filed: December 24, 2007
    Date of Patent: February 25, 2014
    Assignee: Lehigh University
    Inventors: Nelson Tansu, Ronald A. Arif, Yik Khoon Ee, Hongping Zhao
  • Publication number: 20140048766
    Abstract: A method for fabricating light emitting diode (LED) dice includes the step of forming a light emitting diode (LED) die having a multiple quantum well (MQW) layer configured to emit electromagnetic radiation, and a confinement layer on the multiple quantum well (MQW) layer having a wire bond pad. The method also includes the steps of forming a dam on the wire bond pad configured to protect a wire bond area on the wire bond pad, forming an adhesive layer on the confinement layer and the wire bond pad with the dam protecting the wire bond area, and forming a wavelength conversion layer on the adhesive layer. A light emitting diode (LED) die includes the dam on the wire bond pad, the adhesive layer on the confinement layer and the wavelength conversion layer on the adhesive layer configured to convert the electromagnetic radiation to a second spectral region.
    Type: Application
    Filed: August 15, 2012
    Publication date: February 20, 2014
    Applicant: SemiLEDS Optoelectronics Co., Ltd.
    Inventors: Chen-Fu CHU, Feng-Hsu FAN
  • Patent number: 8653499
    Abstract: A light-emitting diode (LED) includes a first conductivity type semiconductor layer, a strain-relaxed layer over the first conductivity type semiconductor layer, an active layer over the strain-relaxed layer, and a second conductivity type semiconductor layer over the active layer. The strain-relaxed layer includes a strain-absorbed layer over the first conductivity type semiconductor layer and a surface-smoothing layer on the strain-absorbed layer filling the cavities. The strain-absorbed layer includes a plurality of cavities in a substantial hexagonal-pyramid form.
    Type: Grant
    Filed: June 6, 2011
    Date of Patent: February 18, 2014
    Assignee: Epistar Corporation
    Inventor: Shih-Chang Lee
  • Patent number: 8653498
    Abstract: According to one embodiment, a semiconductor light emitting device includes: a stacked structural body, a first electrode; and a second electrode. The stacked structural body includes a first semiconductor layer of n-type, a second semiconductor layer of p-type, and a light emitting portion provided therebetween. The first electrode includes a first contact electrode portion. The second electrode includes a second contact electrode portion and a p-side pad electrode. A sheet resistance of the second contact electrode portion is lower than a sheet resistance of the first semiconductor layer. The p-side pad electrode is provided farther inward than a circumscribed rectangle of the first contact electrode portion, and the first contact electrode portion is provided farther outward than a circumscribed rectangle of the p-side pad electrode.
    Type: Grant
    Filed: February 23, 2011
    Date of Patent: February 18, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shigeya Kimura, Taisuke Sato, Toshihide Ito, Takahiro Sato, Toshiyuki Oka, Shinya Nunoue
  • Patent number: 8653501
    Abstract: Provided is an emitting device which is capable of improving the luminous efficiency of an emitting layer formed using a group IV semiconductor material and obtaining an emission spectrum having a narrow band, and a manufacturing method therefor. The emitting device comprises: an emitting layer having a potential confinement structure, comprising: a well region comprising a group IV semiconductor material; and a barrier region being adjacent to the well region and comprising a group IV semiconductor material which is different from the group IV semiconductor material in the well region, wherein: a continuous region from the well region over an interface between the well region and the barrier region to a part of the barrier region comprises fine crystals; and a region in the barrier region, which is other than the continuous region comprising the fine crystals, is amorphous or polycrystalline region.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: February 18, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Tetsuya Takeuchi, Tatsuro Uchida, Mitsuhiro Ikuta
  • Patent number: 8653549
    Abstract: Provided are a phosphor, a phosphor manufacturing method, and a white light emitting device. The phosphor is represented as a chemical formula of aMO-bAlN-cSi3N4, which uses light having a peak wavelength in a wavelength band of about 350 nm to about 480 nm as an excitation source to emit visible light having a peak wavelength in a wavelength band of about 480 nm to about 680 nm. (where M is one selected from alkaline earth metals (0.2?a/(a+b)?0.9, 0.05?b(b+c)?0.85, 0.4?c/(c+a)?0.9)).
    Type: Grant
    Filed: September 2, 2010
    Date of Patent: February 18, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventors: Jae Soo Yoo, Kyung Pil Kim, Hyun Ju Lee, Chang Soo Kim
  • Publication number: 20140042387
    Abstract: A semiconductor light-emitting device and a manufacturing method thereof are provided, wherein the semiconductor light-emitting device includes a first type doped semiconductor structure, a light-emitting layer, a second type doped semiconductor layer, a first conductive layer and a dielectric layer. The first type doped semiconductor structure includes a base and a plurality of columns extending outward from the base. Each of the columns includes a top surface and a plurality of sidewall surfaces. The light-emitting layer is disposed on the sidewall surfaces and the top surface, wherein the surface area of the light-emitting layer gradually changes from one side adjacent to the columns to a side away from the columns. The dielectric layer exposes the first conductive layer locating on the top surface of each of the columns, wherein the dielectric layer includes at least one of a plurality of quantum dots, phosphors, and metal nanoparticles.
    Type: Application
    Filed: September 13, 2012
    Publication date: February 13, 2014
    Applicant: NATIONAL TAIWAN UNIVERSITY
    Inventors: Chih-Chung Yang, Che-Hao Liao, Shao-Ying Ting, Horng-Shyang Chen, Wen-Ming Chang, Yu-Feng Yao, Chih-Yen Chen, Hao-Tsung Chen
  • Patent number: 8648328
    Abstract: A method is provided for fabricating a light emitting diode (LED) using three-dimensional gallium nitride (GaN) pillar structures with planar surfaces. The method forms a plurality of GaN pillar structures, each with an n-doped GaN (n-GaN) pillar and planar sidewalls perpendicular to the c-plane, formed in either an m-plane or a-plane family. A multiple quantum well (MQW) layer is formed overlying the n-GaN pillar sidewalls, and a layer of p-doped GaN (p-GaN) is formed overlying the MQW layer. The plurality of GaN pillar structures are deposited on a first substrate, with the n-doped GaN pillar sidewalls aligned parallel to a top surface of the first substrate. A first end of each GaN pillar structure is connected to a first metal layer. The second end of each GaN pillar structure is etched to expose the n-GaN pillar second end and connected to a second metal layer.
    Type: Grant
    Filed: February 6, 2012
    Date of Patent: February 11, 2014
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Mark Albert Crowder, Changqing Zhan, Paul J. Schuele
  • Patent number: 8642993
    Abstract: A III-nitride film, grown on an m-plane substrate, includes multiple quantum wells (MQWs) with a barrier thickness of 27.5 nm or greater and a well thickness of 8 nm or greater. An emission wavelength can be controlled by selecting the barrier thickness of the MQWs. Device fabricated using the III-nitride film include nonpolar III-nitride light emitting diodes (LEDs) with a long wavelength emission.
    Type: Grant
    Filed: November 15, 2010
    Date of Patent: February 4, 2014
    Assignee: The Regents of the University of California
    Inventors: Hisashi Yamada, Kenji Iso, Shuji Nakamura
  • Patent number: 8642943
    Abstract: A light-receiving element includes an InP substrate 1, a light-receiving layer 3 having an MQW and located on the InP substrate 1, a contact layer 5 located on the light-receiving layer 3, a p-type region 6 extending from a surface of the contact layer 5 to the light-receiving layer, and a p-side electrode 11 that forms an ohmic contact with the p-type region. The light-receiving element is characterized in that the MQW has a laminated structure including pairs of an InxGa1-xAs (0.38?x?0.68) layer and a GaAs1-ySby (0.25?y?0.73) layer, and in the GaAs1-ySby layer, the Sb content y in a portion on the InP substrate side is larger than the Sb content y in a portion on the opposite side.
    Type: Grant
    Filed: December 3, 2010
    Date of Patent: February 4, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiroki Mori, Yasuhiro Iguchi, Hiroshi Inada, Youichi Nagai, Kouhei Miura, Hideaki Nakahata, Katsushi Akita, Takashi Ishizuka, Kei Fujii
  • Patent number: 8642992
    Abstract: A Group III nitride compound semiconductor light emitting device is provided which has: an n-type semiconductor layer (12); an active layer (13) of a multiple quantum well structure laminated on the n-type semiconductor layer (12); a first p-type semiconductor layer (14) that is a layer of a superlattice structure in which an undoped film (14a) that has a composition AlxGa1-xN (x indicating composition ratio, being within a range 0<x?0.4) and that contains no dopant, and a doped film (14b) that has a composition AlyGa1-yN (y indicating composition ratio, being within a range 0?y<0.4) and that contains a dopant, are alternately laminated a plurality of times, and a surface thereof on the active layer side (13) is constituted by the undoped film (14a); and a second p-type semiconductor layer (15) laminated on the first p-type semiconductor layer (14).
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: February 4, 2014
    Assignee: Toyoda Gosei Co., Ltd.
    Inventor: Hisayuki Miki
  • Publication number: 20140027709
    Abstract: A method and structure for receiving a micro device on a receiving substrate are disclosed. A micro device such as a micro LED device is punched-through a passivation layer covering a conductive layer on the receiving substrate, and the passivation layer is hardened. In an embodiment the micro LED device is punched-through a B-staged thermoset material. In an embodiment the micro LED device is punched-through a thermoplastic material.
    Type: Application
    Filed: July 30, 2012
    Publication date: January 30, 2014
    Inventors: John A. Higginson, Andreas Bibl, Hsin-Hua Hu
  • Patent number: 8633092
    Abstract: An apparatus includes a primary planar quantum well and a planar distribution of dopant atoms. The primary planar quantum well is formed by a lower barrier layer, a central well layer on the lower barrier layer, and an upper barrier layer on the central well layer. Each of the layers is a semiconductor layer. One of the barrier layers has a secondary planar quantum well and is located between the planar distribution of dopant atoms and the central well layer. The primary planar quantum well may be undoped or substantially undoped, e.g., intrinsic semiconductor.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: January 21, 2014
    Assignee: Alcatel Lucent
    Inventors: Kirk William Baldwin, Loren N. Pfeiffer, Kenneth William West
  • Patent number: 8629424
    Abstract: A light emitting diode including a substrate, a first semiconductor layer, an active layer, and a second semiconductor layer is provided. The first semiconductor layer includes a first surface and a second surface, and the first surface is connected to the substrate. The active layer and the second semiconductor layer are stacked on the second surface in that order, and a surface of the second semiconductor layer away from the active layer is configured as the light emitting surface. A first electrode electrically is connected with the first semiconductor layer. A second electrode is electrically connected with the second semiconductor layer. A number of three-dimensional nano-structures are located on the surface of the first surface of the first semiconductor layer and the light emitting surface, and a cross section of each of the three-dimensional nano-structures is M-shaped.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: January 14, 2014
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Zhen-Dong Zhu, Qun-Qing Li, Li-Hui Zhang, Mo Chen, Shou-Shan Fan
  • Patent number: 8629559
    Abstract: A stress reduction apparatus comprises a metal structure formed over a substrate, an inter metal dielectric layer formed over the substrate, wherein a lower portion of the metal structure is embedded in the inter metal dielectric layer and an inverted cup shaped stress reduction layer formed over the metal structure, wherein an upper portion of the metal structure is embedded in the inverted cup shaped stress reduction layer.
    Type: Grant
    Filed: February 9, 2012
    Date of Patent: January 14, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ying-Ti Lu, Wen-Tsao Chen, Ming-Ray Mao, Kuan-Chi Tsai
  • Patent number: 8629425
    Abstract: A light emitting diode and a method of fabricating a light emitting diode, the diode has a first set of multiple quantum wells (MQWs), each of the MQWs of the first set comprising a wetting layer providing nucleation sites for quantum dots (QDs) or QD-like structures in a well layer of said each MQW; and a second set of MQWs, each of the MQWs of the second set formed so as to exhibit a photoluminescence (PL) peak wavelength shifted compared to the MQWs of the first set.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: January 14, 2014
    Assignee: Agency for Science, Technology and Research
    Inventors: Chew Beng Soh, Soo Jin Chua, Haryono Hartono
  • Patent number: 8624221
    Abstract: A light emitting device is provided. The light emitting device comprises an active layer comprising a plurality of well layers and a plurality of barrier layers. The bather layers comprise a first barrier layer having a first band gap which is the nearest to the second conductive type semiconductor layer, a second barrier layer adjacent to the first barrier, and a third barrier layer between the second bather layer and the first conductive type semiconductor layer. The well layers comprise a first well layer having a third band gap different from the first band gap between the first and second bather layers, and a second well layer between the second barrier layer and the third barrier layer, the second well layer having a second band gap. The first well layer has a thickness thinner than that of the second well layer.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: January 7, 2014
    Assignee: LG Innotek Co., Ltd.
    Inventor: Jong Hak Won
  • Publication number: 20130335677
    Abstract: A display device is provided. The display device includes a light source emitting a blue light and a light emitting layer including a first group of red quantum dots and a second group of green quantum dots. The light emitting layer is configured to absorb a first portion of the blue light from the light source to emit red light and green light and to transmit a second portion of the blue light. The display device also includes a dichroic filter layer configured to reflect a portion of the transmitted second portion of the blue light such that the reflected portion of the blue light is recycled in the light emitting layer and to transmit a remaining portion of the transmitted second portion of the blue light to output a white light.
    Type: Application
    Filed: September 28, 2012
    Publication date: December 19, 2013
    Applicant: Apple Inc.
    Inventor: Chenhua You
  • Patent number: 8610105
    Abstract: Provided is a semiconductor electroluminescent device with an InGaAlAs-based well layer having tensile strain, or a semiconductor electroluminescent device with an InGaAsP-based well layer having tensile strain and with an InGaAlAs-based barrier layer which is high-performance and highly reliable in a wide temperature range. In a multiple-quantum well layer of the semiconductor electroluminescent device, a magnitude of interface strain at an interface between the well layer and the barrier layer is smaller than a magnitude of critical interface strain determined by a layer thickness value which is larger one of a thickness of the well layer and a thickness of the barrier layer.
    Type: Grant
    Filed: November 9, 2009
    Date of Patent: December 17, 2013
    Assignee: Oclaro Japan, Inc.
    Inventors: Toshihiko Fukamachi, Takashi Shiota, Takeshi Kitatani, Nozomu Yasuhara, Atsushi Nakamura, Mitsuhiro Sawada
  • Patent number: 8610107
    Abstract: A light emitting device is provided. The light emitting device comprises an active layer comprising a plurality of well layers and barrier layers. The barrier layers comprise a first barrier layer which is the nearest to a second conductive type semiconductor layer and has a first band gap, a second barrier layer having a third band gap, and a third barrier layer having the first band gap between the second barrier layer and a first conductive type semiconductor layer. The well layers comprise a first well layer having a second band gap between the first and the second barrier layers, and a second well layer between the second barrier layer and the third barrier layer. The second barrier layer is disposed between the first and the second well layers, and the third band gap is narrower than the first band gap and wider than the second band gap.
    Type: Grant
    Filed: February 1, 2012
    Date of Patent: December 17, 2013
    Assignee: LG Innotek Co., Ltd.
    Inventor: Jong Hak Won
  • Publication number: 20130320296
    Abstract: A light-emitting device comprises a semiconductor stacked structure, the semiconductor stacked structure comprising a p-type semiconductor layer, a n-type semiconductor layer and an multiple quantum well structure between the p-type semiconductor layer and the n-type semiconductor layer, wherein the multiple quantum well structure comprises a first multiple quantum well structure near the n-type semiconductor layer and a second multiple quantum well structure near the p-type semiconductor layer, wherein the first multiple quantum well structure has positive interface bound charge and the second multiple quantum well structure has zero interface bound charge.
    Type: Application
    Filed: June 5, 2012
    Publication date: December 5, 2013
    Applicant: Epistar Corporation
    Inventors: Chun-Ta Yu, Chien-Yuan Tseng, Yu-Yao Lin, Shih-Pang Chang, Hung-Chih Yang
  • Patent number: 8592800
    Abstract: A semiconductor emitter, or a precursor therefor, has a substrate and one or more textured semiconductor layers deposited onto the substrate in a nonpolar orientation. The textured layers enhance light extraction, and the use of nonpolar orientation greatly enhances internal quantum efficiency compared to conventional devices. Both the internal and external quantum efficiencies of emitters of the invention can be 70-80% or higher. The invention provides highly efficient light emitting diodes suitable for solid state lighting.
    Type: Grant
    Filed: March 9, 2009
    Date of Patent: November 26, 2013
    Assignee: Trustees of Boston University
    Inventors: Theodore D. Moustakas, Adam Moldawer, Anirban Bhattacharyya, Joshua Abell
  • Patent number: 8592802
    Abstract: A nitride light emitting diode, on a patterned substrate, comprising a nitride interlayer having at least two periods of alternating layers of InxGa1-xN and InyGa1-yN where 0<x<1 and 0?y<1, and a nitride based active region having at least one quantum well structure on the nitride interlayer.
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: November 26, 2013
    Assignee: The Regents of the University of California
    Inventors: Michael Iza, Hitoshi Sato, Eu Jin Hwang, Steven P. DenBaars, Shuji Nakamura