Abstract: A switching element according to the present invention includes an ion-conducting layer, first electrode 11 and second electrode 12 placed in contact with the ion-conducting layer, and third electrode 15 placed in contact with the ion-conducting layer and to control electrical conductivity between the first electrode and the second electrode, wherein the shortest distance between any two of first, second, and third electrodes 11, 12, and 13 is defined by the film thickness of the ion-conducting layer.

Abstract: A layer of phase change material with silicon or another semiconductor, or a silicon-based or other semiconductor-based additive, is formed using a composite sputter target including the silicon or other semiconductor, and the phase change material. The concentration of silicon or other semiconductor is more than five times greater than the specified concentration of silicon or other semiconductor in the layer being formed. For silicon-based additive in GST-type phase change materials, sputter target may comprise more than 40 at % silicon. Silicon-based or other semiconductor-based additives can be formed using the composite sputter target with a flow of reactive gases, such as oxygen or nitrogen, in the sputter chamber during the deposition.

Abstract: According to one embodiment, a nonvolatile memory device includes a memory section. The memory section includes a first insulating layer, a second insulating layer and a pair of electrodes. The second insulating layer is formed on and in contact with the first insulating layer. The second insulating layer has at least one of a composition different from a composition of the first insulating layer and a phase state different from a phase state of the first insulating layer. The pair of electrodes is capable of passing a current through a current path along a boundary portion between the first insulating layer and the second insulating layer. An electrical resistance of the current path is changed by a voltage applied between the pair of electrodes.

Abstract: A phase-change memory cell including, between two electrical contacts, a portion in a memory material with amorphous-crystalline phase-change and vice versa, as a stack with a central area located between two outmost areas. An interface, inert or quasi-inert from a physico-chemical point of view, is present between the active central area and each passive outmost area. Each passive outmost area is made in a material having a melting temperature higher than that of the material of the active central area.

Abstract: A nonvolatile memory element comprising: a first electrode 2; a second electrode 6 formed above the first electrode 2; a variable resistance film 4 formed between the first electrode 2 and the second electrode 6, a resistance value of the variable resistance film 4 being increased or decreased by an electric pulse applied between the first and second electrodes 2, 6; and an interlayer dielectric film 3 provided between the first and second electrodes 2, 6, wherein the interlayer dielectric film 3 is provided with an opening extending from a surface thereof to the first electrode 2; the variable resistance film 4 is formed at an inner wall face of the opening; and an interior region of the opening which is defined by the variable resistance film 4 is filled with an embedded insulating film 5.

Abstract: Chalcogenide containing semiconductor devices may be formed with a gradient film between a chalcogenide film and another film. The gradient film may have its chalcogenide concentration decrease as it extends away from the chalcogenide film, while the concentration of the other film material increases across the thickness of the gradient film moving away from the chalcogenide film.

Abstract: A phase change memory device having a bottleneck constriction and method of making same are presented. The phase change memory device includes a semiconductor substrate, a lower electrode, an interlayer film, an insulator, a phase change layer and an upper electrode. The interlayer film is formed on the semiconductor substrate having the lower electrode. The interlayer film includes a laminate of a first insulating film, a silicon film and a second insulating film with a hole formed therethrough. The insulator is disposed along the exposed surface of the silicon film around the inner circumference of the hole. The phase change layer is embedded within the hole having the insulator which constricts the shape of the phase change layer to a bottleneck constriction. A method of manufacturing the phase change memory device is also provided.

Abstract: A plurality of bit lines s arranged crossing a plurality of first word lines. A first diode is arranged at each cross point of the first word lines and the bit lines. A cathode of the first diode is connected to one of the first word lines. A first variable resistance film configuring the first diode is provided between the anodes of the first diodes and the bit lines, and configures a first memory cell together with each of the first diodes, and further, is used in common to the first diodes.

Abstract: A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.

Abstract: A phase-change memory is provided. The phase-change memory comprises a substrate. A first electrode is formed on the substrate. A circular or linear phase-change layer is electrically connected to the first electrode. A second electrode formed on the phase-change layer and electrically connected to the phase-change layer, wherein at least one of the first electrode and the second electrode comprises phase-change material.

Abstract: A phase change memory device includes a switching device, a phase change storage node connected to the switching device, and a gate electrode which is spaced apart from the phase change storage node and increases an electrical resistance of the storage node during a reset programming operation. The gate electrode may be disposed around the phase change storage node, and may be used for applying an electric field to the phase change storage node.

Abstract: A lateral phase change memory includes a pair of electrodes separated by an insulating layer. The first electrode is formed in an opening in an insulating layer and is cup-shaped. The first electrode is covered by the insulating layer which is, in turn, covered by the second electrode. As a result, the spacing between the electrodes may be very precisely controlled and limited to very small dimensions. The electrodes are advantageously formed of the same material, prior to formation of the phase change material region.

Abstract: An integrated circuit structure includes a dielectric layer having an upper portion and a lower portion. The dielectric layer is either an inter-layer dielectric (ILD) or an inter-metal dielectric (IMD). A phase change random access memory (PCRAM) cell includes a phase change strip, wherein the phase change strip is on the lower portion and has a top surface lower than a top surface of the dielectric layer, and a bottom surface higher than a bottom surface of the dielectric layer. A first conductive column is electrically connected to the phase change strip. The first conductive column extends from the top surface of the dielectric layer down into the dielectric layer. A second conductive column is in a peripheral region. The second conductive column extends from the top surface of the dielectric layer down into the dielectric layer. The first conductive column and the second conductive column have different heights.

Abstract: According to one embodiment, an information recording and reproducing device includes a first layer, a second layer and a recording layer. The recording layer is provided between the first layer and the second layer and being capable of reversibly changing between a first state having a first resistance and a second state having a second resistance higher than the first resistance by a current supplied via the first layer and the second layer. The recording layer includes a first compound layer and an insulating layer. The first compound layer contains a first compound. The first compound includes a first cation element and a second cation element of a type different from the first cation element. The insulating layer contains a third compound, and the third compound includes an element selected from group 1 to 4 elements and group 12 to 17 elements in the periodic table.

Abstract: A method for manufacturing a resistive switching memory device comprises providing a substrate comprising an electrical contact, providing on the substrate a dielectric layer comprising a trench exposing the electrical contact, and providing in the trench at least the bottom electrode and the resistive switching element of the resistive memory device. The method may furthermore comprise providing a top electrode at least on or in the trench, in contact with the resistive switching element. The present invention also provides corresponding resistive switching memory devices.

Abstract: A nanoscale switching device is provided, comprising: a first electrode of a nanoscale width; a second electrode of a nanoscale width; an active region disposed between the first and second electrodes, the active region having at least one non-conducting layer comprising an electronically semiconducting or nominally insulating and a weak ionic conductor switching material capable of carrying a species of dopants and transporting the dopants under an electric field; and a source layer interposed between the first electrode and the second electrode and comprising a highly reactive and highly mobile ionic species that reacts with a component in the switching material to create dopants that are capable of drifting through the non-conducting layer under an electric field, thereby controlling dopant profile by ionic modulation. A crossbar array comprising a plurality of the nanoscale switching devices is also provided, along with a process for making at least one nanoscale switching device.

Abstract: A semiconductor device, a semiconductor module, an electronic apparatus and methods of fabricating and manufacturing the same are provided. The semiconductor device includes a lower interconnection formed on a substrate, a plurality of control patterns formed on the lower interconnection, a plurality of lower contact plug patterns formed on the control patterns, a plurality of storage patterns formed on the lower contact plug patterns, a plurality of upper electrodes formed on the storage patterns, and a plurality of upper interconnections formed on the upper electrodes. The lower contact plug patterns each include at least two contact holes having different sizes, a plurality of sidewall patterns formed on inner sidewalls of the two contact holes and wherein the sidewall patterns have different thicknesses from one another.

Abstract: A resistive memory device is provided. The resistive memory device includes a bottom electrode, a resistance-variable layer, and a top electrode. The resistance-variable layer is disposed on the bottom electrode. The top electrode is disposed on the resistance-variable layer. The resistance-variable layer includes a conductive polymer layer that reacts with the top electrode to form an oxide layer.

Abstract: A memory element with reduced degradation of memory characteristics that is caused by deterioration of a memory layer, a method of manufacturing the memory element, and a memory device are provided. The memory element includes a first electrode, a memory layer, and a second electrode in this order. The memory layer includes a resistance change layer containing fluoride, and an ion source layer disposed between the resistance change layer and the second electrode.

Abstract: A diode and a memory device having a diode are provided. The diode includes a semiconductor layer and phase change material layer. The semiconductor layer and the phase change material layer have different energy bandgaps and different carrier concentrations such that an isotype heterojunction is formed at a boundary interface between the semiconductor layer and the phase change material layer.

Abstract: A resistance switching memory is introduced herein. The resistance switching memory includes a highly-insulating or resistance-switching material formed to cover the sidewall of a patterned metal line, and extended alongside a dielectric layer sidewall to further contact a portion of the top surface of the lower electrode. The other part of the top surface of the lower electrode is covered by an insulating layer between the top electrode and the lower electrode. An oxygen gettering metal layer in the lower electrode occupies a substantial central part of the top surface of the lower electrode and is partially covered by the highly-insulating or resistance-switching material. A switching area is naturally very well confined to the substantial central part of the oxygen gettering metal layer of the lower electrode.

Abstract: A variable resistance memory cell structure and a method of forming it. The method includes forming a first electrode, forming an insulating material over the first electrode, forming a via in the insulating material to expose a surface of the first electrode, forming a heater material within the via using gas cluster ion beams, forming a variable resistance material within the via, and forming a second electrode such that the heater material and variable resistance material are provided between the first and second electrodes.

Abstract: A resistive switching memory device is provided with first to third electrodes. The first electrode forms a Schottky barrier which can develop a rectifying property and resistance change characteristics at an interface between the first electrode and an oxide semiconductor. The third electrode is made of a material which provides an ohmic contact with the oxide semiconductor. A control voltage is applied between the first and second electrodes, and a driving voltage is applied between the first and third electrodes.

Abstract: A three-dimensional non-volatile memory system is disclosed including a memory array utilizing shared pillar structures for memory cell formation. A shared pillar structure includes two non-volatile storage elements. A first end surface of each pillar contacts one array line from a first set of array lines and a second end surface of each pillar contacts two array lines from a second set of array lines that is vertically separated from the first set of array lines. Each pillar includes a first subset of layers that are divided into portions for the individual storage elements in the pillar. Each pillar includes a second subset of layers that is shared between both non-volatile storage elements formed in the pillar. The individual storage elements each include a steering element and a state change element.

Abstract: Provided is a nonvolatile memory device including a phase-change memory configured with cross-point memory cells in which memory elements formed of a phase-change material and selection elements formed with a diode are combined. A memory cell is configured with a memory element formed of a phase-change material and a selection element formed with a diode having a stacked structure of a first polycrystalline silicon film, a second polycrystalline silicon film, and a third polycrystalline silicon film. The memory cells are arranged at intersection points of a plurality of first metal wirings extending along a first direction with a plurality of third metal wirings extending along a second direction orthogonal to the first direction. An interlayer film is formed between adjacent selection elements and between adjacent memory elements, and voids are formed in the interlayer film provided between the adjacent memory elements.

Abstract: Embodiments of the present invention are directed to nanoscale memristor devices that provide nonvolatile memristive switching. In one embodiment, a memristor device (100) comprises an active region (102), a first electrode (104) disposed on a first surface of the active region, and a second electrode (106) disposed on a second surface of the active region, the second surface opposite the first surface. The first electrode is configured with a larger width than the active region in a first direction, and the second electrode is configured with a larger width than the active region in a second direction. Application of a voltage to at least one of the electrodes produces an electric field across a sub-region (108) within the active region between the first electrode and the second electrode.

Abstract: The invention relates to a memory device, in particular to a resistively switching memory device such as a Phase Change Random Access Memory (“PCRAM”). In one disclosed method, a nanowire of non-conducting material is formed serving as a mould for producing a nanotube of conducting material. A volume of switching active material is deposited on top of the nanotube, so that the ring-shaped front face of the nanotube couples to the switching active material and thus forms a bottom electrode contact.

Abstract: A phase change memory may include an ovonic threshold switch formed over an ovonic memory. In one embodiment, the switch includes a chalcogenide layer that overlaps an underlying electrode. Then, edge damage, due to etching the chalcogenide layer, may be isolated to reduce leakage current.

Abstract: In some embodiments, a memory cell includes a transistor gate spaced from a channel region by gate dielectric; a source region on one side of the channel region; and a drain region on an opposing side of the channel region from the source region. The channel region has phase change material adjacent the drain region. In some embodiments, the phase change material may be adjacent both the source region and the drain region. Some embodiments include methods of programming a memory cell that has phase change material adjacent a drain region. An inversion layer is formed within the channel region adjacent the gate dielectric, with the inversion layer having a pinch-off region within the phase change material adjacent the drain region. Hot carriers (for instance, electrons) within the pinch-off region are utilized to change a phase within the phase change material.

Abstract: An information recording/reproducing device includes a recording layer, and a recording circuit which records data to the recording layer by generating a phase change in the recording layer. The recording layer includes a first chemical compound having a spinel structure. The recording layer is AxMyX4 (0.1?x?2.2, 1.0?y?2.0), where A includes one selected from a group of Zn, Cd and Hg, M includes one selected from a group of Ti, Zr, Hf, V, Nb and Ta, and X includes O.

Abstract: An electric-pulse-induced-resistance change device (EPIR device) is provided which is a resistance switching device. It has a buffer layer inserted between a first active resistance switching layer and a second active resistance switching layer, with both active switching layers connected to electrode layers directly or through additional buffer layers between the active resistance switching layers and the electrodes. This device in its simplest form has the structure: electrode-active layer-buffer layer-active layer-electrode. The second active resistance switching layer may, in the alternative, be an ion donating layer, such that the structure becomes: electrode-active layer-buffer layer-ion donating layer-electrode. The EPIR device is constructed to mitigate the retention challenge.

Abstract: A substantially planar heater for a phase change memory may taper as it extends upwardly to contact a chalcogenide layer. As a result, the contact area between heater and chalcogenide is reduced. This reduced contact area can reduce power consumption in some embodiments.

Abstract: Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device.

Abstract: Chalcogenide containing semiconductor devices may be formed with a gradient film between a chalcogenide film and another film. The gradient film may have its chalcogenide concentration decrease as it extends away from the chalcogenide film, while the concentration of the other film material increases across the thickness of the gradient film moving away from the chalcogenide film.

Abstract: A nonvolatile memory device with a first conductor extending in a first direction and a semiconductor element above the first conductor. The semiconductor element includes a source, a drain and a channel of a field effect transistor (JFET or MOSFET). The nonvolatile memory device also includes a second conductor above the semiconductor element, the second conductor extending in a second direction. The nonvolatile memory device also includes a resistivity switching material disposed between the first conductor and the semiconductor element or between the second conductor and the semiconductor element. The JFET or MOSFET includes a gate adjacent to the channel, and the MOSFET gate being self-aligned with the first conductor.

Abstract: A semiconductor device is comprised of a semiconductor substrate, conductive layers stacked above the semiconductor substrate, which is comprised of a conductive polysilicon, and a metal layer provided above the conductive layers. Both ends of the conductive layers have stairsteps respectively. The conductive layers are connected in series by a metal layer which is provided on the stairsteps. The conductive layers connected in series comprise a resistance element.

Abstract: Phase change devices, and particularly multi-terminal phase change devices, include first and second active terminals bridged together by a phase-change material whose conductivity can be modified in accordance with a control signal applied to a control electrode. This structure allows an application in which an electrical connection can be created between the two active terminals, with the control of the connection being effected using a separate terminal or terminals. Accordingly, the resistance of the heater element can be increased independently from the resistance of the path between the two active terminals. This allows the use of smaller heater elements thus requiring less current to create the same amount of Joule heating per unit area. The resistance of the heating element does not impact the total resistance of the phase change device.

Abstract: A memory cell device has a bottom electrode and a top electrode, a plug of memory material in contact with the bottom electrode, and a cup-shaped conductive member having a rim that contacts the top electrode and an opening in the bottom that contacts the memory material. Accordingly, the conductive path in the memory cells passes from the top electrode through the conductive cup-shaped member, and through the plug of phase change material to the bottom electrode.

Abstract: A method and apparatus for making analog and digital electronics which includes a composite including a squishable material doped with conductive particles. A microelectromechanical systems (MEMS) device has a channel made from the composite, where the channel forms a primary conduction path for the device. Upon applied voltage, capacitive actuators squeeze the composite, causing it to become conductive. The squishable device includes a control electrode, and a composite electrically and mechanically connected to two terminal electrodes. By applying a voltage to the control electrode relative to a first terminal electrode, an electric field is developed between the control electrode and the first terminal electrode. This electric field results in an attractive force between the control electrode and the first terminal electrode, which compresses the composite and enables electric control of the electron conduction from the first terminal electrode through the channel to the second terminal electrode.

Abstract: The concentration of a constituent within a chalcogenide film used to form a chalcogenide containing semiconductor may be adjusted post deposition by reacting the chalcogenide film with a material in contact with the chalcogenide film. For example, a chalcogenide film containing tellurium may be coated with a titanium layer. Upon the application of heat, the titanium may react with the tellurium to a controlled extent to reduce the concentration of tellurium in the chalcogenide film.

Abstract: A non-volatile memory device may include a first wordline on a substrate, an insulating layer on the first wordline, and a second wordline on the insulating layer so that the insulating layer is between the first and second wordlines. A bit pillar may extend adjacent the first wordline, the insulating layer, and the second wordline in a direction perpendicular with respect to a surface of the substrate, and the bit pillar may be electrically conductive. In addition, a first memory cell may include a first resistance changeable element electrically coupled between the first wordline and the bit pillar, and a second memory cell may include a second resistance changeable element electrically coupled between the second wordline and the bit pillar. Related methods and systems are also discussed.

Abstract: A method of forming a vertical interconnect for a memory device. The method includes providing a substrate having a surface region and defining a cell region, a first peripheral region, and a second peripheral region. A first thickness of dielectric material is formed overlying the surface region. A first bottom wiring structure spatially configured to extend in a first direction is formed overlying the first dielectric material for a first array of devices. A second thickness of a dielectric material is formed overlying the first wiring structure. The method includes forming an opening region in the first peripheral region. The opening region is configured to extend in a portion of at least the first thickness of dielectric material and the second thickness of dielectric material to expose a portion of the first wiring structure and to expose a portion of the substrate.

Abstract: An array includes a transistor comprising a first terminal, a second terminal and a third terminal; a first contact plug connected to the first terminal of the transistor; a second contact plug connected to the first terminal of the transistor; a first resistive memory cell having a first end and a second end, wherein the first end is connected to the first contact plug; and a second resistive memory cell having a third end and a fourth end, wherein the third end is connected to the second contact plug.

Abstract: A method of forming a chalcogenide material on a surface of a substrate comprising exposing a surface of a substrate to ionized gas clusters from a source gas, the ionized gas clusters comprising at least one chalcogen and at least one electropositive element. A method of forming a resistive random access memory device is also disclosed. The method comprises forming a plurality of memory cells wherein each cell of the plurality of memory cells is formed by forming a metal on a first electrode, forming a chalcogenide material on the metal by a gas cluster ion beam process, and forming a second electrode on the chalcogenide material. A method of forming another resistive random access memory device and a random access memory device including the chalcogenide material are also disclosed.

Abstract: A memristive device includes a first electrode, a second electrode crossing the first electrode at a non-zero angle, and an active region disposed between the first and second electrodes. The active region has a controlled defect profile throughout its thickness.

Abstract: A method of forming a nonvolatile memory cell includes forming a first electrode having a first current conductive material and a circumferentially self-aligned second current conductive material projecting elevationally outward from the first current conductive material. The second current conductive material is different in composition from the first current conductive material. A programmable region is formed over the first current conductive material and over the projecting second current conductive material of the first electrode. A second electrode is formed over the programmable region. In one embodiment, the programmable region is ion conductive material, and at least one of the first and second electrodes has an electrochemically active surface directly against the ion conductive material. Other method and structural aspects are disclosed.

Abstract: Some embodiments include methods of programming a memory cell. A plurality of charge carriers may be moved within the memory cell, with an average charge across the moving charge carriers having an absolute value greater than 2. Some embodiments include methods of forming and programming an ionic-transport-based memory cell. A stack is formed to have programmable material between first and second electrodes. The programmable material has mobile ions which are moved within the programmable material to transform the programmable material from one memory state to another. An average charge across the moving mobile ions has an absolute value greater than 2. Some embodiments include memory cells with programmable material between first and second electrodes. The programmable material includes an aluminum nitride first layer, and includes a second layer containing a mobile ion species in common with the first layer.

Abstract: According to one embodiment, a memory device includes a nanomaterial assembly layer, a first electrode layer and a second electrode layer. The nanomaterial assembly layer is formed of an assembly of a plurality of micro conductors via gaps between the micro conductors. The first electrode layer is provided on the nanomaterial assembly layer. The second electrode layer is provided on the first electrode layer.

Abstract: A semiconductor device includes a semiconductor element. The semiconductor element comprises a first insulating film, a resistance changing layer, a first electrode, a buried layer, and a second electrode. The first electrode is formed within the opening so as to cover side and bottom surfaces of an inner wall of the opening and so as to include a recessed portion and is in contact with the resistance changing layer via the upper end thereof. The second electrode is formed on the resistance changing layer so as to interpose the resistance changing layer between the second electrode, and the upper end of the first electrode and the buried layer. The semiconductor element changes an electronic resistance between the first and second electrodes by reversibly forming a conductive bridge in the resistance changing layer between the upper end of the first electrode and the second electrode.

Abstract: Programmable metallization memory cells include an electrochemically active electrode and an inert electrode and an ion conductor solid electrolyte material between the electrochemically active electrode and the inert electrode. A sacrificial metal is disposed between the electrochemically active electrode and the inert electrode. The sacrificial metal has a more negative standard electrode potential than the filament forming metal.