Beam Lead Frame Or Beam Lead Device Patents (Class 29/827)
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Patent number: 6986197Abstract: A method is provided for processing leadframe items of two or more types to form integrated circuit packages. The leadframe items are delivered along respective input paths and are received into holders, which are moved alternately between a processing region and a respective leadframe item reception position on a respective input path such that each of the holders moves to the processing region at a time when the other of the holders moves to its respective reception position. The leadframe items are delivered from the respective reception position to the processing region, and are then sent for encapsulation.Type: GrantFiled: December 6, 2001Date of Patent: January 17, 2006Assignee: ASM Technology Singapore PTE Ltd.Inventors: Jian Wu, Yan Zhou, Shu Chuen Ho, Teng Hock Kuah
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Patent number: 6983536Abstract: A method and apparatus for fabricating known good semiconductor dice are provided. The method includes the steps of: testing the gross functionality of dice contained on a semiconductor wafer; sawing the wafer to singulate a die; and then testing the die by assembly in a carrier having an interconnect adapted to establish electrical communication between the bond pads on the die and external test circuitry. The interconnect for the carrier can be formed using different contact technologies including: thick film contact members on a rigid substrate; self-limiting contact members on a silicon substrate; or microbump contact members with a textured surface. During assembly of the carrier, the die and interconnect are optically aligned and placed into contact with a predetermined contact force. This establishes an electrical connection between the contact members on the interconnect and the bond pads of the die.Type: GrantFiled: May 18, 2004Date of Patent: January 10, 2006Assignee: Micron Technology, Inc.Inventors: Warren Farnworth, Alan Wood
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Patent number: 6983537Abstract: A plastic package base, an air cavity type plastic package, and their manufacturing methods, which are capable of realizing the advantages of a ceramic package in that it has a compact size, makes less noise, and is highly thermally resistant, are provided.Type: GrantFiled: July 20, 2001Date of Patent: January 10, 2006Assignee: Mediana Electronic Co., Ltd.Inventor: Chan-ik Park
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Patent number: 6969918Abstract: A system for fabricating semiconductor components includes mating mold cavity plates having mold cavities configured to mold body segments of the semiconductor components on either side of a leadframe. The mold cavity plates also include runners configured to direct molding compound between the mold cavities and into the corners of the mold cavities. The runners prevent trapped air from accumulating in the corners of the mold cavities, and eliminate the need for air vents in the corners. The mold cavity plates also include dummy mold cavities configured to form dummy segments on the leadframe, and air vents in flow communication with the dummy segments. The dummy mold cavities are configured to collect trapped air, and to direct the trapped air through the air vents to atmosphere. Each dummy mold cavity has only a single associated air vent, such that cleaning is facilitated, and flash particles from the air vents are reduced.Type: GrantFiled: August 30, 2001Date of Patent: November 29, 2005Assignee: Micron Technology, Inc.Inventors: Steven L. James, Lori Tandy, legal representative, William D. Tandy, deceased
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Patent number: 6958528Abstract: A semiconductor device assembly including a semiconductor device having a plurality of bond pads on the active surface thereof and a lead frame having a portion of the plurality of lead fingers of the lead frame located below the semiconductor device in a substantially horizontal plane and another portion of the plurality of lead fingers of the lead frame located substantially in the same horizontal plane as the active surface of the semiconductor device. Both pluralities of lead fingers of the lead frame having their ends being located substantially adjacent the peripheral sides of the semiconductor device, rather than at the ends thereof.Type: GrantFiled: November 19, 2002Date of Patent: October 25, 2005Assignee: Micron Technology, Inc.Inventor: David J. Corisis
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Patent number: 6954984Abstract: A Land Grid Array structure is enhanced with a flex film interposer that not only provides a Land Grid Array (LGA) electrical connection between a Multi-Chip Module (MCM) and the next level of integration such as a system board, but also provides a reliable means to implement desired Engineering Change (EC) capability as well as a means for decoupling power to ground structure to minimize switching activity effects on the System. The invention as described can be implemented for EC repair, for Capacitive Decoupling or both.Type: GrantFiled: July 25, 2002Date of Patent: October 18, 2005Assignee: International Business Machines CorporationInventors: Michael F. McAllister, John G. Torok
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Patent number: 6948239Abstract: A method for fabricating a semiconductor apparatus using a board frame. A wiring board region of the frame includes an island on which a semiconductor device is mounted. A marginal region of the frame surrounds the wiring board region. A frame region is located around the marginal region. A support region extends between the wiring board region and the frame region to connect the wiring board region and frame region together through the support region. The marginal region is removed from the board frame and then put back to its original position, while maintaining the wiring board region connected to the frame region through the support region. Then, the device is mounted onto the island. Next, transfer-molding is performed on the device using a die set that includes a gate through which a thermosetting resin is guided into a cavity. Then, the marginal region is removed completely from the board frame.Type: GrantFiled: December 12, 2002Date of Patent: September 27, 2005Assignee: Oki Electric Industry Co., Ltd.Inventor: Takahiro Oka
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Patent number: 6949837Abstract: A variety of pad arrangements are provided for semiconductor devices for reducing the likelihood of bonding failures, particularly those due to shorts, and/or for reducing the difference in length between bonding wires to decrease signal skew during operation of the semiconductor device and improve signal integrity.Type: GrantFiled: June 20, 2003Date of Patent: September 27, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Ho-Cheol Lee, Jae-Hoon Kim, Jung-Su Ryu
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Patent number: 6935020Abstract: A method of producing a battery-connecting plate by providing busbars which connect batteries together, attaching terminals to one end of wires to produce terminal-attached wires for detecting voltage of desired ones of the batteries, placing the terminal-attached wires in a predetermined layout in a wire protector, setting the busbars and wire protector in a mold with the burbars positioned corresponding to an arrangement of the batteries, injecting resin into the mold to produce a molded piece with the burbars and the terminal-attached wires therein, and cutting an element mount portion of each of the terminals and connecting a respective circuit protector element to the element mount portion in a bridging manner across the cut.Type: GrantFiled: December 13, 2001Date of Patent: August 30, 2005Assignee: Yazaki CorporationInventor: Tomohiro Ikeda
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Patent number: 6929485Abstract: A lead frame includes pins for a plurality of parts. The pins for the plurality of the parts include first pins for a first part and first pins for a second part. The first pins for the first part include first shaped pins and second shaped pins. Each of the first shaped pins has a wide area of a first length, and a narrow area. Each of the second shaped pins has a wide area of a second length and a narrow area. The first length and the second length are not equal. The first pins for the first part are interdigitated with the first pins for the second part.Type: GrantFiled: March 16, 2004Date of Patent: August 16, 2005Assignee: Agilent Technologies, Inc.Inventors: Ak Wing Leong, Michael J. Brosnan
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Patent number: 6925704Abstract: A high power resistor includes a resistance element with first and second leads extending out from the opposite ends thereof. A heat sink of dielectric material is in heat conducting relation to the resistance element. The heat conducting relationship of the resistance element and the heat sink render the resistance element capable of operating as a resistor between the temperatures of ?65° C. to +275° C. The heat sink is adhered to the resistance element and a molding compound is molded around the resistance element.Type: GrantFiled: December 23, 2003Date of Patent: August 9, 2005Assignee: Vishay Dale Electronics, Inc.Inventors: Greg Schneekloth, Nathan Welk, Brandon Traudt, Joel Smejkal, Ronald J. Miksch, Steve Hendricks, David L. Lange
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Patent number: 6922889Abstract: A shifting device for shifting two rows of continuous terminals includes a body and a shaft. The body is formed with a hole and an inlet and an outlet both communicating with the hole. A direction into the inlet and a direction out of the outlet are the same. The inlet is shifted a predetermined distance away from the outlet. The shaft is fitted with the hole of the body and defines a spiral channel with the body after fitting with the hole of the body. The spiral channel corresponds to the inlet and the outlet of the body According to the structure, one row of the continuous terminals enters the body from the inlet and travels along the spiral channel and travels out of the body from the outlet with a predetermined distance shifted away from the other row of the continuous terminals.Type: GrantFiled: December 20, 2001Date of Patent: August 2, 2005Inventor: Chou Hsuan Tsai
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Patent number: 6920688Abstract: A method of making an integrated circuit device using an encapsulated semiconductor die, having leads extending therefrom and attaching a heat spreader to each of the major outer encapsulant surfaces thereof, is disclosed. One or both of the heat spreaders has a pair of end posts configured for allowing further encapsulation of portions thereof and insertion into through-holes in a substrate to position and support the device during and following the outer lead solder reflow step at board assembly. The heat spreaders provide high heat dissipation and EMR shielding, and may be connected to the substrate ground to become ground planes.Type: GrantFiled: August 27, 2002Date of Patent: July 26, 2005Assignee: Micron Technology, Inc.Inventor: David J. Corisis
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Patent number: 6912781Abstract: A device for electrically interconnecting and packaging electronic components. A non-conducting base member having a component recess and a set of specially shaped lead channels formed therein is provided. At least one electronic component is disposed within the recess, and the conductors of the component are routed through the lead channels. A set of insertable lead terminals, adapted to cooperate with the specially shaped lead channels, are received and captured within the lead channels, thereby forming an electrical connection between the lead terminals and the conductors of the electronic component(s). A method of fabricating the device is also disclosed.Type: GrantFiled: September 11, 2002Date of Patent: July 5, 2005Assignee: Pulse Engineering, Inc.Inventors: Timothy J. Morrison, Aurelio J. Gutierrez, Thomas Rascon
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Patent number: 6909167Abstract: Two dice may be provided within a single package so that one pin and associated leadfinger may be coupled to bond pads on different dice. This may mean that two different bond pads on different dice are coupled, for example by wirebonding, to the same leadfinger. An adhesive tape may be secured so as to bridge the two dice. One or more conductive traces are formed on the upper side of the adhesive tape and adhesive is provided on the other side to secure the tape to the two dice. As a result, wire bonds may be made from a pad on one die to a trace and then from the opposite side of the trace to a leadfinger. At the same time, a wire bond may be made from a pad on the other die to the same leadfinger. In another embodiment, an adhesive tape with a conductive trace on it may be used as a wire bond bridge to join spaced bond pads on a single chip.Type: GrantFiled: May 14, 2004Date of Patent: June 21, 2005Assignee: Micron Technology, Inc.Inventor: Jicheng Yang
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Patent number: 6907659Abstract: A method for manufacturing and packaging an integrated circuit includes following steps: pressure a continuous pin material and a base board area at first; then cut off pin material into several pin units, accommodate each pin units into respective position in a mould, and ejecting plastic into the mould gap to shape a pin unit, then remove waste part of the pin material after removing down the mould parts; put four pin units and a base board into a rectangle mould, then eject plastic again into mould gap, after that cut off waste part of the base board to attain an IC socket; stick an IC chip on top of the base board of the IC socket and wire it. Finally, cover and stick a panel on the IC socket to finish the whole IC packaging procedures.Type: GrantFiled: February 5, 2003Date of Patent: June 21, 2005Assignee: Advanced Connection Technology Inc.Inventor: Ching-Shun Wang
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Patent number: 6901655Abstract: A surface mount resistor includes an elongated piece of resistive material having strips of conductive material attached to its opposite ends. The strips of conductive material are separated to create an exposed central portion of the resistive material therebetween. According to the method the resistive strip is attached to a single co extensive strip of conductive material and a central portion of the conductive material is removed to create the exposed central portion of the resistive strip.Type: GrantFiled: March 10, 2004Date of Patent: June 7, 2005Assignee: Vishay Dale Electronics, Inc.Inventors: Joel J. Smejkal, Steve E. Hendricks
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Patent number: 6895664Abstract: A lead frame of an optical coupling device of the present invention is so arranged that (a) a light-emitting side section in which a plurality of header sections for mounting thereon the light-emitting elements are aligned and (b) a light-receiving side section in which a plurality of header sections for mounting thereon the light-receiving element are aligned, and (c) a connecting section for connecting the light-emitting side section and the light-receiving side section in parallel into one body. The light-emitting side section and the light-receiving side section are integrated via a connecting section at which a V groove is formed for facilitating the folding of the lead frame. As a result, it is possible to provide a low-cost lead frame of an optical coupling device with a small number of components can be realized, in a simplified manner, and a manufacturing method of the optical coupling device.Type: GrantFiled: October 15, 2002Date of Patent: May 24, 2005Assignee: Sharp Kabushiki KaishaInventors: Hideya Takakura, Kazuo Kusuda
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Patent number: 6895665Abstract: A method of manufacturing a housing for electronic parts, such as isolators, or the like, with as small non-plated portions as possible, which housing is obtained by separating a housing part from a metallic housing part support with the housing part connected to a frame through connections, the method comprising the steps of cutting off and removing the connections after provisional connections of a resin are formed on the housing part support to connect the frame to the housing part, and obtaining the housing for electronic parts by removing the provisional connections after plating is applied to surfaces of the housing part including cut portions of the connections.Type: GrantFiled: June 4, 2003Date of Patent: May 24, 2005Assignee: Alps Electric Co., Ltd.Inventor: Akira Sakai
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Patent number: 6892449Abstract: A method of manufacturing a plurality of electro-optical sub-assemblies in parallel is provided. A plurality of printed circuit boards (PCBs) are preferably formed in a panel of flex material. Rigid substrates can be arranged along regions of the PCBs. A plurality of electrical components, including electro-optical semiconductor devices, are preferably located on the rigid substrates. Lens arrays are preferably aligned over the electro-optical semiconductor devices, such as through an alignment mechanism. The PCBs can then be singulated into individual electro-optical sub-assemblies. The rigid substrates can be a plurality of leadframes formed on a matrix leadframe. The matrix leadframe is preferably attached to the panel of flex material such that the leadframes are arranged in proximity to leadframe cutout regions of the PCBs. Electrical interconnections are then preferably formed between the electrical components on the leadframe and the PCBs.Type: GrantFiled: October 9, 2002Date of Patent: May 17, 2005Assignee: Cypress Semiconductor Corp.Inventors: Brenor Brophy, Marc Hartranft, Syed Tariq Shafaat, Jeff Hall
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Patent number: 6869813Abstract: A chip-type LED including a LED element and a tubular vessel accommodating the LED element therein, wherein the vessel has an upper opening and a lower opening, the LED element is positioned between the upper opening and the lower opening such that the LED element emits light toward the upper opening, and the vessel is filled with a light-transmissive resin from the upper opening to the lower opening.Type: GrantFiled: August 25, 2003Date of Patent: March 22, 2005Assignee: Sharp Kabushiki KaishaInventor: Jun Okazaki
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Patent number: 6865786Abstract: In a method of manufacturing a surface acoustic wave device using a Shear Horizontal type surface acoustic wave, at least one interdigital transducer (IDT) is made of a material having a larger mass-load effect than that of aluminum. The metallization ratio of the IDT and the normalization film thickness h/? of the IDT are controlled such that ripple caused by a transversal mode wave is about 1.5 dB or less, where “h” indicates the film thickness of the electrodes and “h” indicates the wavelength of a surface acoustic wave.Type: GrantFiled: July 7, 2003Date of Patent: March 15, 2005Assignee: Murata Manufacturing Co., Ltd.Inventors: Takeshi Nakao, Koji Fujimoto, Michio Kadota, Toshimaro Yoneda
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Patent number: 6862806Abstract: A manufacturing method manufactures plates having a predetermined pattern, wherein the predetermined pattern is in each frame, side by side, at certain intervals along the longitudinal direction of the frame. A plurality of positioning holes, into which pins are inserted, are formed in each frame. A retainer portion is provided so as to extend from the inner periphery of each positioning hole and is plastically deformed when a pin is inserted thereinto. By inserting a pin into each positioning hole while a plurality of frames are stacked, the outer periphery of the pin contacts the retainer portion of each positioning hole. The retainer portion is deformed to correct misalignment among a plurality of plates.Type: GrantFiled: October 17, 2001Date of Patent: March 8, 2005Assignee: Brother Kogyo Kabushiki KaishaInventors: Atsushi Ito, Masaaki Deguchi, Hisaki Sakurai
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Patent number: 6860004Abstract: In a method of manufacturing a thermally conductive circuit board with high heat dissipation, high conductivity and high ground-connection, a sheet-like thermally conductive resin composition containing 70 to 95 wt. % inorganic filler and 5 to 30 wt. % thermosetting resin composition, a lead frame as a wiring pattern, and an electrically conductive heat sink with a metal pole placed therein are superposed, heated and compressed, and thus are combined to form one body. Consequently, a thermally conductive circuit board with a flat surface is obtained in which a grounding pattern is grounded to the heat sink inside the insulating layer. Thus, the grounding pattern and the heat sink can be connected electrically with each other in an arbitrary position inside the insulating layer of the thermally conductive circuit board.Type: GrantFiled: December 3, 2002Date of Patent: March 1, 2005Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Koichi Hirano, Seiichi Nakatani, Mitsuhiro Matsuo, Yoshihisa Yamashita
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Patent number: 6845556Abstract: Circuit board reworking techniques involve removing original solder from the metallic pad, removing an outer portion of the metallic pad to expose an inner portion of the metallic pad, and applying new solder to the metallic pad. Removal of the original solder and the outer portion of the metallic pad exposes the inner portion which has non-corroded and non-contaminated metal. The application of new solder to this inner portion of the pad enables wettability of the pad as well as provides a protective coating to prevent corrosion of the inner portion (e.g., oxidation, reaction with contaminants, etc.). Accordingly, circuit board abnormalities such as “Black Pad” defects can be cured.Type: GrantFiled: March 20, 2002Date of Patent: January 25, 2005Assignee: EMC CorporationInventor: Jin Liang
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Publication number: 20040255454Abstract: A method of forming a semiconductor package is provided. The method includes forming a leadframe wherein the conductors or leads of the leadframe extend from a first end to a second end such that a portion of each lead exhibits a generally arcuate shape. The first end may be coupled with a printed circuit board and the second end may be coupled with a semiconductor die. The generally arcuately shaped portion of the leads may include a portion which exhibits a constant radius. The generally arcuately shaped portion may also be formed from a plurality of conductor segments including, for example, at least one generally arcuately shaped segment. The semiconductor die and at least a portion of the leads may be encapsulated with an insulating material.Type: ApplicationFiled: July 21, 2004Publication date: December 23, 2004Inventors: Ronnie M. Harrison, David J. Corisis
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Publication number: 20040252474Abstract: A novel multi chip module having increased accuracy of the soldering the integrated circuits (ICs) is provided by utilizing two additional lead frames and turning over the first lead frame soldered IC and stacking secondary IC thereon. Arrays of the first lead frames are mounted on a top tray guided by tooling pins. Solder pastes are printed on the first lead frames. Arrays of the second lead frames are placed on the first lead frames guided with tooling pins. Another layer of solder pastes are printed on the second lead frames. Thermal conductive glue is dispensed on the central portions of the first lead frames. ICs, which become the “bottom ICs” later, are placed on the central portions of the first lead frames upside down by a pick/place machine. After heat treatment, inspection and repair, the bottom ICs are mounted in a pocket on a bottom tray facing the first lead frames upside. Another layer of solder pastes are printed on the first lead frames.Type: ApplicationFiled: November 25, 2002Publication date: December 16, 2004Inventors: Kwanghak Lee, Hanjoo Na, Myeongjin Shin, Paul Wengseng Heng
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Publication number: 20040224436Abstract: A method of producing TAB tape carrier that can produce TAB tape carrier in such a way as to prevent undulation at a split end surface thereof and tear of circuit pattern thereat, thereby producing the TAB tape carrier of high reliability with increased efficiency. In the method, an insulating layer 2 is formed on an elongate metal supporting layer 1 by application of resin solution to the metal supporting layer 1 and by drying, first. Then, a plurality of lines of wiring patterns 3 are formed on the insulating layer 2 in a semi-additive process. Thereafter, slit grooves S are formed in the metal supporting layer 1 in spaces between adjacent lines of wiring patterns 3. Then, the insulating layer 2 is split along the slit grooves S to divide the continuous sheet into individual strips, thereby producing the TAB tape carriers 12.Type: ApplicationFiled: May 6, 2004Publication date: November 11, 2004Inventor: Toshiki Naito
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Patent number: 6813828Abstract: A method is provided for deconstructing an integrated circuit package comprising: taking an integrated circuit package comprising a lead frame having a plurality of wire bond pads for placing a die into electrical contact with the lead frame, and an encapsulant encapsulating the wire bond pads; and removing the encapsulant to expose the wire bond pads; wherein at least a portion of the encapsulant is removed by a lapping process.Type: GrantFiled: January 7, 2002Date of Patent: November 9, 2004Assignee: Gel Pak L.L.C.Inventors: Joseph J. Dlugokecki, Gerardo Bagalawig Nazareno, Carmencita I. Robbins, Steven David Swendrowski
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Patent number: 6807719Abstract: An apparatus for inserting terminals carried on a carrier strip into cavities in a housing having a slide assembly with a cam track movable between a first and a second position, and a pivoting lever with a cam follower. The cam follower is positioned in and cooperates with the cam track. The lever is movable between an open and closed position and has first and second shearing blades. An eccentric pin extends through the lever and is attached to a rotary actuator. The eccentric pin is positioned to act as the pivot point for the lever. The rotary actuator is movable between an engaged and disengaged position. As the lever is moved to the closed position, the first shearing blades engage and shear a first portion of the carrier strip. As the rotary actuator moves to an engaged position, the second shearing blade engages and shears a second portion of the carrier strip.Type: GrantFiled: October 11, 2002Date of Patent: October 26, 2004Assignee: Tyco Electronics CorporationInventors: Marlin Edward Herr, John Michael Wasilko, Christopher John Karrasch, George Edward Hoover
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Patent number: 6806559Abstract: Prepackaged chips, such a memory chips, are vertically stacked and bonded together with their terminals aligned. The exterior lead frames are removed including that portion which extends into the packaging. The bonding wires are now exposed on the collective lateral surface of the stack. In those areas where no bonding wire was connected to the lead frame, a bare insulative surface is left. A contact layer is disposed on top of the stack and vertical metallizations defined on the stack to connect the ends of the wires to the contact layer and hence to contact pads on the top surface of the contact layer. The vertical metallizations are arranged and configured to connect all commonly shared terminals of the chips, while the control and data input/output signals of each chip are separately connected to metallizations, which are disposed in part on the bare insulative surface.Type: GrantFiled: April 22, 2002Date of Patent: October 19, 2004Assignee: Irvine Sensors CorporationInventors: Keith D. Gann, Douglas M. Albert
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Publication number: 20040200062Abstract: A method for providing a leadframeless package structure is provided. The method includes providing a temporary carrier. The temporary carrier is coupled to a metal foil layer with a temporary adhesive layer. An integrated circuit chip is coupled to the metal foil layer. The temporary adhesive layer and the temporary carrier are removed to form the leadframeless package structure after molding.Type: ApplicationFiled: April 29, 2004Publication date: October 14, 2004Applicant: STMicroelectronics, Inc.Inventors: Harry M. Siegel, Anthony M. Chiu
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Patent number: 6796024Abstract: According to the method of producing a semiconductor device, the substrate is provided with an opening formed at a substantially central position, interconnections and joining parts. The heat spreading plate has a fixed portion fixed to the substrate, a stage portion caved with respect to the fixed potion and connecting portions connecting the fixed portion and the stage portion. The heat spreading plate is fixed by positioning the stage portion at a position opposing the opening, then the heat spreading plate is welded to the substrate and the semiconductor chip is mounted on the stage portion through the opening. Then the semiconductor chip and interconnections formed on the substrate are electrically connected and sealing resin is formed on both sides of the heat spreading plate such that at least the semiconductor chip is sealed.Type: GrantFiled: March 20, 2003Date of Patent: September 28, 2004Assignee: Fujitsu LimitedInventors: Yoshitsugu Katoh, Mitsuo Abe, Yoshihiko Ikemoto, Sumikazu Hosoyamada
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Publication number: 20040181938Abstract: Clean accommodation and carrying of semiconductor devices are to be attained. A stack type tray is used which comprises a base portion 1d with plural pockets formed therein in a matrix shape and side walls formed along peripheral edges of the base portion. In the tray is buried an electronic tag which is constituted by a mu-chip having memory with non-contact recognizable information stored therein. Information pieces such as ID, manufacturer's name and product number of the tray, as well as product name, quantity and lot number of an object to be accommodated, are stored in the mu-chip of the electronic tag, and by accommodating a to-be-accommodated object in the tray equipped with the mu-chip and carrying it, the generation of dust can be prevented because paper label is not used.Type: ApplicationFiled: February 4, 2004Publication date: September 23, 2004Applicants: Renesas Technology Corp, Hitachi Transport System, Ltd.Inventors: Hiromichi Suzuki, Wahei Kitamura, Tokuji Toida, Toshimasa Shirai
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Patent number: 6791845Abstract: Methods for mounting electrical components on a substrate and securely retaining the components are described. The methods include altering solder paste compositions, interposed between component retentive pins and retentive through holes, during a reflow process. Electronic assemblies including circuit boards and electrical components mounted thereto are also described. In one of the electronic assembly embodiments, materials originally associated with a mounted electrical component migrate into solder paste coupling the electrical component to the circuit board.Type: GrantFiled: September 26, 2002Date of Patent: September 14, 2004Assignee: FCI Americas Technology, Inc.Inventor: Yakov Belopolsky
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Patent number: 6782612Abstract: The present invention is to provide a manufacturing process of an integrated circuit module comprising the following steps: (a) providing a circuit board, which has at least one module circuit pattern thereon, said circuit pattern having at least one chip assembly area and an electronic element assembly area; (b) mounting at least one substrate on said at least one chip assembly area; said substrate is provided thereon with at least one connecting circuit pattern which is electrically connected to the at least one module circuit pattern of said circuit board; (c) mounting at least one IC chip on said at least one substrate such that said IC chip is electrically connected to said connecting circuit pattern of the substrate.Type: GrantFiled: January 16, 2002Date of Patent: August 31, 2004Inventor: Wen-Wen Chiu
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Patent number: 6782610Abstract: The present invention relates to a method for fabricating a wiring substrate by forming an insulating film on a metal base having openings on the metal base at positions corresponding to metal bumps to be formed later; forming at least one layer of wiring on the base made of a metal through the insulating film, the layer of wiring having a wring film formed thereon by electroplating; and selectively etching the base. The insulating film can be a liquid photosensitive polyamide, the wiring layer can be copper and the wiring film can be a conductive layer selected from the group consisting of Ni-P and Ni. In the present invention, the wiring layer can be formed through the insulating film in contact with the metal base at the openings in the insulating film and in contact with the insulating film where there are no openings in the insulating film.Type: GrantFiled: December 20, 1999Date of Patent: August 31, 2004Assignee: North CorporationInventors: Tomoo Iijima, Masayuki Oosawa, Shigeo Hirade
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Multi-chip package having improved heat spread characteristics and method for manufacturing the same
Patent number: 6781849Abstract: A multi-chip package (MCP) in which heat generated in first and second chips of the MCP is spread effectively and a method for manufacturing the same. The MCP includes first and second chips. The MCP further comprises a tape including a conductive material layer therein situated between the first chip and the second chip. Thus, the heat generated in the second chip can effectively spread to the outside through the tape.Type: GrantFiled: April 7, 2003Date of Patent: August 24, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Joong-hyun Baek, Tae-koo Lee, Min-ha Kim, Yun-hyeok Im -
Patent number: 6780767Abstract: Semiconductor components in a wafer assembly, in which the components are connected to a frame by means of in each case one holder and are formed from the same silicon wafer. The holder connects the respective component to the frame on one side and has a desired breaking point. The desired breaking point is designed as a V-shaped groove, the surfaces of which form crystal planes. According to the method, the patterning for production of the holder takes place on the wafer back surface, with subsequent wet chemical anisotropic etching of the V-groove. In this way, the holder is produced independently of the processing of the wafer front surface, and when the semiconductor component is removed a defined broken edge is formed without there being any risk of the semiconductor component being damaged.Type: GrantFiled: June 21, 2002Date of Patent: August 24, 2004Assignee: Nanoworld AGInventor: Stefan Lutter
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Patent number: 6779260Abstract: An overmolded electronic package includes a circuit-carrying substrate and a connector housing or shroud interconnected via a suitable interconnection arrangement. Some embodiments may include a backplate affixed to the substrate and, in some cases, also to the connector housing or shroud. In some embodiments, the connector housing or shroud may be affixed to the substrate, and in any case the entire subassembly of components is overmolded with a rigidly formable molding compound to bond together all components of the subassembly and form the overmolded electronic package. The subassembly of components with the exception of the backplate may alternatively be overmolded with the molding compound, and a backplate thereafter affixed to the subassembly via a compliant bonding medium.Type: GrantFiled: March 28, 2003Date of Patent: August 24, 2004Assignee: Delphi Technologies, Inc.Inventors: Scott D. Brandenburg, Thomas A. Degenkolb, Bruce A. Myers
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Patent number: 6779264Abstract: A method for manufacturing an electronic device by placing within a die a first lead with an element placement pad, a second lead, and an electronic element placed on the element placement pad. The electronic element, the element placement pad, a part of the first lead, and a part of the second lead are sealed in a package by injecting a sealing resin in the die from a position on a longer side of the package, with the position being offset toward one shorter side thereof. The first lead is bent in an S shape, with a bending depth being at least as large as the thickness of the first lead. A thickness of the resin on a non-device side of the element placement pad is smaller than the bending depth.Type: GrantFiled: October 8, 1999Date of Patent: August 24, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Takeshi Kobayashi, Hideki Fukazawa, Satoshi Utsunomiya
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Patent number: 6778247Abstract: A cutting method of a tap carrier package of a liquid crystal display. The cutting method cuts a film comprising a first straight layout along a predetermined direction on a wiring layer comprising a second straight layout along the predetermined direction and a oblique layout, the method comprises the following steps. First, a breach is formed by cutting a part of the first straight layout on the film. Finally, the film is fastened on the wiring layer. Thus, the remaining first straight layout is only connected to the straight layout and the oblique layout is exposed through the breach.Type: GrantFiled: August 23, 2002Date of Patent: August 17, 2004Assignee: Hannstar Display Corp.Inventors: Chi-Tien Lee, Jiunn-Yau Huang, Mei-Hui Lin, Deuk-Su Lee
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Publication number: 20040145883Abstract: A method of manufacturing an optical communication module, and a mold and a lead frame that are suitable for the method are provided. The method comprises the steps of: placing in a mold the lead frame on which a ferrule and an optical communication facility section are mounted; pressing the ferrule by a moving part that can be stopped at a given position relative to the mold (lower mold tool) such that the distal end of the ferrule is positioned at a proper location within the mold; and filling a resin into the mold, wherein a displacement and a reactive force generated in the lead frame when it is pressed are absorbed by springs provided in the lead frame when it is pressed are absorbed by springs provided in the lead frame such that a catching portion for coupling to a connector is formed with high accuracy at a proper position relative the distal end of the ferrule.Type: ApplicationFiled: January 23, 2003Publication date: July 29, 2004Inventors: Takeshi Okada, Hiromi Nakanishi
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Publication number: 20040143962Abstract: A method is provided for processing a lead frame. Generally, a first surface of a lead frame base tape is placed on a first surface of the lead frame. A second surface of the lead frame base tape is placed on a first surface of a porous block. A vacuum is placed on a second surface of the porous block. A device for processing lead frames comprises a porous block with a first side and a second side, and a vacuum system connected to the first side of the porous block. The device may also include devices for attaching chips to the lead frame and wire bonding the chips to the lead frame.Type: ApplicationFiled: January 15, 2004Publication date: July 29, 2004Applicant: National Semiconductor CorporationInventors: Ah Lek Hu, Sharon Mei Wan Ko, Peng Yeen Chan, Jaime Bayan
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Patent number: 6764882Abstract: A semiconductor card includes a printed circuit substrate upon which is mounted a card circuit including one or more semiconductor components such as dice or packages. External contacts link the card circuit to the circuit of another apparatus by removable insertion therein. The substrate is defined by a peripheral opening in a surrounding frame, which may be part of a multiframe strip. The substrate is connected to the frame by connecting segments. The card includes a first plastic casting molded to the substrate and encapsulating the semiconductor components while leaving a peripheral portion of the substrate uncovered. A second plastic casting is molded to the peripheral portion to abut the first plastic casting and form the card periphery. A method for fabricating the semiconductor card is also included.Type: GrantFiled: August 5, 2002Date of Patent: July 20, 2004Assignee: Micron Technology, Inc.Inventor: Todd O. Bolken
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Patent number: 6762067Abstract: A method and arrangement for packaging a plurality of chip devices. The method includes providing a plurality of bottom leadframes coupled together with rails to form a bottom leadframe assembly and providing a plurality of top leadframes coupled together with rails to form a top leadframe assembly. Dies are placed between the top and bottom leadframes and the top and bottom leadframe assemblies are coupled to one another. The dies are attached to die attach pads of the bottom leadframes and are coupled to the top leadframes with solder bumps. A molded body is placed around the top and bottom leadframes with the dies therebetween and the rails are removed from the top and bottom leadframes, thus providing a plurality of chip devices.Type: GrantFiled: January 18, 2000Date of Patent: July 13, 2004Assignee: Fairchild Semiconductor CorporationInventors: Maria Clemens Y. Quinones, Gilmore S. Baje, Maria Christina B. Estacio, Marvin R. Gestole, Oliver M. Ledon, Santos E. Mepieza
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Publication number: 20040123457Abstract: By forming a terminal at a tip of a lead part of a lead frame, and by fixing this terminal and a connecting pad which was formed on an upper surface of a first printed circuit board, the lead frame is attached to the first printed circuit board. By cutting off a frame part and a tie bar part from the lead frame which was attached to the first printed circuit board, the lead part is separated, and forming is applied to the lead part so as for its tip to be extended over the first printed board. After the lead part which is expanded upward is inserted into a through-hole which was opened in a second printed circuit board, by soldering the lead part and the through-hole, the first printed circuit board and the second printed circuit board are electrically connected.Type: ApplicationFiled: October 9, 2003Publication date: July 1, 2004Applicants: FUJITSU TEN LIMITED, TOYOTA JIDOSHA KABUSHIKI KAISHAInventors: Takashi Ohta, Kazuaki Yamada, Kiyoshi Tsujii, Hidekazu Manabe
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Patent number: 6748650Abstract: A circuit assembly comprises a substrate comprising one or more conductors. An integral frame of frame elements supports the substrate. The frame elements spaced apart to expose intervening regions of the substrate between adjacent frame elements. A dielectric layer overlies the intervening regions, as a protective barrier for at least one of the conductors, a component, and a circuit feature of the substrate.Type: GrantFiled: June 27, 2001Date of Patent: June 15, 2004Assignee: Visteon Global Technologies, Inc.Inventor: Harvinder Singh
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Patent number: 6748651Abstract: This method includes punching a bus-bar pattern out of a conductive metal sheet. A bus bar terminal piece is punched out of the remaining material in the conductive metal sheet. An electrical connection is formed between the bus-bar pattern and the bus-bar terminal piece using male and female connections.Type: GrantFiled: March 28, 2001Date of Patent: June 15, 2004Assignee: The Furukawa Electric Co., Ltd.Inventors: Kazuo Miyajima, Shin Hasegawa, Yoshiaki Sawaki
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Publication number: 20040103530Abstract: A magnetic sensor is constituted using magnetic sensor chips mounted on stages supported by interconnecting members and a frame having leads in a lead frame. Herein, the stages are inclined upon plastic deformation of the interconnecting members. When the frame is held in a metal mold and the stages are pressed, the interconnecting members are elastically deformed, so that the magnetic sensor chips are bonded onto the stages placed substantially in the same plane and are then wired with the leads. Thereafter, the stages are released from pressure, so that the interconnecting members are restored from the elastically deformed states thereof. When the magnetic sensor chips are combined together to realize three sensing directions, it is possible to accurately measure three-dimensional bearings of magnetism, and the magnetic sensor can be reduced in dimensions and manufactured with a reduced cost therefor.Type: ApplicationFiled: July 28, 2003Publication date: June 3, 2004Inventors: Hiroshi Adachi, Hiroshi Saitoh, Kenichi Shirasaka, Hideki Sato, Masayoshi Omura