Assembling Bases Patents (Class 29/830)
  • Patent number: 8813324
    Abstract: A method for fabricating a piezoelectric multilayer are described. The method includes providing conductive layers. Alternating conductive layers are electrically connected. A first plurality of alternating conductive layers is electrically isolated from a second plurality of alternating conductive layers. Piezoelectric layers are interleaved with the conductive layers. Apertures are provided in the piezoelectric layers. A first conductive plug electrically connects the first plurality of alternating conductive layers, includes a first plurality of segments, and is in apertures in the piezoelectric layers. Each of the first plurality of segments extends through one of the piezoelectric layers. A second conductive plug electrically connects the second plurality of alternating conductive layers, includes a second plurality of segments, and is in a second portion of the plurality of apertures. Each of the second plurality of segments extends through one of the plurality of piezoelectric layers.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: August 26, 2014
    Assignee: Western Digital (Fremont), LLC
    Inventors: Nathan C. Emley, Donghong Li, Prakash Mani
  • Patent number: 8813353
    Abstract: A dielectric structure including a metal foil, a dielectric layer and a conductor layer provided in this order, wherein the metal foil has a thickness of from 10 to 40 ?m, the dielectric layer has a thickness of from 0.3 to 5 ?m, and the conductor layer has a thickness of from 0.3 to 10 ?m. The dielectric structure has plural vias which are separated from each other, and which penetrate through both of the dielectric layer and the conductor layer. The vias of the dielectric layer have different diameters which are in a range of from 100 to 300 ?m, a diameter of each of the vias of the conductor layer is larger than a diameter of a corresponding via of the dielectric layer by 5 to 50 ?m, and a minimum via pitch is from 100 to 350 ?m.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: August 26, 2014
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Yasuhiko Inui, Takamichi Ogawa, Seiji Ichiyanagi, Jun Otsuka, Manabu Sato
  • Patent number: 8813354
    Abstract: An electromagnetic interference (EMI) shielding structure, which includes: a substrate, at least one chip unit, a packing layer, and an EMI shielding unit. The chip unit is disposed on the surface of the substrate and electrically coupled thereto. The packing layer is formed on the substrate and covers the chip unit. The EMI shielding unit includes: a first, second, and third shielding layer. The first shielding layer covers the outer surface of the packing layer and the lateral surface of the substrate. The second and third shielding layer respectively covers the outer surface of the first and second shielding layer. Based on the instant disclosure, the EMI shielding unit uses the methods of sputtering and electroless plating, to increase the adhesion strength of the EMI shielding unit and make the thickness of the shielding layer uniform. The instant disclosure raises the EMI shielding efficiency and lowers the manufacturing cost.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: August 26, 2014
    Assignees: Universal Scientific Industrial (Shanghai) Co., Ltd., Universal Global Scientific Industrial Co., Ltd.
    Inventor: Ming-Che Wu
  • Patent number: 8814954
    Abstract: The method for manufacturing products having a metal surface by imparting microfeatures onto the metal surface. The method if further described as the steps of: creating a transfer tool from a microstructured intermediate fabricated from a microstructured prototype having microfeatures; and, transferring the microfeatures to said metal surface using the transfer tool.
    Type: Grant
    Filed: August 26, 2010
    Date of Patent: August 26, 2014
    Assignee: Hoowaki, LLC
    Inventors: Ralph A. Hulseman, David Mammarella, Andrew H. Cannon, William P. King
  • Patent number: 8800138
    Abstract: A method for forming an electronic device on a flexible substrate conditions a surface of the flexible substrate to increase its malleability and to provide a conditioned substrate surface. A master surface is impressed against the conditioned substrate surface. The master surface is then released from the conditioned substrate surface, thereby forming a circuit-side surface on the substrate. The electronic device is then formed on the circuit-side surface. The substrate may be supported on a carrier during the method.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: August 12, 2014
    Assignee: Carestream Health, Inc.
    Inventors: Timothy J. Tredwell, Roger S. Kerr
  • Publication number: 20140218869
    Abstract: A heat radiation structure for an electric device includes: at least one multi-layer substrate including a plurality of base parts made of insulation material and a conductor pattern, which are stacked in a multi-layer structure so that the conductor pattern is electrically coupled with an interlayer connection portion in the base parts; the electric device having at least one of a first electric element built in the at least one multi-layer substrate and a second electric element, which is not built in the multi-layer substrate; and a low heat resistance element opposed to the electric device. The low heat resistance element has a heat resistance lower than the insulation material.
    Type: Application
    Filed: January 29, 2014
    Publication date: August 7, 2014
    Applicant: Denso Corporation
    Inventors: Takahiro YAMANAKA, Yoshimichi HARA, Toshihisa YAMAMOTO, Kouji KAMEYAMA, Yuuji KOBAYASHI
  • Publication number: 20140218883
    Abstract: An electronic module includes a substrate, which includes a dielectric material having multiple sides, including first and second sides, and first and second cavities indented respectively within the first and second sides. First and second conductive contacts within the first and second cavities are configured for contact with at least first and second electronic components that are mounted respectively in the first and second cavities. Conductive traces within the substrate are in electrical communication with the first and second conductive contacts.
    Type: Application
    Filed: April 13, 2014
    Publication date: August 7, 2014
    Applicant: Eagantu Ltd.
    Inventors: Michael Dakhiya, Eran Shaked
  • Publication number: 20140213077
    Abstract: A primary circuit board has a front surface, a back surface, and a non-conductive void. The void has first planar dimensions through a first portion of a thickness of the primary circuit board extending from the front surface to a position between the front and back surfaces, and second planar dimensions through a second portion of the thickness extending from the position at least towards the back surface. A secondary circuit board holder includes a non-conducting locking member insertable into the non-conductive void at the primary circuit board's front surface to secure the holder while a conductive part of the holder is conductively affixed to a conductive part of the primary circuit board. The first planar dimensions are different than the second planar dimensions to permit the primary circuit board's thickness to be greater than a maximum thickness specification of the holder's non-conducting locking member.
    Type: Application
    Filed: January 27, 2013
    Publication date: July 31, 2014
    Applicant: International Business Machines Corporation
    Inventors: Wai M. Ma, James E. Tersigni, Jefferson L. Watson
  • Patent number: 8789272
    Abstract: A test socket that provides a temporary interconnect between terminals on an integrated circuit (IC) device and contact pads on a test printed circuit board (PCB). The test socket includes a compliant printed circuit and a socket housing. The compliant printed circuit includes at least one compliant layer, a plurality of first contact members located along a first major surface, a plurality of second contact members located along a second major surface, and a plurality of conductive traces electrically coupling the first and second contact members. The compliant layer is positioned to bias the first contact members against the terminals on the IC device and the second contact members against contact pads on the test PCB. The socket housing is coupled to the compliant printed circuit so the first contact members are positioned in a recess of the socket housing sized to receive the IC device.
    Type: Grant
    Filed: May 27, 2010
    Date of Patent: July 29, 2014
    Assignee: HSIO Technologies, LLC
    Inventor: James Rathburn
  • Patent number: 8786084
    Abstract: A semiconductor package includes a semiconductor die attached to a support having electrically conductive paths, the semiconductor die having a bond-pad electrically connected to the electrically a conductive path on the support by a bond-wire of a first metallic composition, the bond-wire and the bond-pad being coated with a protection layer of a second metallic composition.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: July 22, 2014
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Jean-François Sauty
  • Patent number: 8782895
    Abstract: In a method for manufacturing a droplet ejection head, a structure of a substrate having an energy-generating element that imparts energy to a liquid to eject a liquid droplet from an ejection orifice and an orifice plate having the ejection orifice formed therein are laminated through a flow channel member for forming a pattern of a liquid flow channel that is a region in which the liquid flows. At least one of a plate before being laminated and the flow channel member before being laminated has a void of at least one of a through-hole other than the ejection orifice and a recess in the face to be laminated.
    Type: Grant
    Filed: November 10, 2011
    Date of Patent: July 22, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yoshiyuki Fukumoto
  • Patent number: 8782882
    Abstract: A method of manufacturing a printed circuit board includes the following steps (A) to (D). (A) Laminating a resin insulating layer on each of two sides of a core member to form a core substrate, (B) forming penetrating openings in the core substrate by applying laser beams, (C) forming a rough surface on the core substrate, and (D) providing a metal film for each penetrating opening to form through holes.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: July 22, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Motoo Asai, Dongdong Wang, Takahiro Mori
  • Patent number: 8776363
    Abstract: A method for supporting a semiconductor wafer includes providing a device wafer to a magnetizable ring, providing a magnetizable carrier to the device wafer, and magnetizing the magnetizable ring and the magnetizable carrier to form a magnetized clamp having a magnetized ring and magnetized carrier. The magnetized clamp securely clamps the device wafer therebetween.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: July 15, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chang-Sheng Hsu, Li-Che Chen, Kuo-Yuh Yang, Chia-Wen Lien, Yan-Da Chen
  • Patent number: 8780561
    Abstract: A method of forming a heat-dissipating structure for semiconductor circuits is provided. First and second semiconductor integrated circuit (IC) chips are provided, where the first and second semiconductor chips each have first and second opposing sides, wherein the first and second semiconductor IC chips are configured to be fixedly attached to a top surface of a substantially planar circuit board along their respective first sides. The respective second opposing sides of each of the first and second semiconductor IC chips are coupled to first and second respective portions of a sacrificial thermal spreader material, the sacrificial thermal spreader material comprising a material that is thermally conductive. The first and second portions of the sacrificial thermal spreader material are planarized to substantially equalize a respective first height of the first semiconductor chip and a respective second height of the second semiconductor chip.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: July 15, 2014
    Assignee: Raytheon Company
    Inventors: Paul A. Danello, Richard A. Stander, Michael D. Goulet
  • Patent number: 8776364
    Abstract: A multilayer ceramic component includes a stack containing ceramic layers and electrode layers interspersed among the ceramic layers. The electrode layers contain copper and define first and second internal electrodes. First and second external contacts are on different sides of the stack. The first and second external contacts contain copper and are substantially perpendicular to the ceramic layers and electrode layers. The first internal electrode is connected to the first external contact and the second internal electrode is connected to the second external contact. The first and second internal electrodes overlap each other at a plane intersecting the stack. In areas adjacent to boundaries between the first and second external contacts and the ceramic layers, the first and second external contacts are not oxidized and material making-up the ceramic layers is not diminished. A bonding strength of the external contacts to the stack exceeds 50 N.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: July 15, 2014
    Assignee: EPCOS AG
    Inventors: Heinz Florian, Marion Ottlinger, Peter Sedlmaier
  • Publication number: 20140192502
    Abstract: Disclosed are a method and system to reduce impedance of printed circuit boards through an interconnecting of printed circuit boards using a square wave pattern of plated-through holes. A method of connecting a first printed circuit board to a second printed circuit board comprises forming a square wave pattern of the first printed circuit board and the second printed circuit board and adjoining the first printed circuit board and the second printed circuit board. The method also involves producing plated-through holes along the square wave pattern, a top section, and/or a bottom section of the adjoined first printed circuit board and second printed circuit board. The method further involves securing the top section and the bottom section using a first metal clip and a second metal clip, respectively, and connecting the first printed circuit board to the second printed circuit board by a wave soldering process.
    Type: Application
    Filed: January 8, 2013
    Publication date: July 10, 2014
    Inventor: Shuang Xu
  • Patent number: 8772088
    Abstract: In a high frequency module, electronic components are mounted on a mounting surface of a collective substrate including a plurality of unit substrates that include a via conductor electrically conducted to a ground potential in a peripheral portion thereof, and the mounting surface and the electronic components are encapsulated with an encapsulation layer. The collective substrate is cut on the encapsulation layer side, thereby forming a half-cut groove penetrating through the encapsulation layer and extending halfway along the collective substrate in a thickness direction such that the via conductor is exposed only at a bottom surface of the half-cut groove. A conductive shield layer is formed to cover the encapsulation layer and is electrically conducted to the exposed via conductor. The collective substrate is then cut into individual unit substrates each including the conductive shield layer electrically conducted to the ground potential through the via conductor.
    Type: Grant
    Filed: February 7, 2012
    Date of Patent: July 8, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventor: Takayuki Horibe
  • Patent number: 8763241
    Abstract: A method for manufacturing a printed circuit board including providing a first resin substrate having a resin plate and a circuit pattern formed on a surface of the resin plate, providing a second resin substrate having a resin plate and an accommodation portion formed in the resin plate of the second substrate, connecting an electrode of a capacitor to the circuit pattern of the first substrate with a bonding material such that the capacitor is mounted to the first substrate, attaching the second substrate to the resin substrate through a bonding resin layer such that the capacitor on the first substrate is accommodated in the accommodation portion of the second substrate, and forming a via hole in the first substrate such that the via hole is electrically connected to the electrode of the capacitor in the accommodation portion of the second substrate.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: July 1, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
  • Patent number: 8763242
    Abstract: In a method of manufacturing a semiconductor device, a second wiring substrate is stacked over a first wiring substrate using a conductive paste, where each wiring substrate has mounted thereon an electronic component. The conductive paste is hardened to form a metal column which forms an electrical connection between the first wiring substrate and the second wiring substrate. The wiring substrates are sealed with a resin. The semiconductor device can be downsized, thinned, and made highly reliable, and its manufacturing cost can be reduced. By using conductive paste for the electrical connection between the wiring substrates, a connecting pitch can be smaller than that in a connecting method of using a solder ball including Cu core, and a connection at low temperature can be achieved. Also, by coating the conductive paste by a print-coating or dispense-coating method, manufacturing is simplified and the manufacturing cost is reduced.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: July 1, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Kenya Kawano, Chiko Yorita, Yuji Shirai
  • Patent number: 8766107
    Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.
    Type: Grant
    Filed: April 13, 2012
    Date of Patent: July 1, 2014
    Assignee: International Business Machines Corporation
    Inventors: Moises Cases, Tae Hong Kim, Rohan U. Mandrekar, Nusrat I. Sherali
  • Patent number: 8763244
    Abstract: There is disclosed a method of forming a patterned conductive element for an implantable medical device, the method comprising the steps of: depositing a supplementary material on a sheet of conductive, parent material to form a sheet of composite material; applying a carrier material over the supplementary material of the composite sheet to form a sheet of semi-finished material; removing portions from at least the conductive parent material of the sheet of semi-finished material in accordance with a desired pattern corresponding to a patterned conductive element to be formed; and releasing at least the carrier material from the sheet of semi-finished material.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: July 1, 2014
    Assignee: Cochlear Limited
    Inventor: Peter Schuller
  • Patent number: 8763240
    Abstract: A fabricating process for a multi-layer printed circuit board containing embedded passive components is provided. The method includes a calibration step wherein a calibration measurement is taken of the geometry or at least one electrical parameter of an arrangement of calibration test points for a circuit forming process, such as masking, etching and/or lamination. A process control step is performed during the process, wherein a process control measurement is taken of at least one electrical parameter at one or more process control test points along one or more axes outside areas in which a circuit is to be formed. An analysis is performed of at least the calibration measurement and the process control measurement to calculate a CAD geometry change required to improve precision of embedded passive components to be printed on the multi-layer printed circuit board.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: July 1, 2014
    Assignee: TFRI, Inc.
    Inventors: Lendon L. Bendix, Derek A. Turner
  • Publication number: 20140177180
    Abstract: Electrical components in an electronic device are mounted on substrates such as printed circuits. Printed circuits contain signal paths formed from metal traces. The signal lines in the signal paths of the printed circuits are coupled together using electrical connection structures such as printed circuit board-to-board connectors, contacts joined by anisotropic conductive film, or contacts joined using solder. Electrical connection structures may be surrounded by conductive resilient ring-shaped structures such as conductive foam structures or spring structures. The conductive foam structures may be provided with a metal layer with which the conductive foam structures are soldered to a ring of metal on a printed circuit. Strain relief structures may be formed from an elastomeric ring that surrounds the electrical connection structures or an overmolded plastic structure.
    Type: Application
    Filed: December 24, 2012
    Publication date: June 26, 2014
    Applicant: Apple Inc.
    Inventors: Shayan Malek, Michael B. Wittenberg, Sawyer I. Cohen, Ashutosh Y. Shukla
  • Patent number: 8756803
    Abstract: A method for manufacturing a printed wiring board including forming an insulative resin layer containing a resin and an inorganic filler, forming a conductor layer including a conductive material and having a conductor on the insulative resin layer, irradiating a laser beam upon the conductor of the conductor layer such that the conductor is sectioned or a width of the conductor is narrowed, and forming a conductive pattern on the insulative resin layer. The inorganic filler is in an amount of 30 wt. % or more of the insulative resin layer.
    Type: Grant
    Filed: July 1, 2011
    Date of Patent: June 24, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Toru Nakai, Tetsuo Amano, Yoshinori Takasaki
  • Publication number: 20140170866
    Abstract: An improved electrical connector retainer employs a shell having a cavity. A pair of mated electrical connectors are received within the cavity and at least a portion of an upper wall of the shell is deflected towards a lower wall of the shell. The shell is configured to retain the upper wall in the deflected position, maintaining the pair of connectors in the mated position.
    Type: Application
    Filed: December 18, 2012
    Publication date: June 19, 2014
    Applicant: Apple Inc.
    Inventors: Derek W. Wright, Alex Yeung, Steve McClure, Sean S. Corbin, John B. Ardisana, II, Benjamin J. Pope, Shayan Malek
  • Publication number: 20140172057
    Abstract: An electrical stimulation lead includes a paddle body with micro-circuit assemblies having micro-circuits laminated between electrically-nonconductive substrates. The micro-circuits have first end portions and opposing second end portions. Electrodes are electrically coupled to the first end portions of the micro-circuits. Distal end portions of one or more lead bodies are coupled to the paddle body. Terminals are disposed along proximal end portions of the one or more lead bodies. Lead-body conductors are coupled to the terminals and extend along the one or more lead bodies to distal end portions of the one or more lead bodies. The lead-body conductors are attached to the second end portions of the micro-circuits to electrically couple the terminals to the electrodes.
    Type: Application
    Filed: December 10, 2013
    Publication date: June 19, 2014
    Applicant: BOSTON SCIENTIFIC NEUROMODULATION CORPORATION
    Inventor: William George Orinski
  • Publication number: 20140170865
    Abstract: A substantially cable-free board connection assembly may include a plurality of printed circuit boards (PCBs) forming an interconnect plane for a plurality of electronic devices respectively attached to a plurality of plane boards included in the interconnect plane. An insertion direction for substantially all connectors is substantially perpendicular to a face of the interconnect plane. At least a portion of the board connection assembly is mounted to a support structure via a flexible connection.
    Type: Application
    Filed: December 17, 2012
    Publication date: June 19, 2014
    Applicant: MICROSOFT CORPORATION
    Inventors: Eric C. Peterson, David T. Harper, III
  • Patent number: 8752283
    Abstract: A method for operating an assembly tool includes deposing a first component on an assembly surface with a first tool tip of a manipulator having a range of motion defined by a plane and an axis that is substantially normal to the plane, deposing a second component on the assembly surface, changing an orientation of the assembly surface relative to the axis from a first orientation to a second orientation, lifting the first component from the assembly surface with a second tool tip of the manipulator, and deposing the first component on the second component.
    Type: Grant
    Filed: June 1, 2012
    Date of Patent: June 17, 2014
    Assignee: International Business Machines Corporation
    Inventors: Tymon Barwicz, Bing Dang
  • Patent number: 8754337
    Abstract: An object of the invention is to provide a method for fabricating a printed wiring board that can suppress warping of the printed wiring board and can improve the yield of semiconductor chip mounting and enhance the reliability of a semiconductor package. The printed wiring board fabrication method according to the invention is a method for fabricating a printed wiring board having a through-hole in a core layer, wherein the printed wiring board fabrication method includes the step of applying a laser from one side of the core layer to a position where the through-hole is to be formed in the core layer and the step of applying a laser to the same position from the opposite side of the core layer.
    Type: Grant
    Filed: March 26, 2010
    Date of Patent: June 17, 2014
    Assignee: Sumitomo Bakelite Co., Ltd.
    Inventor: Kenichi Kaneda
  • Publication number: 20140158408
    Abstract: A multi-layer wiring board comprises: a plurality of multi-layer wiring units each having a plurality of printed wiring boards stacked therein via an adhesive layer, the printed wiring board having a wiring layer formed on an insulating base therein and having flexibility, and the wiring layers being connected to each other via a via that penetrates in a stacking direction; and a cable unit connecting between the plurality of multi-layer wiring units and having flexibility, the cable unit configured having a lower insulating base, the wiring layer formed on the lower insulating base and an upper insulating base disposed above the lower insulating base via the adhesive layer, the lower insulating base and the wiring layer correspond to one-layer of the printed wiring board, and the lower and upper insulating bases and the wiring layer being led out from the multi-layer wiring units.
    Type: Application
    Filed: December 9, 2013
    Publication date: June 12, 2014
    Applicant: FUJIKURA LTD.
    Inventor: Kumi Onodera
  • Publication number: 20140159226
    Abstract: Various embodiments of a compact sensor module are disclosed herein. The sensor module can include a stiffener and a sensor substrate having a mounting segment and a first wing segment extending from the mounting segment. The first wing segment may be folded around an edge of the stiffener. A sensor die may be mounted on the mounting segment of the sensor substrate. A processor substrate may be coupled to the sensor substrate. A processor die may be mounted on the processor substrate and may be in electrical communication with the sensor die.
    Type: Application
    Filed: December 7, 2012
    Publication date: June 12, 2014
    Applicant: ANALOG DEVICES, INC.
    Inventor: David Bolognia
  • Patent number: 8745841
    Abstract: There is provided an aluminum bonding member capable of being simply and inexpensively produced and capable of being used as a cooling member having a high cooling power. The aluminum bonding member 10 has an aluminum member 12 of aluminum or an aluminum alloy exposed to the outside, and a tubular member 14 of a material which does not melt at a temperature close to the melting point of aluminum or the aluminum alloy. Both of the opening end portions of the tubular member 14 are open to the outside of the aluminum member 12. A portion of the tubular member 14 between the opening end portions extends in the aluminum member 12, and the outer peripheral surface of the portion of the tubular member 14 extending in the aluminum member 12 is bonded directly to the aluminum member 12.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: June 10, 2014
    Assignee: Dowa Metaltech Co., Ltd.
    Inventor: Hideyo Osanai
  • Patent number: 8745860
    Abstract: A method for manufacturing a printed wiring board includes forming on a support board a first resin insulation layer, forming a second resin insulation layer on the first resin insulation layer, forming in the second resin insulation layer an opening portion in which an electronic component having an electrode is mounted, accommodating the electronic component in the opening portion of the second resin insulation layer such that the electrode of the electronic component faces an opposite side of the first resin insulation layer, forming on the first surface of the second resin insulation layer and the electronic component an interlayer resin insulation layer, and forming in the interlayer resin insulation layer a via conductor reaching to the electrode of the electronic component.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: June 10, 2014
    Assignee: Ibiden Co., Ltd.
    Inventor: Tsuyoshi Inui
  • Patent number: 8745863
    Abstract: A method of manufacturing a multi-layer printed circuit board includes the following steps (A) and (B). (A) Providing penetrating openings which are formed into through holes and each of which has a small diameter for a core substrate, and (B) providing penetrating openings which are formed into through holes each having a large diameter for the core substrate.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: June 10, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Motoo Asai, Dongdong Wang, Takahiro Mori
  • Publication number: 20140153206
    Abstract: Embodiments relate to active devices embedded within printed circuit boards (PCBs). In embodiments, the active devices can comprise at least one die, such as a semiconductor die, and coupling elements for mechanically and electrically coupling the active device with one or more layers of the PCB in which the device is embedded. Embodiments thereby provide easy embedding of active devices in PCBs and inexpensive integration with existing PCB technologies and processes.
    Type: Application
    Filed: November 30, 2012
    Publication date: June 5, 2014
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Martin Standing, Andrew Roberts
  • Publication number: 20140150253
    Abstract: A touch screen comprises a first substrate, a second substrate and a third substrate sequentially stacked. A first sensing layer is provided on a first surface of the second substrate opposing to the third substrate, and a second sensing layer is provided on a surface of the third substrate opposing to the second substrate. The second substrate provided with the first sensing layer and the third substrate provided with the second sensing layer constitute a touch unit for sensing a touch signal, and the second substrate and the first substrate constitute a display unit for displaying.
    Type: Application
    Filed: November 26, 2013
    Publication date: June 5, 2014
    Applicant: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Yun Sik IM, Yao YU
  • Patent number: 8739402
    Abstract: A method of manufacture of an electrical bridge including the following steps: (a) providing a first flexible electrically insulating material, (b) laminating a pattern of a second electrically conductive material, on the first material, (c) separating a strap having a connection portion formed from the pattern of electrically conductive material.
    Type: Grant
    Filed: December 17, 2008
    Date of Patent: June 3, 2014
    Assignee: Microconnections SAS
    Inventors: Jean Pierre Radenne, Christophe Mathieu, Laurent Berdalle
  • Patent number: 8739399
    Abstract: A method of making an electronic storage system includes receiving a substrate and a circuit template. A transceiver including a transceiver substrate separate from the substrate is disposed over the substrate. The transceiver includes an output electrical-connection pad, and a plurality of input electrical-connection pads. A circuit template is disposed over the substrate so that at least one of the conductors of the circuit template is electrically connected to the output pad and at least one of the conductors of the circuit template is electrically connected to each of the input pads. At least one electrically-conductive strap is printed over the substrate so that each strap electrically connects the output pad to the at least one of the input pads through at least two of the conductors of the circuit template.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: June 3, 2014
    Assignee: Eastman Kodak Company
    Inventors: Ronald Steven Cok, Christopher Lyons
  • Patent number: 8732942
    Abstract: In some embodiments a high speed interconnect includes a layer of FR4 material, a trench in the layer of FR4 material, and a pair of transmission lines located near the trench. The trench is filled with a homogenous material. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: May 27, 2014
    Assignee: Intel Corporation
    Inventors: Stephen H. Hall, Bryce D. Horine, Gary A. Brist, Howard Heck
  • Publication number: 20140138635
    Abstract: A stretchable organic light-emitting display device includes a stretchable base plate including a stretchable substrate, first metal electrodes that are separated from each other and located in a plurality of rows on a the stretchable substrate, and first power wirings electrically coupling respective ones of the metal electrodes of each row, a light-emitting layer on the stretchable base plate, second metal electrodes located in a plurality of rows on the light-emitting layer and corresponding to the first metal electrodes, second power wirings for electrically coupling respective ones of the second metal electrodes of each row, and an encapsulation substrate covering the second power wiring.
    Type: Application
    Filed: March 14, 2013
    Publication date: May 22, 2014
    Applicant: SAMSUNG DISPLAY CO., LTD.
    Inventors: Chang-Hoon Lee, Jong-Ho Hong, Won-Sang Park, Jong-In Baek
  • Patent number: 8729397
    Abstract: An embedded structure of circuit board is provided. The embedded structure includes a substrate, a first patterned conductive layer disposed on the substrate and selectively exposing the substrate, a first dielectric layer covering the first patterned conductive layer and the substrate, a pad opening disposed in the first dielectric layer, and a via disposed in the pad opening and exposing the first patterned conductive layer, wherein the outer surface of the first dielectric layer has a substantially even surface.
    Type: Grant
    Filed: December 13, 2011
    Date of Patent: May 20, 2014
    Assignee: Unimicron Technology Corp.
    Inventors: Yi-Chun Liu, Wei-Ming Cheng, Tsung-Yuan Chen, Shu-Sheng Chiang
  • Patent number: 8726488
    Abstract: A handheld computing device and handheld music player are disclosed. The handheld computing device includes a seamless enclosure formed from an extruded tube. The extruded tube includes open ends and internal rails which serve as a guide for slidably assembling an operational assembly through the open ends of the extruded tube, a reference surface for positioning the operational assembly relative to an access opening in the seamless enclosure, and a support structure for supporting the operational assembly during use. The handheld music player includes an elongated extruded tube extending along a longitudinal axis. The elongated extruded tube has a first open end and a second open end opposite the first open end, and defines an internal lumen which is sized and dimensioned for slidable receipt of operational components of the handheld music player. The lumen includes rails for guiding the operational components to their desired position within the lumen.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: May 20, 2014
    Assignee: Apple Inc.
    Inventors: Stephen Paul Zadesky, Stephen Brian Lynch
  • Patent number: 8720049
    Abstract: Disclosed herein is a method for fabricating a printed circuit board, including: stacking a second insulating layer including a reinforcement on an outer surface of a first insulating layer having a post via formed thereon; polishing an upper surface of the second insulating layer to expose an upper side of the post via; stacking a film member on the second insulating layer to cover the post via and compress the second insulating layer; polishing an upper surface of the film member to expose an upper side of the post via; and forming a circuit layer connected to the post via on the upper surface of the film member.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: May 13, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd
    Inventors: Tae Kyun Bae, Chang Gun Oh, Ho Sik Park
  • Patent number: 8720048
    Abstract: A method of manufacturing a printed circuit board includes arranging a core layer in which a bending prevention portion of at least two layers that are metal layers having different thermal expansion coefficients is disposed between a plurality of insulating members; forming a circuit pattern so as to have a desired pattern on at least one of the inside of the core layer and an outer face of the core layer; and forming an insulating layer including an opening portion that exposes the circuit pattern on the core layer.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: May 13, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Mi Sun Hwang, Jae Joon Lee, Myung Sam Kang
  • Publication number: 20140127915
    Abstract: A method and apparatus are provided for implementing electrical connection of two large circuit cards through multiple discrete land grid array (LGA) sites. Each of the circuit cards includes a plurality of LGA sites. A first circuit card includes a plurality of LGA interposers locally aligned at the respective LGA sites of the first circuit card. A board-to-board connection hardware assembly connecting a second circuit card to the first circuit card includes a elongated carrier defining a cavity receiving a plurality of load springs coupled to an associated bearing block for loading and maintaining flatness of the LGA sites.
    Type: Application
    Filed: June 23, 2010
    Publication date: May 8, 2014
    Applicant: International Business Machines Corporation
    Inventors: Terry F. Banitt, John L. Colbert, Jason R. Eagle, Roger S. Krabbenhoft
  • Patent number: 8717753
    Abstract: A latching device for latching a storage device module into a storage chassis is provided. The latching device includes a latch member having a latching end and a spring end opposite the latching end, the latch member slidingly disposed within a front bezel of the storage device module and being movable between a latching position and a releasing position. The latching device also includes a latch spring between a bearing surface of the front bezel and the spring end of the latch member. The latch spring is in increased compression when the latch member transitions from the latching position to the releasing position, and the latch spring is in decreased compression when the latch member transitions from the releasing position to the latching position. The latching end extends through a latch hole in a side member of the storage chassis for locking the storage device module in the chassis.
    Type: Grant
    Filed: January 11, 2012
    Date of Patent: May 6, 2014
    Assignee: Dot Hill Systems Corporation
    Inventors: David Michael Keffeler, Andrew Rudolph Heyd
  • Patent number: 8713769
    Abstract: A novel method for manufacturing embedded a capacitive stack and a novel capacitive stack apparatus are provided having a capacitive core that serves as a structural substrate on which alternating thin conductive foils and nanopowder-loaded dielectric layers may be added and tested for reliability. This layering and testing allows early fault detection of the thin dielectric layers of the capacitive stack. The capacitive stack may be configured to supply multiple isolated capacitive elements that provide segregated, device-specific decoupling capacitance to one or more electrical components. The capacitive stack may serve as a core substrate on which a plurality of additional signaling layers of a multilayer circuit board may be coupled.
    Type: Grant
    Filed: March 10, 2008
    Date of Patent: May 6, 2014
    Assignee: Sanmina-Sci Corporation
    Inventor: George Dudnikov
  • Publication number: 20140119688
    Abstract: A circuit board, a manufacturing method thereof, and an electro-optic apparatus having the circuit board are provided. The circuit board includes a substrate including a first dielectric layer and a first circuit layer disposed thereon, a waveguide layer disposed on a portion of the substrate, a second dielectric layer, a convex structure and a second circuit layer. The second dielectric layer is disposed on the substrate and the waveguide layer. The second dielectric layer has an opening exposing the sidewall of the waveguide layer and a portion of the first circuit layer. The convex structure is disposed on the sidewall of the waveguide layer. The convex structure and the waveguide layer respectively have refractive index n1 and n2, and |n1-n21|n1<1%. The surface roughness of the convex structure is less than that of the sidewall of the waveguide layer. The second circuit layer is disposed on the second dielectric layer.
    Type: Application
    Filed: February 26, 2013
    Publication date: May 1, 2014
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventors: Pei-Chang Huang, Wen-Fang Liu, Cheng-Po Yu
  • Patent number: 8710375
    Abstract: The present invention provides a display device substrate that enables microfabrication of lines and is capable of reducing faulty connection and enhancing the reliability of display devices including the display device substrate, a method for producing the display device substrate, a display device, a method for forming a multilayer wiring structure, and a multilayer wiring board. The display substrate of the present invention includes an insulating substrate and includes at least one of a terminal area having a connection terminal to be connected to an external connection component and a peripheral circuit region having a peripheral circuit formed thereon, on the insulating substrate. The display device substrate includes an organic insulating film and an inorganic insulating film, and the inorganic insulating film is stacked directly on and above the organic insulating film such that an organic-inorganic film stacked body is formed.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: April 29, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hiroyuki Moriwaki
  • Patent number: 8707551
    Abstract: This invention is directed to bendable circuit substrate structures useful for LED mounting and interconnection.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: April 29, 2014
    Assignee: E.I. du Pont de Nemours and Company
    Inventors: Daniel I. Amey, Deborah R. Gravely, Michael J. Green, Steven H. White