Assembling Bases Patents (Class 29/830)
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Patent number: 8850695Abstract: Printed circuit board (PCB) assembly tooling and methods are provided. Particular tooling includes a first tooling fixture having a first core component receiver to receive a first portion of a magnetic core to be coupled to a first side of a PCB. The tooling also has a second tooling fixture including a second core component receiver to receive a second portion of the magnetic core to be coupled on a second side of the PCB to the first portion of the magnetic core. The tooling also has an alignment component disposed on at least one of the first tooling fixture and the second tooling fixture. The alignment component enables alignment of the first tooling fixture and the second tooling fixture. When the first tooling fixture and the second tooling fixture are aligned, the first portion of the magnetic core and the second portion of the magnetic core are aligned.Type: GrantFiled: January 5, 2010Date of Patent: October 7, 2014Assignee: The Boeing CompanyInventors: Norman L. Call, Jose M. Chavez, Rodolfo Chavez
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Publication number: 20140290052Abstract: An apparatus for connecting two or more circuit boards, the apparatus comprising: a first circuit board comprising a first surface and a second surface, the second surface having a first conductive pad; a second circuit board comprising a third surface and a fourth surface, the third surface having a second conductive pad; a fixing means configured to engage with the first circuit board and the second circuit board to couple the first circuit board to the second circuit board, wherein, when coupled, the fixing means is electrically isolated from one of the first circuit board and the second circuit board; and an electrically conductive spacer configured to electrically couple the first conductive pad and the second conductive pad.Type: ApplicationFiled: March 28, 2014Publication date: October 2, 2014Applicant: Control Techniques LimitedInventors: Dnyaneshwar Prabhakarrao Bujade, Sarang Sharad GHODKE, Dilesh Arvind Raut
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Patent number: 8844126Abstract: Electrical resistance between a male part and a female part through a canted spring is disclosed using mathematical modeling. Increase or decrease in resistance can be quickly analyzed by looking at the equivalence resistance and the number of contacts at the input side, the output side, or both. The number of contacts may also be created by forming a dimple having a discontinuity.Type: GrantFiled: December 9, 2011Date of Patent: September 30, 2014Assignee: Bal Seal Engineering, Inc.Inventors: Jeff Frederick, Steve Rust
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Patent number: 8844123Abstract: A method of manufacturing a hollow surface mount type electronic component has a preparing step, a gluing step and a cutting step. The preparing step includes preparing a baseboard, a clapboard and a cover board, mounting multiple circuit segments and conducting points on two opposite faces of the baseboard at intervals and boring multiple through holes on the clapboard corresponding to the circuit segments. The gluing step includes mounting multiple electronic elements on the baseboard to connected with the circuit segments, gelatinizing glue on the boards to mount the clapboard between the baseboard and the cover board and pressing the boards by a pressing machine. The cutting step includes cutting the boards by a cutting machine to produce multiple single SDM electronic components.Type: GrantFiled: December 3, 2009Date of Patent: September 30, 2014Inventor: Chin-Chi Yang
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Patent number: 8839520Abstract: A method of manufacturing a device that has a semiconductor element includes: forming a first wiring on a first surface of a first member; forming a second wiring on a second surface of a second member with a gap from a connection terminal and a third wiring on an inclined plane of the second member, the second member being disposed on the first member so that the first and second surfaces face in the same direction, the third wiring being aligned with, and connecting, the first and second wirings; disposing the semiconductor element on the first or second surface; and providing plating that electrically connects the first, second and third wiring with the connection terminal, wherein the connection terminal faces the second wiring, and the plating is provided in the gap between the connection terminal and the second wiring.Type: GrantFiled: July 27, 2010Date of Patent: September 23, 2014Assignee: Seiko Epson CorporationInventor: Tsuyoshi Yoda
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Patent number: 8839508Abstract: A fabrication method for a low-cost high-frequency electronic device package having waveguide structures formed from the high frequency device to the package lead transition. The package lead transition is optimized to take advantage of waveguide interconnect structure.Type: GrantFiled: November 30, 2011Date of Patent: September 23, 2014Assignee: Rosenberger Hochfrequenztechnick GmbH & Co. KGInventors: Eric A. Sanjuan, Sean S. Cahill
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Publication number: 20140268606Abstract: A package of an environmentally sensitive electronic device and a fabricating method thereof are provided, wherein the package may include a first substrate, a second substrate, the environmentally sensitive electronic device, a packaging body, and a filler. In one or more embodiments, the environmentally sensitive electronic device may be disposed on the first substrate and located between the first substrate and the second substrate. The filler is disposed between the first substrate and the second substrate and covers the environmentally sensitive electronic device. The packaging body is sandwiched between the first substrate and the second substrate and encloses the environmentally sensitive electronic device and the filler. A material for the packaging body may include a bonding of transition metal and metalloid.Type: ApplicationFiled: February 27, 2014Publication date: September 18, 2014Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventor: Kuang-Jung CHEN
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Publication number: 20140268574Abstract: A component built-in board comprises stacked therein a plurality of printed wiring bases having a wiring pattern and a via formed on/in a resin base thereof, and comprises an electronic component built in thereto, wherein at least a portion of the plurality of printed wiring bases include a thermal wiring in the wiring pattern and include a thermal via in the via, at least one of the plurality of printed wiring bases has formed therein an opening where the electronic component is built, and has formed therein a heat-conducting layer and closely attached to a surface on an opposite side to an electrode formation surface of the electronic component built in to the opening, and the electronic component is fixed in the opening by an adhesive layer stacked on the heat-conducting layer, via a hole formed in a region facing onto the opening of the heat-conducting layer.Type: ApplicationFiled: May 29, 2014Publication date: September 18, 2014Applicant: FUJIKURA LTD.Inventors: Kazuhisa Itoi, Masahiro Okamoto
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Patent number: 8836509Abstract: A security device for protecting stored sensitive data includes a closed housing including an array of conductor paths and tamper detecting means adapted to detect a change in impedance of the array of conductor paths above a predetermined threshold value.Type: GrantFiled: April 9, 2010Date of Patent: September 16, 2014Assignee: Direct Payment Solutions LimitedInventor: Jonathan David Lowy
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Patent number: 8832932Abstract: A printed circuit board assembly (PCBA) includes a printed circuit board (PCB) with through holes, a supporting member standing on the PCB adjacent to the through holes, and an electronic component mounted on the PCB is provided. The electronic component includes a component body and a plurality of conductive leads. Fixing ends of the conductive leads of the electronic component is received in the though hole and electrically and mechanically fixed to the PCB. The component body of the electronic component is supported by the supporting member.Type: GrantFiled: November 29, 2011Date of Patent: September 16, 2014Assignees: Hong Fu Jin Precision Industry (ShenZhen) Co., Ltd., Hon Hai Precision Industry Co., Ltd.Inventors: Xiao-Hui Zhou, Hong Li, Ping Li, Rui Li
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Patent number: 8832929Abstract: A method of manufacturing a flexible printed circuit board including determining an elastic modulus of a conductive portion and an elastic modulus of first and second dielectric portions, determining a thickness of the conductive portion and the first and second dielectric portions so that a neutral plane is located within a predetermined range of the thickness of the conductive portion, the neutral plane being substantially free from tension or compression in response to bending of the flexible printed circuit board, and insulating the conductive portion according to the determined thickness and the determined elastic modulus.Type: GrantFiled: May 16, 2012Date of Patent: September 16, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Kyung Ho Lee, Se Min Oh, Chang Hwan Choi, Choon Keun Lee, Jeong Yeol Moon, Jong Rip Kim
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Patent number: 8832935Abstract: A method for manufacturing a printed wiring board including providing a structure having a wiring substrate having a conductor circuit, a build-up multilayer structure formed over the wiring substrate and having an outermost conductor circuit and an outermost insulative resin layer, and a solder resist layer formed over the outermost conductor circuit and outermost insulative resin layer and having openings with an opening diameter D for mounting electronic elements, forming conductor pads with a pitch of about 200 pm or less on the outermost conductor circuit in the openings of the solder resist layer, respectively, and forming solder bumps with a height H from a surface of the solder resist layer on the conductor pads on the conductor pads, respectively, such that a ratio H/D is about 0.55 to about 1.0.Type: GrantFiled: November 23, 2010Date of Patent: September 16, 2014Assignee: Ibiden Co., Ltd.Inventors: Yoichiro Kawamura, Shigeki Sawa, Katsuhiko Tanno, Hironori Tanaka, Naoaki Fujii
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Patent number: 8832930Abstract: A touchscreen panel includes an upper substrate having a first transparent conductor layer provided on a first base layer, and a lower substrate having a second transparent conductor layer provided on a second base layer. The first and second transparent conductor layers oppose each other via a spacer and make contact when the first base layer is pressed. The first transparent conductor layer is segmented into a plurality of conductive regions that are electrically insulated from each other.Type: GrantFiled: October 22, 2013Date of Patent: September 16, 2014Assignee: Fujitsu Component LimitedInventors: Koichi Kondoh, Takashi Nakajima, Nobuyoshi Shimizu, Masanobu Hayama, Norio Endo
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Patent number: 8837141Abstract: An electronic module comprises: a multilayer circuit board having a bifurcated area along one edge and a plurality of electronic components mounted on at least one surface; a plurality of electrode pads functionally connected to the electronic components and positioned on the inner surfaces of the bifurcated area so that when the two legs of the bifurcated area are spread apart by about 180° the electrode pads align with respective contacts on a motherboard, and are connectable thereto, so that a secure connection may be created between the circuit board and the motherboard; and, two metal, heat spreading covers lockably enclosing the circuit board, one on either side, the covers further providing mating surfaces upon which a mechanical clamping device can engage and secure the module to a motherboard.Type: GrantFiled: October 17, 2012Date of Patent: September 16, 2014Assignee: Microelectronics Assembly TechnologiesInventors: James E. Clayton, Zakaryae Fathi
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Patent number: 8826531Abstract: A method for making an integrated circuit substrate having laminated laser-embedded circuit layers provides a multi-layer high-density mounting and interconnect structure for integrated circuits. A prepared substrate, which may be a rigid double-sided dielectric or film dielectric with conductive patterns plated, etched or printed on one or both sides is laminated with a thin-film dielectric on one or both sides. The thin-film is laser-ablated to form channels and via apertures and conductive material is plated or paste screened into the channels and apertures, forming a conductive interconnect pattern that is isolated by the channel sides and vias through to the conductive patterns on the prepared substrate. An integrated circuit die and external terminals can then be attached to the substrate, providing an integrated circuit having a high-density interconnect.Type: GrantFiled: April 5, 2005Date of Patent: September 9, 2014Inventors: David Jon Hiner, Ronald Patrick Huemoeller, Sukianto Rusli
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Patent number: 8826526Abstract: A method of manufacturing a multilayer wiring substrate is provided. A foil of a metal-foil-clad resin insulation material is brought into contact with a foil of a metal-foil-clad support substrate. A peripheral edge portion of the resin insulation material exposed as a result of removal of a peripheral edge portion of the foil is adhered to the foil of the support substrate. A plurality of conductor layers and a plurality of resin insulation layers are laminated so as to obtain a laminate structure having a wiring laminate portion, which is to become the multilayer wiring substrate. The laminate structure is cut along a boundary between the wiring laminate portion and a surrounding portion, and the surrounding portion is removed. The wiring laminate portion is separated from the support substrate along the boundary between the two foils.Type: GrantFiled: October 26, 2011Date of Patent: September 9, 2014Assignee: NGK Spark Plug Co., Ltd.Inventor: Shinnosuke Maeda
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Patent number: 8831918Abstract: The present invention relates to a pin-less registration and inductive heating system involving the use of a pre-alignment station for imaging an initial position of a laminate element, an imaging and computer operation control system for determining a required correction factor between an alignment of the laminate element at the pre-alignment station and a preferred stack orientation for the laminate element, and an alignment and transfer system for securely gripping, transferring, and repositioning a laminate element from atop position to the preferred stack orientation employing a preferred four-axis orientation.Type: GrantFiled: October 7, 2013Date of Patent: September 9, 2014Assignee: Duetto Integrated Systems, Inc.Inventors: Anthony Faraci, Gary N. Sortino
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Patent number: 8819931Abstract: A printed circuit board is fabricated so contacts for tight-pitch components are at an angle with respect to the bundles of glass fibers in the epoxy-glass printed circuit board such that adjacent component contacts do not contact the same bundle of glass fibers. This angle may be accomplished by manufacturing a printed circuit board panel with the glass fibers at an angle with respect to its edges. This angle may also be accomplished by placing parts on a printed circuit board panel that has a traditional X-Y orthogonal weave of glass fiber bundles at an angle with respect to the edges of the panel. This angle may also be accomplished by starting with a traditional panel that has an X-Y orthogonal weave, laying out parts on the panel along the X-Y weave, then placing components on the parts at an angle with respect to the edges of the parts.Type: GrantFiled: July 15, 2008Date of Patent: September 2, 2014Assignee: International Business Machines CorporationInventors: Bruce John Chamberlin, Mitchell G. Ferrill, Roger Scott Krabbenhoft
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Patent number: 8819932Abstract: A method of manufacturing a ceramic electronic component prevents variations in characteristics even when the ceramic electronic component is embedded in a wiring board. Ceramic green sheets containing an organic binder having a degree of polymerization in a range from about 1000 to about 1500 are prepared. A first conductive paste layer is formed on a surface of each of the ceramic green sheets. The ceramic green sheets are laminated to form a raw ceramic laminated body. A second conductive paste layer is formed on a surface of the raw ceramic laminated body. The raw ceramic laminated body formed with the second conductive paste layer is fired.Type: GrantFiled: July 18, 2011Date of Patent: September 2, 2014Assignee: Murata Manufacturing Co., Ltd.Inventors: Koji Sato, Yukio Sanada, Yasuhiro Nishisaka
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Publication number: 20140238724Abstract: A method of fabricating components for a three-dimensional circuit structure includes providing a printed circuit board (PCB) having a top surface, an opposing bottom surface, and an end section. A first angled channel is formed in the top surface at the end section, with the first angled channel extending to an edge of the end section and dividing the end section into a first end portion and a second end portion. The PCB material is removed from the top surface at the first end portion to form a first support member having an upper surface at a preselected distance below the top surface. A second angled channel is formed in the bottom surface at the end section of the first PCB, with the second angled channel extending to the edge of the end section and being adjacent to the first support member. The PCB material is removed from the bottom surface at the second end portion to form a second support member having an upper surface that is contiguous with the top surface of the PCB.Type: ApplicationFiled: November 18, 2011Publication date: August 28, 2014Applicant: HONEYWELL INTERNATIONAL INC.Inventors: Nigel Wang, Orville Nyhus
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Publication number: 20140240940Abstract: A connection structure for an electronic component, which is set on two lead frames spaced apart from each other. The electronic component is connected to the two lead frames by a conductive joining member. The connection structure includes two electrodes arranged on at least portions of a lower surface of the electronic component. The two electrodes respectively face the two lead frames. A receiving surface is included in each of the two lead frames immediately below the corresponding electrode. The receiving surface extends from a supporting portion supporting the electronic component toward the other one of the lead frames and away from the electronic component. The conductive joining member is located between the receiving surface of each of the two lead frames and the corresponding one of the electrodes.Type: ApplicationFiled: February 21, 2014Publication date: August 28, 2014Applicant: KABUSHIKI KAISHA TOKAI RIKA DENKI SEISAKUSHOInventor: Hajime ITO
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Patent number: 8813354Abstract: An electromagnetic interference (EMI) shielding structure, which includes: a substrate, at least one chip unit, a packing layer, and an EMI shielding unit. The chip unit is disposed on the surface of the substrate and electrically coupled thereto. The packing layer is formed on the substrate and covers the chip unit. The EMI shielding unit includes: a first, second, and third shielding layer. The first shielding layer covers the outer surface of the packing layer and the lateral surface of the substrate. The second and third shielding layer respectively covers the outer surface of the first and second shielding layer. Based on the instant disclosure, the EMI shielding unit uses the methods of sputtering and electroless plating, to increase the adhesion strength of the EMI shielding unit and make the thickness of the shielding layer uniform. The instant disclosure raises the EMI shielding efficiency and lowers the manufacturing cost.Type: GrantFiled: August 1, 2011Date of Patent: August 26, 2014Assignees: Universal Scientific Industrial (Shanghai) Co., Ltd., Universal Global Scientific Industrial Co., Ltd.Inventor: Ming-Che Wu
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Patent number: 8814954Abstract: The method for manufacturing products having a metal surface by imparting microfeatures onto the metal surface. The method if further described as the steps of: creating a transfer tool from a microstructured intermediate fabricated from a microstructured prototype having microfeatures; and, transferring the microfeatures to said metal surface using the transfer tool.Type: GrantFiled: August 26, 2010Date of Patent: August 26, 2014Assignee: Hoowaki, LLCInventors: Ralph A. Hulseman, David Mammarella, Andrew H. Cannon, William P. King
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Patent number: 8813324Abstract: A method for fabricating a piezoelectric multilayer are described. The method includes providing conductive layers. Alternating conductive layers are electrically connected. A first plurality of alternating conductive layers is electrically isolated from a second plurality of alternating conductive layers. Piezoelectric layers are interleaved with the conductive layers. Apertures are provided in the piezoelectric layers. A first conductive plug electrically connects the first plurality of alternating conductive layers, includes a first plurality of segments, and is in apertures in the piezoelectric layers. Each of the first plurality of segments extends through one of the piezoelectric layers. A second conductive plug electrically connects the second plurality of alternating conductive layers, includes a second plurality of segments, and is in a second portion of the plurality of apertures. Each of the second plurality of segments extends through one of the plurality of piezoelectric layers.Type: GrantFiled: April 30, 2012Date of Patent: August 26, 2014Assignee: Western Digital (Fremont), LLCInventors: Nathan C. Emley, Donghong Li, Prakash Mani
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Patent number: 8813353Abstract: A dielectric structure including a metal foil, a dielectric layer and a conductor layer provided in this order, wherein the metal foil has a thickness of from 10 to 40 ?m, the dielectric layer has a thickness of from 0.3 to 5 ?m, and the conductor layer has a thickness of from 0.3 to 10 ?m. The dielectric structure has plural vias which are separated from each other, and which penetrate through both of the dielectric layer and the conductor layer. The vias of the dielectric layer have different diameters which are in a range of from 100 to 300 ?m, a diameter of each of the vias of the conductor layer is larger than a diameter of a corresponding via of the dielectric layer by 5 to 50 ?m, and a minimum via pitch is from 100 to 350 ?m.Type: GrantFiled: May 21, 2010Date of Patent: August 26, 2014Assignee: NGK Spark Plug Co., Ltd.Inventors: Yasuhiko Inui, Takamichi Ogawa, Seiji Ichiyanagi, Jun Otsuka, Manabu Sato
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Patent number: 8800138Abstract: A method for forming an electronic device on a flexible substrate conditions a surface of the flexible substrate to increase its malleability and to provide a conditioned substrate surface. A master surface is impressed against the conditioned substrate surface. The master surface is then released from the conditioned substrate surface, thereby forming a circuit-side surface on the substrate. The electronic device is then formed on the circuit-side surface. The substrate may be supported on a carrier during the method.Type: GrantFiled: February 27, 2009Date of Patent: August 12, 2014Assignee: Carestream Health, Inc.Inventors: Timothy J. Tredwell, Roger S. Kerr
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Publication number: 20140218883Abstract: An electronic module includes a substrate, which includes a dielectric material having multiple sides, including first and second sides, and first and second cavities indented respectively within the first and second sides. First and second conductive contacts within the first and second cavities are configured for contact with at least first and second electronic components that are mounted respectively in the first and second cavities. Conductive traces within the substrate are in electrical communication with the first and second conductive contacts.Type: ApplicationFiled: April 13, 2014Publication date: August 7, 2014Applicant: Eagantu Ltd.Inventors: Michael Dakhiya, Eran Shaked
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Publication number: 20140218869Abstract: A heat radiation structure for an electric device includes: at least one multi-layer substrate including a plurality of base parts made of insulation material and a conductor pattern, which are stacked in a multi-layer structure so that the conductor pattern is electrically coupled with an interlayer connection portion in the base parts; the electric device having at least one of a first electric element built in the at least one multi-layer substrate and a second electric element, which is not built in the multi-layer substrate; and a low heat resistance element opposed to the electric device. The low heat resistance element has a heat resistance lower than the insulation material.Type: ApplicationFiled: January 29, 2014Publication date: August 7, 2014Applicant: Denso CorporationInventors: Takahiro YAMANAKA, Yoshimichi HARA, Toshihisa YAMAMOTO, Kouji KAMEYAMA, Yuuji KOBAYASHI
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Publication number: 20140213077Abstract: A primary circuit board has a front surface, a back surface, and a non-conductive void. The void has first planar dimensions through a first portion of a thickness of the primary circuit board extending from the front surface to a position between the front and back surfaces, and second planar dimensions through a second portion of the thickness extending from the position at least towards the back surface. A secondary circuit board holder includes a non-conducting locking member insertable into the non-conductive void at the primary circuit board's front surface to secure the holder while a conductive part of the holder is conductively affixed to a conductive part of the primary circuit board. The first planar dimensions are different than the second planar dimensions to permit the primary circuit board's thickness to be greater than a maximum thickness specification of the holder's non-conducting locking member.Type: ApplicationFiled: January 27, 2013Publication date: July 31, 2014Applicant: International Business Machines CorporationInventors: Wai M. Ma, James E. Tersigni, Jefferson L. Watson
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Patent number: 8789272Abstract: A test socket that provides a temporary interconnect between terminals on an integrated circuit (IC) device and contact pads on a test printed circuit board (PCB). The test socket includes a compliant printed circuit and a socket housing. The compliant printed circuit includes at least one compliant layer, a plurality of first contact members located along a first major surface, a plurality of second contact members located along a second major surface, and a plurality of conductive traces electrically coupling the first and second contact members. The compliant layer is positioned to bias the first contact members against the terminals on the IC device and the second contact members against contact pads on the test PCB. The socket housing is coupled to the compliant printed circuit so the first contact members are positioned in a recess of the socket housing sized to receive the IC device.Type: GrantFiled: May 27, 2010Date of Patent: July 29, 2014Assignee: HSIO Technologies, LLCInventor: James Rathburn
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Patent number: 8782895Abstract: In a method for manufacturing a droplet ejection head, a structure of a substrate having an energy-generating element that imparts energy to a liquid to eject a liquid droplet from an ejection orifice and an orifice plate having the ejection orifice formed therein are laminated through a flow channel member for forming a pattern of a liquid flow channel that is a region in which the liquid flows. At least one of a plate before being laminated and the flow channel member before being laminated has a void of at least one of a through-hole other than the ejection orifice and a recess in the face to be laminated.Type: GrantFiled: November 10, 2011Date of Patent: July 22, 2014Assignee: Canon Kabushiki KaishaInventor: Yoshiyuki Fukumoto
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Patent number: 8782882Abstract: A method of manufacturing a printed circuit board includes the following steps (A) to (D). (A) Laminating a resin insulating layer on each of two sides of a core member to form a core substrate, (B) forming penetrating openings in the core substrate by applying laser beams, (C) forming a rough surface on the core substrate, and (D) providing a metal film for each penetrating opening to form through holes.Type: GrantFiled: June 27, 2011Date of Patent: July 22, 2014Assignee: Ibiden Co., Ltd.Inventors: Motoo Asai, Dongdong Wang, Takahiro Mori
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Patent number: 8786084Abstract: A semiconductor package includes a semiconductor die attached to a support having electrically conductive paths, the semiconductor die having a bond-pad electrically connected to the electrically a conductive path on the support by a bond-wire of a first metallic composition, the bond-wire and the bond-pad being coated with a protection layer of a second metallic composition.Type: GrantFiled: March 31, 2010Date of Patent: July 22, 2014Assignee: STMicroelectronics (Grenoble 2) SASInventors: Romain Coffy, Jean-François Sauty
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Patent number: 8776363Abstract: A method for supporting a semiconductor wafer includes providing a device wafer to a magnetizable ring, providing a magnetizable carrier to the device wafer, and magnetizing the magnetizable ring and the magnetizable carrier to form a magnetized clamp having a magnetized ring and magnetized carrier. The magnetized clamp securely clamps the device wafer therebetween.Type: GrantFiled: May 23, 2012Date of Patent: July 15, 2014Assignee: United Microelectronics Corp.Inventors: Chang-Sheng Hsu, Li-Che Chen, Kuo-Yuh Yang, Chia-Wen Lien, Yan-Da Chen
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Patent number: 8776364Abstract: A multilayer ceramic component includes a stack containing ceramic layers and electrode layers interspersed among the ceramic layers. The electrode layers contain copper and define first and second internal electrodes. First and second external contacts are on different sides of the stack. The first and second external contacts contain copper and are substantially perpendicular to the ceramic layers and electrode layers. The first internal electrode is connected to the first external contact and the second internal electrode is connected to the second external contact. The first and second internal electrodes overlap each other at a plane intersecting the stack. In areas adjacent to boundaries between the first and second external contacts and the ceramic layers, the first and second external contacts are not oxidized and material making-up the ceramic layers is not diminished. A bonding strength of the external contacts to the stack exceeds 50 N.Type: GrantFiled: March 31, 2009Date of Patent: July 15, 2014Assignee: EPCOS AGInventors: Heinz Florian, Marion Ottlinger, Peter Sedlmaier
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Patent number: 8780561Abstract: A method of forming a heat-dissipating structure for semiconductor circuits is provided. First and second semiconductor integrated circuit (IC) chips are provided, where the first and second semiconductor chips each have first and second opposing sides, wherein the first and second semiconductor IC chips are configured to be fixedly attached to a top surface of a substantially planar circuit board along their respective first sides. The respective second opposing sides of each of the first and second semiconductor IC chips are coupled to first and second respective portions of a sacrificial thermal spreader material, the sacrificial thermal spreader material comprising a material that is thermally conductive. The first and second portions of the sacrificial thermal spreader material are planarized to substantially equalize a respective first height of the first semiconductor chip and a respective second height of the second semiconductor chip.Type: GrantFiled: March 30, 2012Date of Patent: July 15, 2014Assignee: Raytheon CompanyInventors: Paul A. Danello, Richard A. Stander, Michael D. Goulet
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Publication number: 20140192502Abstract: Disclosed are a method and system to reduce impedance of printed circuit boards through an interconnecting of printed circuit boards using a square wave pattern of plated-through holes. A method of connecting a first printed circuit board to a second printed circuit board comprises forming a square wave pattern of the first printed circuit board and the second printed circuit board and adjoining the first printed circuit board and the second printed circuit board. The method also involves producing plated-through holes along the square wave pattern, a top section, and/or a bottom section of the adjoined first printed circuit board and second printed circuit board. The method further involves securing the top section and the bottom section using a first metal clip and a second metal clip, respectively, and connecting the first printed circuit board to the second printed circuit board by a wave soldering process.Type: ApplicationFiled: January 8, 2013Publication date: July 10, 2014Inventor: Shuang Xu
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Patent number: 8772088Abstract: In a high frequency module, electronic components are mounted on a mounting surface of a collective substrate including a plurality of unit substrates that include a via conductor electrically conducted to a ground potential in a peripheral portion thereof, and the mounting surface and the electronic components are encapsulated with an encapsulation layer. The collective substrate is cut on the encapsulation layer side, thereby forming a half-cut groove penetrating through the encapsulation layer and extending halfway along the collective substrate in a thickness direction such that the via conductor is exposed only at a bottom surface of the half-cut groove. A conductive shield layer is formed to cover the encapsulation layer and is electrically conducted to the exposed via conductor. The collective substrate is then cut into individual unit substrates each including the conductive shield layer electrically conducted to the ground potential through the via conductor.Type: GrantFiled: February 7, 2012Date of Patent: July 8, 2014Assignee: Murata Manufacturing Co., Ltd.Inventor: Takayuki Horibe
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Patent number: 8763242Abstract: In a method of manufacturing a semiconductor device, a second wiring substrate is stacked over a first wiring substrate using a conductive paste, where each wiring substrate has mounted thereon an electronic component. The conductive paste is hardened to form a metal column which forms an electrical connection between the first wiring substrate and the second wiring substrate. The wiring substrates are sealed with a resin. The semiconductor device can be downsized, thinned, and made highly reliable, and its manufacturing cost can be reduced. By using conductive paste for the electrical connection between the wiring substrates, a connecting pitch can be smaller than that in a connecting method of using a solder ball including Cu core, and a connection at low temperature can be achieved. Also, by coating the conductive paste by a print-coating or dispense-coating method, manufacturing is simplified and the manufacturing cost is reduced.Type: GrantFiled: November 30, 2010Date of Patent: July 1, 2014Assignee: Renesas Electronics CorporationInventors: Kenya Kawano, Chiko Yorita, Yuji Shirai
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Patent number: 8766107Abstract: Example multi-layer printed circuit boards (‘PCBs’) are described as well as methods of making and using such PCBs that include layers of laminate; at least one via hole traversing the layers of laminate, and a via conductor contained within the via hole, the via conductor comprising a used portion and an unused portion, the via conductor comprising copper coated with a metal having a conductivity lower than the conductivity of copper.Type: GrantFiled: April 13, 2012Date of Patent: July 1, 2014Assignee: International Business Machines CorporationInventors: Moises Cases, Tae Hong Kim, Rohan U. Mandrekar, Nusrat I. Sherali
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Patent number: 8763240Abstract: A fabricating process for a multi-layer printed circuit board containing embedded passive components is provided. The method includes a calibration step wherein a calibration measurement is taken of the geometry or at least one electrical parameter of an arrangement of calibration test points for a circuit forming process, such as masking, etching and/or lamination. A process control step is performed during the process, wherein a process control measurement is taken of at least one electrical parameter at one or more process control test points along one or more axes outside areas in which a circuit is to be formed. An analysis is performed of at least the calibration measurement and the process control measurement to calculate a CAD geometry change required to improve precision of embedded passive components to be printed on the multi-layer printed circuit board.Type: GrantFiled: July 5, 2011Date of Patent: July 1, 2014Assignee: TFRI, Inc.Inventors: Lendon L. Bendix, Derek A. Turner
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Patent number: 8763244Abstract: There is disclosed a method of forming a patterned conductive element for an implantable medical device, the method comprising the steps of: depositing a supplementary material on a sheet of conductive, parent material to form a sheet of composite material; applying a carrier material over the supplementary material of the composite sheet to form a sheet of semi-finished material; removing portions from at least the conductive parent material of the sheet of semi-finished material in accordance with a desired pattern corresponding to a patterned conductive element to be formed; and releasing at least the carrier material from the sheet of semi-finished material.Type: GrantFiled: May 26, 2009Date of Patent: July 1, 2014Assignee: Cochlear LimitedInventor: Peter Schuller
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Patent number: 8763241Abstract: A method for manufacturing a printed circuit board including providing a first resin substrate having a resin plate and a circuit pattern formed on a surface of the resin plate, providing a second resin substrate having a resin plate and an accommodation portion formed in the resin plate of the second substrate, connecting an electrode of a capacitor to the circuit pattern of the first substrate with a bonding material such that the capacitor is mounted to the first substrate, attaching the second substrate to the resin substrate through a bonding resin layer such that the capacitor on the first substrate is accommodated in the accommodation portion of the second substrate, and forming a via hole in the first substrate such that the via hole is electrically connected to the electrode of the capacitor in the accommodation portion of the second substrate.Type: GrantFiled: September 22, 2011Date of Patent: July 1, 2014Assignee: Ibiden Co., Ltd.Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
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Publication number: 20140177180Abstract: Electrical components in an electronic device are mounted on substrates such as printed circuits. Printed circuits contain signal paths formed from metal traces. The signal lines in the signal paths of the printed circuits are coupled together using electrical connection structures such as printed circuit board-to-board connectors, contacts joined by anisotropic conductive film, or contacts joined using solder. Electrical connection structures may be surrounded by conductive resilient ring-shaped structures such as conductive foam structures or spring structures. The conductive foam structures may be provided with a metal layer with which the conductive foam structures are soldered to a ring of metal on a printed circuit. Strain relief structures may be formed from an elastomeric ring that surrounds the electrical connection structures or an overmolded plastic structure.Type: ApplicationFiled: December 24, 2012Publication date: June 26, 2014Applicant: Apple Inc.Inventors: Shayan Malek, Michael B. Wittenberg, Sawyer I. Cohen, Ashutosh Y. Shukla
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Patent number: 8756803Abstract: A method for manufacturing a printed wiring board including forming an insulative resin layer containing a resin and an inorganic filler, forming a conductor layer including a conductive material and having a conductor on the insulative resin layer, irradiating a laser beam upon the conductor of the conductor layer such that the conductor is sectioned or a width of the conductor is narrowed, and forming a conductive pattern on the insulative resin layer. The inorganic filler is in an amount of 30 wt. % or more of the insulative resin layer.Type: GrantFiled: July 1, 2011Date of Patent: June 24, 2014Assignee: Ibiden Co., Ltd.Inventors: Toru Nakai, Tetsuo Amano, Yoshinori Takasaki
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Publication number: 20140170865Abstract: A substantially cable-free board connection assembly may include a plurality of printed circuit boards (PCBs) forming an interconnect plane for a plurality of electronic devices respectively attached to a plurality of plane boards included in the interconnect plane. An insertion direction for substantially all connectors is substantially perpendicular to a face of the interconnect plane. At least a portion of the board connection assembly is mounted to a support structure via a flexible connection.Type: ApplicationFiled: December 17, 2012Publication date: June 19, 2014Applicant: MICROSOFT CORPORATIONInventors: Eric C. Peterson, David T. Harper, III
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Publication number: 20140172057Abstract: An electrical stimulation lead includes a paddle body with micro-circuit assemblies having micro-circuits laminated between electrically-nonconductive substrates. The micro-circuits have first end portions and opposing second end portions. Electrodes are electrically coupled to the first end portions of the micro-circuits. Distal end portions of one or more lead bodies are coupled to the paddle body. Terminals are disposed along proximal end portions of the one or more lead bodies. Lead-body conductors are coupled to the terminals and extend along the one or more lead bodies to distal end portions of the one or more lead bodies. The lead-body conductors are attached to the second end portions of the micro-circuits to electrically couple the terminals to the electrodes.Type: ApplicationFiled: December 10, 2013Publication date: June 19, 2014Applicant: BOSTON SCIENTIFIC NEUROMODULATION CORPORATIONInventor: William George Orinski
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Publication number: 20140170866Abstract: An improved electrical connector retainer employs a shell having a cavity. A pair of mated electrical connectors are received within the cavity and at least a portion of an upper wall of the shell is deflected towards a lower wall of the shell. The shell is configured to retain the upper wall in the deflected position, maintaining the pair of connectors in the mated position.Type: ApplicationFiled: December 18, 2012Publication date: June 19, 2014Applicant: Apple Inc.Inventors: Derek W. Wright, Alex Yeung, Steve McClure, Sean S. Corbin, John B. Ardisana, II, Benjamin J. Pope, Shayan Malek
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Patent number: 8752283Abstract: A method for operating an assembly tool includes deposing a first component on an assembly surface with a first tool tip of a manipulator having a range of motion defined by a plane and an axis that is substantially normal to the plane, deposing a second component on the assembly surface, changing an orientation of the assembly surface relative to the axis from a first orientation to a second orientation, lifting the first component from the assembly surface with a second tool tip of the manipulator, and deposing the first component on the second component.Type: GrantFiled: June 1, 2012Date of Patent: June 17, 2014Assignee: International Business Machines CorporationInventors: Tymon Barwicz, Bing Dang
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Patent number: RE45143Abstract: An apparatus for equalizing voltage across an electrical lighting system, particularly in low voltage landscape lighting systems. The apparatus consists of a plastic cylinder having open ends and containing two or more connectors for connecting a homerun wire from a transformer to wire leads from the various light fixtures in the lighting system. The wire leads are of uniform length to ensure that each light fixture is ecu equally distant from the transformer.Type: GrantFiled: July 18, 2012Date of Patent: September 23, 2014Assignee: The Toro CompanyInventor: Nate Mullen