Assembling Bases Patents (Class 29/830)
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Publication number: 20150005573Abstract: A device, including an implantable electronic circuit integrated at least one of in or on a substrate, wherein the device includes a hermetic enclosure having a space therein, wherein the substrate forms at least a portion of the hermetic enclosure.Type: ApplicationFiled: July 1, 2014Publication date: January 1, 2015Inventors: Torsten LEHMANN, Gregg Jørgen SUANING, Tony Mikael NYGARD, Thomas GUENTHER, William LIM, Kushal DAS
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Patent number: 8918992Abstract: A circuit layer manufacturing method is applied to a portable computer. The portable computer includes a front bezel, a display module, and a back cover. The front bezel is connected to the back cover for containing the display module. The front bezel includes a metal portion. The metal portion has a flat region corresponding to a side of the back cover. The circuit layer manufacturing method includes forming at least one control circuit layer assembly on the flat region, grounding the control circuit layer assembly to the flat region, and forming a protection layer on the control circuit layer assembly. The control circuit layer assembly includes an insulation layer and a control circuit layer. The control circuit layer is electrically connected to the display module. The insulation layer is formed between the control circuit layer and the flat region for being alternately stacked with the control circuit layer.Type: GrantFiled: July 25, 2012Date of Patent: December 30, 2014Assignee: Wistron CorporationInventor: Chu-Hsun Wu
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Patent number: 8918971Abstract: A method of manufacturing packages having contents sealed therein, including: a step of forming cavities in a plurality of package forming areas on a first wafer; a step of bonding the first wafer and a second wafer while arranging the contents in the cavities; and a step of irradiating a bonded wafer member with a laser and separating the packages into pieces, characterized in that dummy cavities are formed on an outside of the package forming area in an outermost periphery of the first wafer in the cavity forming step.Type: GrantFiled: July 7, 2011Date of Patent: December 30, 2014Assignee: SII Crystal Technology Inc.Inventor: Junya Fukuda
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Publication number: 20140376196Abstract: The invention relates to a method for producing a printed circuit board consisting of at least two printed circuit board regions, wherein the printed circuit board regions each comprise at least one conductive layer and/or at least one conductive component, wherein printed circuit board regions to be connected to one another, in the region of in each case at least one lateral surface directly adjoining one another, are connected to one another by a mechanical coupling. According to the invention, at least one sub-region or connection port of the conductive layer, and/or a conductive element of the component are electrically conductively coupled to each other at the lateral surface, whereby a simple and reliable lateral electrical coupling between printed circuit board regions to be connected to each other is rendered possible. The invention further relates to such a printed circuit board.Type: ApplicationFiled: December 28, 2012Publication date: December 25, 2014Inventors: Volodymyr Karpovych, Johannes Stahr
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Publication number: 20140376193Abstract: There is provided an electronic component module capable of increasing a degree of integration by mounting electronic component on both surfaces of a substrate, the module including: a first substrate having mounted electrodes formed on both surfaces thereof; a plurality of electronic components mounted on both surfaces of the first substrate; at least one second substrate bonded to a lower surface of the first substrate; and an insulating part formed in at least one position in a gap between the first substrate and the second substrate and bonding the first substrate to the second bonding substrate.Type: ApplicationFiled: October 7, 2013Publication date: December 25, 2014Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Il Hyeong LEE, Jae Cheon DOH, Seung Yong CHOI
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Patent number: 8914974Abstract: The invention relates to a method for integrating an electronic component into a printed circuit board, whereby the electronic component (4) comprising contacts (6) oriented towards an insulating layer (1) which is fixed to a laminate consisting of a conductive layer (2) and a insulating layer (1). Once the component (4) has been fixed to the insulating layer (1), at least one hole or perforation (8, 11) corresponding to the contacts (6) of the component (4) are formed in the conducting layer (2) and in the insulating layer (1), the contacts come into contact with the conducting layer (2), enabling a reliable integration or embedding of an electronic component (4) into a printed circuit board.Type: GrantFiled: October 28, 2009Date of Patent: December 23, 2014Assignee: AT & S Austria Technologie & Systemtechnik AktiengesellschaftInventors: Wolfgang Schrittwieser, Patrick Lenhardt, Klaus Merl
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Publication number: 20140368220Abstract: A non-contact sensing module includes a coil printed circuit board in which a reference pattern coil may be formed at an upper surface and in which a sensing pattern coil may be formed at a lower surface and that has a mounting hole at the center, and a main printed circuit board that may be coupled to the mounting hole and that may be vertically disposed at an upper surface of the coil printed circuit board and that may be electrically connected to the reference pattern coil and the sensing pattern coil.Type: ApplicationFiled: June 18, 2013Publication date: December 18, 2014Applicants: DH Holdings Co., Ltd., Hyundai Motor CompanyInventors: Myung-Sub Kum, Jong-Sang Noh, Jung-Min Lee
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Publication number: 20140366369Abstract: A method for manufacturing a circuit board constituted by a light emitting device and a mounting board includes the steps of: conveying the light emitting device onto the mounting board in a state in which a top face is chucked by a nozzle so that the nozzle and an exposed part of a first terminal part of the light emitting device are in contact; and placing the light emitting device onto the mounting board so that the first terminal part and a wiring component are in contact in a state in which the top face is chucked by the nozzle.Type: ApplicationFiled: September 5, 2014Publication date: December 18, 2014Inventors: Ryohei YAMASHITA, Tomohide MIKI, Hiroto TAMAKI
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Patent number: 8910356Abstract: A method of forming an electrical component is provided. The method comprises preparing a subassembly by electrically connecting an integrated circuit to a flexible circuit; and attaching the subassembly to a multilayer ceramic capacitor having a mounting surface with a curvature deviation exceeding 0.008 inches per inch.Type: GrantFiled: May 24, 2010Date of Patent: December 16, 2014Assignee: Kemet Electronics CorporationInventors: Michael S. Randall, Chris Wayne, John McConnell
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Patent number: 8910380Abstract: Described is a process for producing an inkjet printhead comprising an aperture face having an oleophobic surface. The process includes forming an aperture plate by disposing a silicon layer on an aperture plate; using photolithography to create a textured pattern on an outer surface of the silicon layer; and chemically modifying the textured surface by disposing a conformal, oleophobic coating on the textured surface. The oleophobic aperture plate may be used as a front face surface for an inkjet printhead.Type: GrantFiled: June 15, 2010Date of Patent: December 16, 2014Assignee: Xerox CorporationInventors: Kock-Yee Law, Hong Zhao
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Patent number: 8910355Abstract: Manufacturing a semiconductor structure including modifying a frequency of a Film Bulk Acoustic Resonator (FBAR) device though a vent hole of a sealing layer surrounding the FBAR device.Type: GrantFiled: December 12, 2011Date of Patent: December 16, 2014Assignee: International Business Machines CorporationInventors: James W. Adkisson, Panglijen Candra, Thomas J. Dunbar, Jeffrey P. Gambino, Mark D. Jaffe, Anthony K. Stamper, Randy L. Wolf
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Publication number: 20140360013Abstract: Methods, structures, apparatus, devices, and materials to facilitate the integration of electronic integrated circuits (chips) including drivers, amplifiers, microcontrollers, etc., onto/into photonic integrated circuits (chips) using recessed windows exhibiting controlled depths onto/into the photonic chip. The electronic chips are positioned into the recessed windows and electrical connections between the electronic chips and the photonic chip are achieved by flip-chip techniques with predefined traces at a bottom of the recessed windows or direct wire bonding. Advantageously, this integration may be performed on a wafer level for large-volume productions.Type: ApplicationFiled: June 6, 2014Publication date: December 11, 2014Inventor: Long CHEN
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Patent number: 8904631Abstract: An interconnect device and a method for fabricating same. An embodiment of the invention includes sequential steps of providing a flexible substrate, forming vias through the flexible substrate, applying a conductive seed layer including first and second portions, applying conductive materials including first and second portions, copper plating the substrate, and then removing the second portions of the conductive seed layer and the conductive materials.Type: GrantFiled: April 15, 2011Date of Patent: December 9, 2014Assignee: General Electric CompanyInventors: Kevin Matthew Durocher, William Edward Burdick, Jr., Yuru Alexeyevich Plotnikov, David DeCrescente, Jr.
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Patent number: 8904632Abstract: A method is for making a multilayer circuit board from circuit board layers, each including a dielectric layer and conductive traces thereon including a first metal. The method includes forming a through-via in a first circuit board layer, plating the through-via with the first metal, and coating a second metal onto the first metal of the first circuit board layer, the plated through-via, and the first metal. The method also includes aligning the first and second circuit board layers together so that the plated through-via of the first circuit board layer is adjacent a feature on the second circuit board layer, and heating and pressing the aligned first and second circuit board layers so as to laminate the dielectric layers together and form an intermetallic compound of the first and second metals bonding adjacent metal portions together.Type: GrantFiled: September 23, 2011Date of Patent: December 9, 2014Assignee: Harris CorporationInventors: Michael Raymond Weatherspoon, Louis Joseph Rendek, Jr., Lawrence Wayne Shacklette, Casey P. Rodriguez
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Patent number: 8907694Abstract: A wiring board for transmission of test signals between test point locations on a circuit board under test and an external analyzer having compliant contacts making electrical contact with a pad positioned on a conductive surface circuit layer having a trace extending to a second pad having a hole for receipt of an interface pin electrically connected to the external analyzer.Type: GrantFiled: December 3, 2010Date of Patent: December 9, 2014Assignee: Xcerra CorporationInventors: Mark A. Swart, Kenneth R. Snyder
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Publication number: 20140354915Abstract: A narrow frame liquid crystal display, comprising: an array substrate comprising a first mounting area and a second mounting area; a color film substrate mounted on the first mounting area; a first chip bonded onto the second mounting area of the array substrate; a first flexible circuit board bonded onto the second mounting area of the array substrate; a first lead configured to electrically connect the first chip and the first flexible circuit board; and a second lead configured to electrically connect a display region of the array substrate and the first chip. The first chip, the first lead and the first flexible circuit board are sequentially arranged on the second mounting area in a first direction away from the color film substrate. A distance between the first chip and the first flexible circuit board is set to be less than 10 mm. The size of the area for mounting the chip can be reduced, and the frame of the liquid crystal display can become narrower.Type: ApplicationFiled: February 27, 2014Publication date: December 4, 2014Applicant: BOE Technology Group Co., Ltd.Inventors: Chao Xu, Wei Qin
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Publication number: 20140355229Abstract: A surface treated copper foil which is well bonded to a resin and achieves excellent visibility when observed through the resin, and a laminate using the same are provided.Type: ApplicationFiled: November 11, 2013Publication date: December 4, 2014Inventors: Hideta Arai, Atsushi Miki, Kohsuke Arai, Kaichiro Nakamuro
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Patent number: 8898891Abstract: Circuit boards and methods for their manufacture are disclosed. The circuit boards carry high-speed signals using conductors formed to include lengthwise channels. The channels increase the surface area of the conductors, and therefore enhance the ability of the conductors to carry high-speed signals. In at least some embodiments, a discontinuity also exists between the dielectric constant within the channels and just outside the channels, which is believed to reduce signal loss into the dielectric material.Type: GrantFiled: December 7, 2010Date of Patent: December 2, 2014Assignee: Force10 Networks, Inc.Inventors: Joel R. Goergen, Yi Zheng
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Patent number: 8898892Abstract: A circuit board module includes a circuit board and a heat-dissipating device. The circuit board includes a ceramic substrate, and a circuit pattern formed on a surface of the ceramic substrate. The circuit board is sinter-bonded to a main body of the heat-dissipating device. A method of making the circuit board module is also disclosed.Type: GrantFiled: September 5, 2013Date of Patent: December 2, 2014Assignee: Tong Hsing Electronic Industries, Ltd.Inventors: Wen-Chung Chiang, Keng-Chung Wu, Ying-Chi Hsieh, Cheng-Kang Lu, Ming-Huang Fu
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Patent number: 8898896Abstract: The invention relates to a method for making a connection component that comprises a set of conducting inserts to be electrically connected with another component, said inserts being hollow.Type: GrantFiled: February 19, 2009Date of Patent: December 2, 2014Assignee: Commissariat a l'Energie Atomique et aux Energies AlternativesInventors: Francois Marion, Damien Saint-Patrice
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Patent number: 8898875Abstract: Providing a method for manufacturing a package capable of achieving reliable anodic bonding between the bonding material and a base board wafer even when the bonding material having a large resistance value is used. Providing a method for manufacturing a package by anodically bonding a bonding material, which is fixed in advance to an inner surface of a lid board wafer made of an insulator, to an inner surface of a base board wafer made of an insulator, the method including an anodic bonding step where an auxiliary bonding material serving as an anode is disposed on an outer surface of the lid board wafer, a cathode is disposed on an outer surface of the base board wafer, and a voltage is applied between the auxiliary bonding material and the cathode, wherein the auxiliary bonding material is made of a material that causes an anodic bonding reaction between the auxiliary bonding material and the lid board wafer in the anodic bonding step.Type: GrantFiled: August 25, 2010Date of Patent: December 2, 2014Assignee: Seiko Instruments Inc.Inventor: Takeshi Sugiyama
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Publication number: 20140346317Abstract: A method of manufacturing a touch screen panel includes forming first sensing electrodes on a first substrate, forming second sensing electrodes on a second substrate, and forming a photosensitive layer on the first sensing electrodes. The photosensitive layer is patterned to form photosensitive spacers spaced apart from one another in a first direction. The first substrate and the second substrate are joined together. The photosensitive spacers maintain a substantially constant space between the first sensing electrodes and the second sensing electrodes in a second direction.Type: ApplicationFiled: September 13, 2013Publication date: November 27, 2014Applicant: Samsung Display Co., Ltd.Inventor: Sun-Haeng CHO
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Publication number: 20140347839Abstract: A hermetic electronics package includes a metal case with opposing first and second open ends, with each end connected to a first feedthrough construction and a second feedthrough construction. Each feedthrough contruction has an electrically insulating substrate and an array of electrically conductive feedthroughs extending therethrough, with the electrically insulating substrates connected to the opposing first and second open ends, respectively, of the metal case so as to form a hermetically sealed enclosure. A set of electronic components are located within the hermetically sealed enclosure and are operably connected to the feedthroughs of the first and second feedthrough constructions so as to electrically communicate outside the package from opposite sides of the package.Type: ApplicationFiled: June 14, 2012Publication date: November 27, 2014Inventors: Kedar G. Shah, Satinderpall S. Pannu
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Publication number: 20140345123Abstract: Manufacturing a product, wherein the product includes a first part and a second part, wherein the first part includes solder pins and the second part includes solder pads, wherein each of the solder pins has the matching solder pad, wherein each of the solder pads is covered by a matching solder paste bead. Aligning the solder pins against the solder pads in a way that each pair of the solder pin and the matching solder pad is thermally and electrically connected by the matching solder paste bead. Connecting a mating connector to the first part, wherein the mating connector is operable for providing a part of an electrical conducting path.Type: ApplicationFiled: May 20, 2014Publication date: November 27, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce J. Chamberlin, Andreas Huber, Harald Huels, Thomas-Michael Winkel
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Publication number: 20140347964Abstract: A timing device for indicating a passage of a duration of time is disclosed. The timing device in accordance with the embodiments of the invention has a grid array architecture. The grid array architecture includes an electrode structure with an anode layer, a cathode layer and a thermistor layer. The anode layer and the thermistor layer are electrically coupled through a plurality of cathode line structures. In operation the timing device is actuated through a suitable mechanism to initiate depletion of the anode layer and, thereby, indicate a passage of a duration time. As the anode layer depletes, sequential cathode line structures are exposed and the thermistor layer acts as a variable resistor through a plurality of exposed cathode line structures.Type: ApplicationFiled: August 6, 2014Publication date: November 27, 2014Inventor: Alfred S. Braunberger
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Patent number: 8893379Abstract: A manufacturing method of a package structure is provided. In the manufacturing method, a metal substrate having a seed layer is provided. A patterned circuit layer is formed on a portion of the seed layer. A first patterned dry film layer is formed on the other portion of the seed layer. A surface treatment layer is electroplated on the patterned circuit layer with use of the first patterned dry film layer as an electroplating mask. The first patterned dry film layer is removed. A chip bonding process is performed to electrically connect a chip to the surface treatment layer. An encapsulant is formed on the metal substrate. The encapsulant encapsulates the chip, the surface treatment layer, and the patterned circuit layer. The metal substrate and the seed layer are removed to expose a bottom surface of the encapsulant and a lower surface of the patterned circuit layer.Type: GrantFiled: December 3, 2012Date of Patent: November 25, 2014Assignee: Subtron Technology Co., Ltd.Inventors: Shih-Hao Sun, Chang-Fu Chen
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Publication number: 20140340861Abstract: Electronic devices may include a first substrate including circuitry components within the substrate, a microscale bond pad on a surface of the substrate, and a via electrically connecting the microscale bond pad to one of the circuitry components. A distance between centers of at least some adjacent circuitry components of the circuitry components may be a nanoscale distance. A second substrate may be electrically connected to the microscale bond pad. Methods of forming electronic devices may involve positioning a first substrate adjacent to a second substrate and electrically connecting the second substrate to a microscale bond pad on a surface of the first substrate. The first substrate may include circuitry components within the first substrate and a via electrically connecting the microscale bond pad to one of the circuitry components. A distance between centers of at least some adjacent circuitry components of the circuitry components may be a nanoscale distance.Type: ApplicationFiled: August 7, 2014Publication date: November 20, 2014Inventors: Roy E. Meade, Gurtej S. Sandhu
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Publication number: 20140340731Abstract: Thin-film devices, for example electrochromic devices for windows, and methods of manufacturing are described. Particular focus is given to methods of patterning optical devices. Various edge deletion and isolation scribes are performed, for example, to ensure the optical device has appropriate isolation from any edge defects. Methods described herein apply to any thin-film device having one or more material layers sandwiched between two thin film electrical conductor layers. The described methods create novel optical device configurations.Type: ApplicationFiled: December 10, 2012Publication date: November 20, 2014Applicant: View, Inc.Inventors: Fabian Strong, Yashraj Bhatnagar, Abhishek Anant Dixit, Todd Martin, Robert T. Rozbicki
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Patent number: 8881382Abstract: Embodiments of the invention provide a method of manufacturing an embedded printed circuit board, which includes the following operations in the order presented: a first operation of forming a first cavity and a third cavity, disposing a first device in the first cavity and disposing a third device in the third cavity; a second operation of forming a second cavity and a fourth cavity, disposing a second device in the second cavity; a third operation of providing an insulating member; a fourth operation of disposing a first base substrate and a second base substrate and pressure laminating the first base substrate, the second base substrate, and the insulating member together; and a fifth operation of forming a first copper clad laminate and forming a second copper clad laminate.Type: GrantFiled: August 19, 2011Date of Patent: November 11, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Sang Chul Lee, Jung Soo Byun, Jin Seon Park, Doo Hwan Lee
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Patent number: 8881381Abstract: Disclosed herein is a method of manufacturing a printed circuit board, comprising: preparing a first carrier including a first pattern formed on one side thereof; preparing a second carrier including a first solder resist layer and a second pattern sequentially formed on one side thereof; pressing the first carrier and the second carrier such that the first pattern is embedded in one side of an insulation layer and the second pattern is embedded in the other side of the insulation layer and then removing the first carrier and the second carrier to fabricate two substrates; attaching the two substrates to each other using an adhesion layer such that the first solder resist layers face each other; and forming a via for connecting the first pattern with the second pattern in the insulation layer, forming a second solder resist on the insulation layer provided with the first pattern, and then removing the adhesion layer.Type: GrantFiled: December 4, 2009Date of Patent: November 11, 2014Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Mi Sun Hwang, Myung Sam Kang, Ok Tae Kim, Seon Ha Kang, Gil Yong Shin, Kil Yong Yun, Min Jung Cho
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Publication number: 20140328030Abstract: An electrical connection between two electrical harnesses is provided. The electrical harnesses include flexible printed circuits with embedded conductive tracks, each of which terminates in a receiving hole in a respective terminating region The terminating regions are connected together using conductive pins. The connection formation is then encapsulated by an encapsulating body formed of an insulating. The encapsulating body seals and protects the electrical connection, which is thus reliable and robust.Type: ApplicationFiled: April 24, 2014Publication date: November 6, 2014Applicant: ROLLS-ROYCE PLCInventor: Paul BROUGHTON
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Patent number: 8875390Abstract: A method of manufacturing a laminate circuit board which includes the sequential steps of metalizing the substrate to form the base layer, forming the first circuit metal layer, forming at least one insulation layer and at least one second circuit metal layer interleaved, removing the substrate, forming the support frame and forming the solder resist is disclosed. The laminate circuit board has a thickness less than 150 ?m. The support frame which does not overlap the first circuit metal layer is formed on the edge of the base layer by the pattern transfer process after the substrate is removed. The base layer formed of at least one metal layer is not completely removed. The support frame provides enhanced physical support for the entire laminate circuit board without influence on the electrical connection of the circuit in the second circuit metal layer, thereby solving the warping problem.Type: GrantFiled: October 29, 2012Date of Patent: November 4, 2014Assignee: Kinsus Interconnect Technology Corp.Inventors: Ting-Hao Lin, Yu-Te Lu, De-Hao Lu
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Patent number: 8875389Abstract: Systems and methods electrically connect a first electronic device or electrical component, having a external electrical connector, to a circuit board of a second electronic device. A low-cost, user-installable connection system isolates mechanical stresses imposed on the external electrical connector to within the user-installable connection system, thereby preventing the mechanical stresses from reaching the circuit board in the second electronic device. If the connection becomes faulty, only the low-cost, user-installable connection system must be replaced.Type: GrantFiled: November 4, 2011Date of Patent: November 4, 2014Assignee: Flextronics AP, LLCInventors: Ken Kan, Jeff Chen, Michael Chang
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Patent number: 8875362Abstract: A method of manufacturing a piezoelectric device includes the steps of bonding a first substrate to a second substrate having a toughness greater than that of the first substrate, forming a first though-hole through the first substrate from the side opposite to the side on which the second substrate is bonded, and forming a second through-hole through the second substrate at a location corresponding to the first through-hole by a formation method different from that used to form the first through-hole from the side opposite to the side on which the first substrate is bonded.Type: GrantFiled: December 15, 2010Date of Patent: November 4, 2014Assignee: Murata Manufacturing Co., Ltd.Inventors: Takashi Miyake, Yuji Toyota
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Patent number: 8878560Abstract: The present disclosure provide a probe card for wafer level testing. The probe card includes a space transformer having a power line, a ground line, and signal lines embedded therein, wherein the space transformer includes various conductive lines having a first pitch on a first surface and a second pitch on a second surface, the second pitch being substantially less than the first pitch; a printed circuit board configured approximate the first surface of the space transformer; and a power plane disposed on the first surface of the space transformer and patterned to couple the power line and the ground line of the space transformer to the printed circuit board.Type: GrantFiled: December 30, 2010Date of Patent: November 4, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ying-Hsin Kuo, Wensen Hung
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Publication number: 20140318832Abstract: A manufacturing method of an anode foil for an aluminum electrolytic capacitor is provided, which comprises a first step of forming a porous oxide film, i.e. subjecting an etched foil having etched holes thereon to an anodic oxidation process to form a porous oxide film on both the outer surface of the etched foil and the inner surface of etched holes, and a second step of forming a dense oxide film, i.e. converting the porous oxide film into the dense oxide film. The method can be used to manufacture an anode foil for various voltage ranges, e.g. an ultra-high voltage anode foil whose voltage is more than 800 vf, and the method can increase specific capacity, reduce power consumption, simplify the process, and increase production efficiency.Type: ApplicationFiled: September 25, 2012Publication date: October 30, 2014Inventors: Yong Huang, Zhengqing Chen
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Publication number: 20140317918Abstract: Provided are a composition for an anisotropic conductive adhesive, a method of forming a solder bump and a method of forming a flip chip using the same. The composition for an anisotropic conductive adhesive includes a low melting point solder particle and a thermo-curable polymer resin. The anisotropic conductive adhesive includes forming a mixture by mixing a polymer resin and a curing agent, and mixing a deforming agent, a catalyst or a reductant with the mixture.Type: ApplicationFiled: July 8, 2014Publication date: October 30, 2014Applicant: Electronics and Telecommunications Research InstituteInventors: Yong Sung EOM, Jong Tae MOON, Sangwon OH, Keonsoo JANG
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Publication number: 20140321011Abstract: An electronic sub-assembly for an HVAC Controller may include a touch screen display and a printed circuit board. The touch screen display including a viewing side and a non-viewing side. A conductive trace may be disposed on the viewing side of the touch screen display adjacent a perimeter of the touch screen display. The printed circuit board, which may include a grounding feature, may be positioned adjacent the non-viewing side of the touch screen display. A connector may be in electrical communication with the conductive trace and the grounding feature of the printed circuit board.Type: ApplicationFiled: May 1, 2014Publication date: October 30, 2014Inventors: Reed Bisson, Jaromir Cechak, Tomas Gabas
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Patent number: 8872040Abstract: A wiring structure includes: an insulating film formed over a substrate; a plurality of wirings formed on the insulating film; and an inducing layer, which is formed on the insulating film in a region between the plurality of wirings, a constituent atoms of the wirings are diffused in the inducing layer.Type: GrantFiled: June 22, 2012Date of Patent: October 28, 2014Assignee: Fujitsu LimitedInventors: Tsuyoshi Kanki, Shoichi Suda, Yoshihiro Nakata
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Patent number: 8869400Abstract: A nozzle plate includes: a flow channel opening in a first surface of the nozzle plate; a liquid chamber communicating with the flow channel; and a nozzle hole communicating with the liquid chamber and opening in a second surface of the nozzle plate. The liquid chamber has a flat portion which is substantially parallel to the second surface. The nozzle hole communicates with the liquid chamber in the flat portion. A method for producing a nozzle plate includes: forming a liquid chamber which opens in a first surface of a plate-like body; forming a flat portion in a bottom of the liquid chamber; and forming a nozzle hole which communicates with the flat portion and opens in a second surface of the plate-like body.Type: GrantFiled: September 21, 2007Date of Patent: October 28, 2014Assignee: Kabushiki Kaisha ToshibaInventor: Masahiro Uekita
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Publication number: 20140311773Abstract: A multi-layer wiring board is configured having stacked therein, in a stacking direction, via an adhesive layer, a plurality of printed wiring bases in each of which a wiring pattern and a via are formed on/in a resin base. A multi-layer wiring board includes a movable portion configured from an elastic member and a void portion, the movable portion being formed in the printed wiring bases and adhesive layer in a periphery of a matrix-shaped plurality of multi-layer wiring portions disposed at a certain interval as viewed in a planar manner, and the movable portion joining the plurality of multi-layer wiring portions such that each of the multi-layer wiring portions is displaceable in the stacking direction and a direction of surfaces of the printed wiring bases.Type: ApplicationFiled: April 21, 2014Publication date: October 23, 2014Applicant: FUJIKURA LTD.Inventor: Nobuki Ueta
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Patent number: 8863377Abstract: According to one embodiment of the invention, a method for manufacturing a circuit board comprises covering with a metal layer a surface of a first resin layer including polyimide resin; forming a plurality of conductive layers arranged on the metal layer with the conductive layers apart from each other in a planer view; roughening surfaces of the conductive layers with an alkaline aqueous solution; and etching a part of the metal layer between the conductive layers in the planer view to expose the surface of the first resin layer after roughening the surfaces of the conductive layers.Type: GrantFiled: April 27, 2011Date of Patent: October 21, 2014Assignee: Kyocera CorporationInventors: Masaaki Harazono, Takayuki Umemoto
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Patent number: 8863373Abstract: An application and development apparatus has a plurality of vertically stacked blocks directed to coating film formation on a substrate. This plurality of blocks includes first processing units, a first substrate transportation region, and a first transportation unit for transporting substrates between the first processing units within the first transportation region. A development process block also is vertically stacked with the blocks directed to coating film formation to constitute a layered block as the process block. The development process block also includes second processing units and a second transportation unit for transporting substrates between the second processing units within the second transportation region. The application and development apparatus further has a shelf-type delivery stage group, a vertical transportation unit and a substrate inspection unit such that a substrate input into the inspection unit passes through the delivery stage group from the vertical transportation unit.Type: GrantFiled: October 21, 2010Date of Patent: October 21, 2014Assignee: Tokyo Electron LimitedInventors: Nobuaki Matsuoka, Shinichi Hayashi, Yasushi Hayashida, Yoshitaka Hara
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Patent number: 8863379Abstract: Methods of manufacturing printed circuit boards using parallel processes to interconnect with subassemblies are provided. In one embodiment, the invention relates to a method of manufacturing a printed circuit board including providing a core subassembly including at least one metal layer, providing a plurality of one-metal layer carriers after parallel processing each of the plurality of one-metal layer carriers, and attaching at least two of the plurality of one-metal layer carriers with each other and with the core subassembly.Type: GrantFiled: August 9, 2011Date of Patent: October 21, 2014Inventors: Rajesh Kumar, Monte P. Dreyer, Michael J. Taylor
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Publication number: 20140307396Abstract: Discussed is a flexible display device with a reduced bezel width. The flexible display device according to an embodiment includes a display panel configured to display images, and including a flexible first substrate having a plurality of pixels disposed therein and a second substrate coupled to the flexible first substrate, the flexible first substrate including a display area, a bent part extending from the display area, and a pad part extending from the bent part; a panel driver connected to the pad part, and configured to supply signals to the respective pixels; and a supporting member configured to support the flexible first substrate, and including a bent part for guiding the bent part of the first substrate.Type: ApplicationFiled: December 19, 2013Publication date: October 16, 2014Applicant: LG DISPLAY CO., LTD.Inventor: Dal Jae LEE
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Publication number: 20140304987Abstract: A photovoltaic device and a method of making a photovoltaic device that includes a stack of layers, including a substrate and an electrode layer. The photovoltaic device includes a semiconductor light absorption layer that is formed on the stack by a coating liquid that includes a plurality of semiconducting particles. The coating liquid may also include a solvent and a plurality of additive molecules. The photovoltaic device also includes a transparent conducting layer disposed on the semiconductor light absorption layer and a grid electrode disposed on the transparent conducting layer.Type: ApplicationFiled: November 29, 2012Publication date: October 16, 2014Applicant: KONICA MINOLTA LABORATORY U.S.A., INC.Inventor: Hiroaki Ando
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Patent number: 8861217Abstract: This relates to systems and methods for providing one or more vias through a module of an electrical system. For example, in some embodiments, the module can include one or more passive elements and/or active of the electrical system around which a packaging has been plastic molded. The module can be stacked under another component of the electrical system. Vias can then be provided that extend through the module. The vias can include, for example, electrically conductive pathways. In this manner, the vias can provide electrical pathways for coupling the component stacked on top of the module to other entities of an electronic device including the electrical system. For example, the component can be coupled to other entities such as other components, other modules, printed circuit boards, other electrical systems, or to any other suitable entity.Type: GrantFiled: November 5, 2012Date of Patent: October 14, 2014Assignee: Apple Inc.Inventors: Gloria Lin, William Bryson Gardner, Jr., Joseph Fisher, Jr., Dennis Pyper, Amir Salehi
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Patent number: 8853562Abstract: An electromagnetic shielding method includes the steps of disposing a flexible electromagnetic shielding film including a laminate of at least an insulating layer and a conductive metal layer to cover a portion to be electromagnetically shielded on a printed wiring board so that the insulating layer faces the printed wiring board, the conductive metal layer having a higher melting temperature than that of the insulating resin layer; and heating the electromagnetic shielding film to a temperature to melt and contract the insulating layer, thereby bonding the conductive metal layer to a grounding conductor of the printed wiring board and electrically connecting the conductive metal layer to the grounding conductor. The heating temperature is higher than the melting temperature of the insulating layer and lower than the melting temperature of the conductive metal layer.Type: GrantFiled: June 25, 2012Date of Patent: October 7, 2014Assignees: Sony Corporation, Sony Mobile Communications Inc.Inventors: Koichi Izawa, Yumi Ogura
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Patent number: 8853546Abstract: A base insulating layer is formed on a suspension body. A lead wire for plating and a wiring trace are integrally formed on the base insulating layer. A cover insulating layer is formed on the base insulating layer to cover the lead wire for plating and the wiring trace. A thickness of a portion of the cover insulating layer above a region of the base insulating layer in which the lead wire for plating is formed is set smaller than the thickness of a portion of the cover insulating layer above other regions of the base insulating layer.Type: GrantFiled: July 16, 2010Date of Patent: October 7, 2014Assignee: Nitto Denko CorporationInventors: Daisuke Yamauchi, Tetsuya Oosawa, Mitsuru Honjo, Masami Inoue
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Patent number: 8850697Abstract: An automatic or semiautomatic method of assembly of radiation digital imaging tiles to form a one or two dimensional imaging panel whereby the imaging tiles are provided with alignment mark(s), inherent or specific, and a mother board or substrate is also provide with alignment mark(s) and the imaging tiles are mounted on the mother board by means of mechanical pick and place mechanism, whereby the distances of corresponding alignment mark are set to predetermined values, programmed in the automatic machine.Type: GrantFiled: December 23, 2011Date of Patent: October 7, 2014Assignee: Oy AJAT LtdInventors: Konstantinos Spartiotis, Pasi Laukka