With Sintering Of Base Patents (Class 29/851)
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Patent number: 7905000Abstract: According to various production methods for producing a piezoceramic multilayer actuator, in the course of the production method, multilayer locks (10) are electrochemically or mechanically processed in such a way that a recess structure is obtained. The lateral surfaces (22; 24) of the electrodes (20) inside these recesses are electrically insulated using the slip casting method in order to be able to contact the remaining electrodes by imprinting an outer metallization.Type: GrantFiled: January 15, 2008Date of Patent: March 15, 2011Assignee: Siemens AktiengesellschaftInventors: Axel Ganster, Susanne Kornely, Andreas Lenk, Andreas Mantovan, Carsten Schuh, Jörg Zapf
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Patent number: 7905012Abstract: A method for manufacturing an electronic component includes: a step of temporarily bonding a substrate to a support plate with an adhesive sheet; a step of forming a cut groove for dividing the substrate into individual chips by providing the substrate with a cut extending in the thickness direction from a second surface side, located opposite the first surface side, to a certain part of the support plate; a step of forming a continuous electrode on the second surface and on a peripheral surface located inside the cut groove, of each of the chips by sputtering, for example; and a step of detaching the chips from the support plate. An electrode on the first surface of the substrate may be formed prior to the temporary bonding step, and the electrode formed on the peripheral surface may be connected to the electrode on the first surface.Type: GrantFiled: February 12, 2008Date of Patent: March 15, 2011Assignee: TDK CorporationInventors: Hajime Kuwajima, Hitoshi Ohkubo, Manabu Ohta
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Patent number: 7866039Abstract: A method of manufacturing a wiring board comprising preparing a substrate having a groove and an adjacent area; the substrate being of a wiring board also comprising a first wiring having first and second portions provided in first and second areas, respectively, making a contact angle of the second area different from a contact angle of a third area which is another part of the adjacent area, surrounding the second area together with the groove; and applying conductive paste to at least the first and second areas.Type: GrantFiled: June 12, 2007Date of Patent: January 11, 2011Assignee: Canon Kabushiki KaishaInventors: Masafumi Moriya, Kazuya Ishiwata, Yoshio Suzuki
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Patent number: 7841080Abstract: One embodiment relates to forming a plurality of vias extending partially through a body, the vias including sidewalls defined by the body. An insulating layer is formed on the sidewalls and on an upper surface of the body. An electrically conductive layer is formed on the insulating layer, the electrically conductive layer defining first metal pads on the upper surface and second metal pads in contact with the first metal pads, the second metal pads having a denser pitch than the first metal pads. A dielectric layer is formed between adjacent first metal pads and between adjacent second metal pads. A plurality of electronic elements are coupled to the second metal pads. After the coupling the elements, the body is thinned through a lower surface. A portion of the insulating layer in the vias is removed and the electrically conductive layer is coupled to a substrate.Type: GrantFiled: May 30, 2007Date of Patent: November 30, 2010Assignee: Intel CorporationInventors: Sriram Muthukumar, Raul Mancera, Yoshihiro Tomita, Chi-won Hwang
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Patent number: 7793250Abstract: A method for developing a wiring design for a complex system includes creating a master wire harness network (MWHN) within pathway space reservations of a pathway space-reservation network of the complex system. In this regard, the MWHN can comprise a model of possible wiring pathways between equipment of the complex system, and can include wire harness elements interconnecting termination device elements. The method can also include importing a subsystems definition capable of being represented by interconnections between the equipment. Thus, one or more logical net harnesses (LNHs) can be created based upon the MWHN and the subsystems definition. The LNH, then, can comprise a collection of interconnections routed within the MWHN. One or more logical wire harnesses (LWHs) can be created based upon the LNHs, after which one or more end-item configurations (EICs) can be created based upon the LWHs.Type: GrantFiled: December 19, 2005Date of Patent: September 7, 2010Assignee: The Boeing CompanyInventors: Satpal Saini, Ronald G. Fonden, Patrick H. Riedl, Sewon Hong, Teresa A. Moore, Paul E. Shappell
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Publication number: 20100156251Abstract: The invention relates to a method for producing a piezoelectric actuator in which a metallization paste is applied to a sintered piezoelectric stack and a flexible metal electrode is arranged on top of the paste. In a subsequent baking or firing step, a base metallic coating is formed from the metallization paste, whereby the base coating is permanently connected to the piezoelectric stack and to the flexible metal electrode. Alternatively, the metallization paste can be applied to a green body which is subsequently sintered so that a first layer of a base metallic coating is formed in the sintering step. A metallization paste is applied to the first layer in a similar manner and a flexible metal electrode is arranged thereon, whereby the metal electrode becomes fixed during a second baking step.Type: ApplicationFiled: April 18, 2007Publication date: June 24, 2010Inventors: Eugen Hohmann, Stefan Henneck, Immanuel Fergen
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Patent number: 7740725Abstract: This invention is related to thick film conductor compositions comprising electrically conductive gold powder, one or more glass frit or ceramic oxide compositions and an organic vehicle. It is further directed to the composition's uses for LTCC (low temperature co-fired ceramic) tape, for fabrication of multilayer electronic circuits and in high frequency microelectronic applications.Type: GrantFiled: December 7, 2007Date of Patent: June 22, 2010Assignee: E.I. Du Pont De Nemours and CompanyInventors: Patricia J. Ollivier, Kenneth Warren Hang
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Publication number: 20100146781Abstract: Method for connecting the conductive surfaces of circuit boards, especially a circuit board equipped with at least two conductive surfaces separated by an insulator layer and with holes, or for creating conductors on a board in a manner that conducts electricity. In the method, a metal or metal alloy, in a powder form, is fed into and the powder is sintered using a laser in order to create a unified conductive structure.Type: ApplicationFiled: May 29, 2008Publication date: June 17, 2010Applicant: FINNISH ENVIRONMENT TECHNOLOGY OYInventors: Antti Salminen, Rauno Holappa
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Patent number: 7712210Abstract: A method of making a printed circuit board in which at least two circuitized substrates are aligned and bonded together (e.g., using lamination). A gasket is provided on one of these and a facing circuitized portion on the other. The gasket forms an effective seal about the circuitized portion to prevent heated dielectric material from contacting the circuitry. After bonding, parts of the bonded structure, including the gasket, are removed to leave a projecting edge portion having circuitry thereon. This edge portion is then adapted for being positioned within an edge connector.Type: GrantFiled: June 7, 2007Date of Patent: May 11, 2010Assignee: Endicott Interconnect Technologies, Inc.Inventors: Thomas R. Miller, Duane A. Stanke, Robert J. Testa
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Publication number: 20100096178Abstract: A non-shrinkage ceramic substrate includes: a ceramic laminated body formed by laminating a plurality of green sheets; an electrode part including a via electrode penetratingly formed at the ceramic laminated body and an outer electrode formed on a surface of the ceramic laminated body and electrically connected with the via electrode; and an interface part formed between the ceramic laminated body and the electrode part to prevent an electrical connection between the electrodes from weakening.Type: ApplicationFiled: June 4, 2009Publication date: April 22, 2010Inventors: Jin Waun KIM, Seung Gyo Jeong
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Patent number: 7698812Abstract: A method for forming a ceramic laminate ceramic laminate from first and second sheets of ceramic material, the sheets having a first and a second surface, wherein the first ceramic material has a different coefficient of thermal expansion than the second ceramic material and the outer layers comprises ceramic materials having substantially the same thermal properties, comprising (a) heating the first and the second sheets of ceramic material; (b) stacking the first and the second sheets of ceramic material wherein the second surfaces are opposed to one another to provide stacked sheets; and (c) pressing the stacked sheets and forming the ceramic laminate.Type: GrantFiled: October 14, 2005Date of Patent: April 20, 2010Assignee: Lexmark International, Inc.Inventors: Douglas Campbell Hamilton, Jerry Wayne Smith, Larry Earl Stahlman, Kiyoshi Mizushima, Hisakazu Hujimoto, Makoto Aoki
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Patent number: 7698813Abstract: A method for fabricating a conductive blind via of a circuit substrate including the following steps is provided. First, the circuit substrate including a first dielectric layer, a patterned circuit layer and a second dielectric layer are provided. The patterned circuit layer including at least a capture pad is disposed between the first dielectric layer and the second dielectric layer. Next, a blind via exposing the capture pad is formed in the second dielectric layer. Then, an electroless plating process is performed to form an electroless copper layer on the capture pad and an inner wall of the blind via. Next, the electroless copper layer on the capture pad is removed. Finally, the blind via is filled with a conductive material to form the conductive blind via.Type: GrantFiled: December 21, 2006Date of Patent: April 20, 2010Assignee: Advanced Semiconductor Engineering, Inc.Inventor: Te-Chun Wang
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Patent number: 7676919Abstract: A method for forming a via in a printed circuit board is disclosed, which via allows for the passage of a signal from one signal plane to another in the (PCB), and in so doing transgresses the power and ground planes between the signal planes. The method comprises forming a first conductive layer on a first side of a circuit board, and forming a second conductive layer on a second side of the circuit board; forming a first hole in the first side of the circuit board; forming a first cylinder on vertical edges of the first hole and in contact with the first conductive layer; forming a second hole in the second side of the circuit board; forming a second cylinder on vertical edges of the first hole, wherein the second cylinder is surrounded by first cylinder and in contact with the second conductive layer; and forming a via in the circuit board, wherein the via is surrounded by the second cylinder.Type: GrantFiled: September 19, 2006Date of Patent: March 16, 2010Assignee: Micron Technology, Inc.Inventors: Shiyou Zhao, Houfei Chen, Hao Wang
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Patent number: 7650694Abstract: Embodiments include electronic device substrates and methods for forming the same. A method for forming a package comprising a multilayer substrate includes forming a stack of a plurality of dielectric layers comprising a ceramic material, the stack including upper and lower dielectric layers. The method also includes providing a plurality of metallization lines on the dielectric layers in the stack. The method also includes forming a plurality of vias in the dielectric layers, the vias formed to include electrically conductive material therein. A first metal layer is formed on the upper dielectric layer, and a second metal layer is formed on the lower dielectric layer. The first metal layer and the second metal layer are each formed to be at least 250 ?m thick. Other embodiments are described and claimed.Type: GrantFiled: June 30, 2005Date of Patent: January 26, 2010Assignee: Intel CorporationInventor: Washington M. Mobley
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Publication number: 20090277007Abstract: The invention concerns a method for forming a conductive pattern on an insulating substrate and a related apparatus. In the method, particle-type conductive matter is transferred onto a surface of the substrate and the particle-type conductive matter is at least partially sintered at elevated temperature and pressure in order to convert the particle-formed pattern into a continuously conducting pattern affixed to the substrate. According to the invention, the conductive matter is transferred in the form of a predefined pattern, and the sintering is carried out by using a nip comprising two opposing nip members between which the substrate is fed. The method provides an efficient way of making high-resolution conductor structures at low temperatures.Type: ApplicationFiled: July 6, 2007Publication date: November 12, 2009Applicant: Oy Keskuslaboratorio-Centrallboratorium ABInventors: Juha Maijala, Juha Merta, Sanna Lehti
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Patent number: 7614146Abstract: The present invention provides a circuit board structure and a method of fabricating circuit board structure the same, the circuit board structure consisting of a carrier board having a first surface and an opposed second surface, the carrier board being formed with at least one through hole penetrating the first and second surfaces; a conductive pillar formed in the through hole by electroplating; and a first circuit layer and a second circuit layer respectively formed on the first and second surfaces of the carrier board, the first and second circuit layers being electrically connected to the two end portions of the conductive pillar, thereby reducing spacing between adjacent conductive pillars of the carrier board and achieving high density circuit layout.Type: GrantFiled: October 4, 2007Date of Patent: November 10, 2009Assignee: Phoenix Precision Technology CorporationInventor: Shih-Ping Hsu
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Patent number: 7578058Abstract: A multilayer ceramic substrate having a cavity is formed by the steps of laminating a plurality of ceramic green sheets including ceramic green sheets having through holes corresponding to the cavity to form a multilayer body, pressing the multilayer body and firing the pressed body. At this time, a shrinkage suppression green sheet is laminated on the surface of the a ceramic green sheet constituting the outermost layer of the multilayer body, and a shrinkage suppression green sheet piece is disposed on the ceramic green sheet exposed to the bottom of the cavity in accordance with the shape of the cavity. A burnable sheet is further disposed on the shrinkage suppression green sheet piece. Before the pressing step, an embedded green sheet separate from the ceramic green sheets (portion separated by inserting a cut) is disposed on the shrinkage suppression green sheet piece or the burnable sheet so that it is filled in the cavity. After the firing step, the embedded green sheet fired is removed.Type: GrantFiled: April 18, 2006Date of Patent: August 25, 2009Assignee: TDK CorporationInventors: Kenji Endou, Kiyoshi Hatanaka, Masaharu Hirakawa, Haruo Nishino, Hideaki Fujioka
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Patent number: 7480988Abstract: A method and apparatus suitable for forming hermetic electrical feedthroughs in a ceramic sheet having a thickness of ?40 mils. More particularly, the method yields an apparatus including a hermetic electrical feedthrough which is both biocompatible and electrochemically stable and suitable for implantation in a patient's body. The method involves: (a) providing an unfired, ceramic sheet having a thickness of ?40 mils and preferably comprising >99% aluminum oxide; (b) forming multiple blind holes in said sheet; (c) inserting solid wires, preferably of platinum, in said holes; (d) firing the assembly of sheet and wires to a temperature sufficient to sinter the sheet material but insufficient to melt the wires; and (e) removing sufficient material from the sheet lower surface so that the lower ends of said wires are flush with the finished sheet lower surface.Type: GrantFiled: March 30, 2001Date of Patent: January 27, 2009Assignee: Second Sight Medical Products, Inc.Inventors: Jerry Ok, Robert J. Greenberg
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Patent number: 7467448Abstract: Disclosed are a piezoelectric ceramic structurally crystal-oriented through the crystallizing control of an amorphous material under an electric field and a method of manufacturing the same. The amorphous material is applied with an electric field to produce the crystal-oriented piezoelectric ceramic. The material is amorphous Li2B4O7 consisting of Li2O and B2O3 in a ratio of 1:2, and is employed in information technology, device technology, mechanical technology and so forth.Type: GrantFiled: May 13, 2005Date of Patent: December 23, 2008Assignee: Key Sung Metal Co., Ltd.Inventors: Yong Suk Yang, Su Jae Kim, Jong Soo Kim
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Publication number: 20080282537Abstract: The present invention relates to a method for forming a wiring of a printed circuit board and more particularly, to a method including: preparing a base film; forming a wiring pattern with ink including metal nanoparticles on the base film by printing; and forming a wring by the induction heating of the base film on which the wiring pattern is formed. The method of the present invention which minimizes the thermal strain and thermal decomposition of a base film, provides an appropriate sintering process of wirings, shortens the manufacturing process, and exhibits excellent mechanical strength is provided by using the induction heating.Type: ApplicationFiled: May 9, 2008Publication date: November 20, 2008Inventors: Kwi-Jong Lee, Young-Il Lee, Byung-Ho Jun, Joon-Rak Choi, In-Keun Shim
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Patent number: 7442097Abstract: A male contact portion, a female contact portion, a clamp portion where an electric wire is clamped for connection, a crimp portion where an electric wire is crimped and a piercing portion where an electric wire is pierced to be crimped are formed separately, whereby one of the male contact portion and the female contact portion is selected according to an application and one of the clamp portion, the crimp portion and the piercing portion is selected according to the application, and a connecting portion of the selected electric contact part and a connecting portion of the selected wire connection part are superposed on each other so as to join the selected electric contact making point and the selected wire connection part together.Type: GrantFiled: January 10, 2008Date of Patent: October 28, 2008Assignee: Yazaki CorporationInventor: Hideto Kumakura
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Publication number: 20080256792Abstract: A terminal insertion apparatus having a wire holding unit holding two wires, each wire having a terminal, a connector holding unit holding a connector housing having at least two holes for receiving terminals, and a terminal insertion head is disclosed. The terminal insertion head has a wire gripping unit having a first holder and a second holder. The first holder and second holder are movable in a vertical direction toward and away from the wire holding unit and are movable in a horizontal direction toward and away from the connector holding unit. The first holder has an outer grip and an inner grip that together hold one of the two wires while the second holder has an outer grip and an inner grip that together hold the remaining of the two wires.Type: ApplicationFiled: December 6, 2007Publication date: October 23, 2008Inventors: Koji Imai, Minoru Abe, Jun Funakawa, Koichi Nakajima, Daisuke Toma, Hirohide Miyazaki
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Patent number: 7430800Abstract: A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.Type: GrantFiled: June 6, 2005Date of Patent: October 7, 2008Assignee: International Business Machines CorporationInventors: Anand Haridass, Andreas Huber, Bao G. Truong, Roger D. Weekly
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Publication number: 20080223606Abstract: A chip-mounted substrate includes a chip electronic component on a ceramic substrate having surface electrodes. The chip electronic component includes a ceramic sintered compact defining an element assembly and terminal electrodes. The surface electrodes of the ceramic substrate are integrated with the corresponding external terminal electrodes by sintering.Type: ApplicationFiled: May 25, 2005Publication date: September 18, 2008Applicant: MURATA MANUFACTURING CO., LTD.Inventors: Takayuki Tsukizawa, Tetsuya Ikeda, Osamu Chikagawa
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Publication number: 20080164053Abstract: A ceramic electronic component achieves a sufficient drop resistance strength even when terminal electrodes are formed with a higher density. The ceramic electronic component includes a ceramic laminate including ceramic laminates which are laminated to each other, first terminal electrodes disposed in a peripheral portion of a bottom surface of the ceramic laminate, catch pad electrodes arranged in the ceramic laminate so as to face the respective first terminal electrodes, and sets each including at least two first via hole conductors, which electrically connect the first terminal electrodes and the respective catch pad electrodes.Type: ApplicationFiled: January 10, 2008Publication date: July 10, 2008Applicant: MURATA MANUFACTURING CO., LTD.Inventors: Daigo Matsubara, Osamu Chikagawa
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Publication number: 20080149374Abstract: Plural thermoplastic resin films, each having a circuit pattern formed thereon, are laminated. Via-holes filled with conductor past are formed in the thermoplastic films to electrically connect neighboring layers. The laminated body is pressed under heat between a pair of hot press plates to thereby form an integral body of multi-layer circuit board. To apply a uniform pressure to the laminated body in the pressing process, a projected portion formed on a pressure-adjusting sheet is pushed against a portion of the laminated body where the number of laminated circuit patterns is smaller than other portions. In this manner, the plural thermoplastic films are uniformly bonded together, and the paste in the via-holes is sufficiently converted into an alloy. Thus, reliability of the laminated multi-layer circuit board is enhanced.Type: ApplicationFiled: July 31, 2007Publication date: June 26, 2008Applicant: DENSO CORPORATIONInventors: Toshikazu Harada, Kouji Kondo
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Patent number: 7386934Abstract: Double photolithography is used to produce an under-layer of protective and filtering photoresist over a substrate that will have channels milled with a FIB. Secondary layers are applied with precision on top of the first layer in order to define the precise patterns to be milled and to provide targeting and alignment fiducials.Type: GrantFiled: January 26, 2006Date of Patent: June 17, 2008Assignee: Advanced Research CorporationInventors: Matthew P. Dugas, Joseph Tersteeg
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Patent number: 7383621Abstract: A piezoelectric contains comprises a plurality of piezoelectric particles made from a piezoelectric material such as lead titanate zirconate and a dielectric made from a dielectric material, such as a composite perovskite compound, having a higher dielectric constant then the piezoelectric material, the dielectric existing in gaps between the piezoelectric particles. When poling to produce a piezoelectric ceramic, the poling is uniformly performed, and nearly all of the electric field is applied to the piezoelectric particles. Thus, the dispersion of the piezoelectric properties can be reduced, and the piezoelectric properties can be enhanced.Type: GrantFiled: May 2, 2006Date of Patent: June 10, 2008Assignee: Murata Manufacturing Co., Ltd.Inventor: Mitsuru Sube
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Patent number: 7356917Abstract: A multi-layer printed circuit board includes an insulation substrate; a surface conductive pattern disposed on a surface of the insulation substrate; and an inner conductive pattern embedded in the insulation substrate. The surface conductive pattern has a surface roughness on an insulation substrate side, the surface roughness of the surface conductive pattern being larger than that of the inner conductive pattern.Type: GrantFiled: April 28, 2005Date of Patent: April 15, 2008Assignee: DENSO CORPORATIONInventors: Toshikazu Harada, Koji Kondo
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Patent number: 7356911Abstract: A method for producing an insulated wire having a cross section of a desired shape, in which a conductor having a cross section of a desired shape is coated with an insulating film, which method comprises: supplying a raw conductor while passing through a rolling unit composed of at least one pair of rolling rolls that are capable of freely rotating without a drive mechanism and that have a desired shape, thereby forming a conductor having a cross section of a desired shape; and coating the conductor with an insulating film.Type: GrantFiled: June 27, 2005Date of Patent: April 15, 2008Assignee: The Furukawa Electric Co., Ltd.Inventors: Toshinobu Harada, Masaki Sugiura, Satoshi Saitou
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Patent number: 7346982Abstract: A method is directed towards fabricating a printed circuit board (PCB) having a thin core layer. In the method, a substrate, where a copper foil is formed on a release film and a prepreg, is employed as a base substrate and a core insulating layer is removed after the fabrication of the PCB, thereby reducing the thickness of the final product.Type: GrantFiled: March 22, 2005Date of Patent: March 25, 2008Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Chong Ho Kim, Dong Kuk Kim, Hyo Soo Lee, Young Hwan Shin
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Patent number: 7340823Abstract: Embodiments include a method for forming a head suspension assembly. A spacer layer is formed in or on a silicon wafer. A transfer film including an opening defining the shape of a slider support membrane is provided, and the opening is filled with a resin material. The transfer film with the resin material therein is positioned over the silicon wafer so that at least a portion of the resin material is positioned adjacent to the spacer layer. The resin material is baked to form a glassy carbon material. The spacer layer is etched to form a trench in the silicon wafer adjacent to the glassy carbon material, and a slider is positioned on the glassy carbon material over the trench.Type: GrantFiled: February 27, 2004Date of Patent: March 11, 2008Assignee: Hitachi Global Storage Technologies Netherlands B.V.Inventor: Jeffrey S. Lille
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Patent number: 7334325Abstract: The invention relates to an apparatus and method for improving coupling across plane discontinuities on circuit boards. A circuit board includes a discontinuity, e.g., a split, slot, or cutout, formed on a voltage reference plane. A conductive layer overlies the discontinuity. The conductive layer has a first portion connected to the underlying reference plane and a second portion spanning the discontinuity. The first portion is connected to the reference plane using a slot or vias. And the conductive layer has a third portion extending over the reference plane but remaining disconnected from it. The conductive layer might be graphite or carbon black.Type: GrantFiled: November 16, 2004Date of Patent: February 26, 2008Assignee: Intel CorporationInventors: Weston Roth, Jayne L. Mershon, Xang Moua, Jason A. Mix
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Patent number: 7334323Abstract: A method of making a circuitized substrate which includes a high temperature dielectric material in combination with a low temperature conductive paste, the paste including an organic binder component and at least one metallic component. The flakes of the metallic component are sintered to form a conductive path through the dielectric when the dielectric is used as a layer in the substrate.Type: GrantFiled: July 11, 2005Date of Patent: February 26, 2008Assignee: Endicott Interconnect Technologies, Inc.Inventors: Frank D. Egitto, Voya R. Markovich, Luis J. Matienzo
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Patent number: 7328505Abstract: A multilayer circuit board that has electrodes only on one surface is manufactured as follows. A plurality of conductor layers are formed on a resin film made of thermoplastic resin to form a single-sided conductor layer film. Then, a plurality of via-holes 24, which are bottomed by the conductor layers, are formed in the resin film. Then interlayer connecting material is packed in the via-holes 24 to form a single-sided conductor layer film having the interlayer connecting material. A plurality of single-sided conductor layer films are formed and stacked such that surfaces having the conductor layers face in the same direction. Then, the single-sided conductor layer films are pressed and heated to complete the multilayer circuit board. The multilayer circuit board is formed by using only the single-sided conductor layer films and pressing once, so the manufacturing process is simplified.Type: GrantFiled: May 11, 2004Date of Patent: February 12, 2008Assignee: DENSO CORPORATIONInventor: Koji Kondo
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Patent number: 7316063Abstract: A method of fabricating a substrate is disclosed. Apertures are formed in a substrate blank. A conductive layer is formed on opposing surfaces of the substrate, as well as inside the apertures. Conductive elements are defined on one or both opposing surfaces by masking and etching. Additional layers of conductive materials may be used to provide a barrier layer and a noble metal cap for the conductive elements. The methods of the present invention may be used to fabricate an interposer for use in packaging semiconductor devices or a test substrate. Substrate precursor structures are also disclosed.Type: GrantFiled: January 12, 2004Date of Patent: January 8, 2008Assignee: Micron Technology, Inc.Inventors: Warren M. Farnworth, Steven M. McDonald, Nishant Sinha, William M. Hiatt
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Patent number: 7287321Abstract: Two types of resin films are prepared for manufacturing a multi-layer board containing a chip component. A fist type has a via hole for the chip component to be inserted into, while a second type does not have the via hole. Resin films including the two types are piled before the chip component is inserted. At least a given resin film of the first type has a via hole provided with protruding members. Of the protruding members, opposing protruding members form a gap between their tips. This gap is shorter than an outer dimension of the inserted chip component. The chip component crushes portion of the tips of the protruding members while being pressed and inserted into the via hole in the given resin film.Type: GrantFiled: August 26, 2005Date of Patent: October 30, 2007Assignee: DENSO CORPORATIONInventors: Satoshi Takeuchi, Motoki Shimizu
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Patent number: 7275309Abstract: A method of manufacturing an electrical-resistance heating element includes forming sintered ceramics or calcined ceramics, forming an electrode on the sintered ceramics or the calcined ceramics, and forming a ceramic base material having mainly a high melting point metal on the electrode embedded therein, thereby forming a heating element with built-in electrode.Type: GrantFiled: July 30, 2004Date of Patent: October 2, 2007Assignee: NGK Insulators, Ltd.Inventors: Hiroto Matsuda, Kazuhiro Nobori, Yutaka Mori
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Patent number: 7243424Abstract: An object of the invention is to connect different dielectrics electrically to each other in the direction of main surface of a sheet in a multilayer ceramic substrate and to increase the degree of flexibility in design and make the multilayer ceramic substrate compact in size. A multilayer ceramic substrate in accordance with the invention is formed of a plurality of laminated ceramic substrates including such a composite ceramic substrate of different materials that is made by inserting the second ceramic substrate in a pounched-out portion made in the first ceramic substrate and by planarizing its top and bottom surfaces, wherein a conductive layer is formed in a portion across a boundary between the first ceramic substrate and the second ceramic substrate of the interface of the composite ceramic substrate of different materials.Type: GrantFiled: February 17, 2005Date of Patent: July 17, 2007Assignee: TDK CorporationInventors: Kiyoshi Hatanaka, Haruo Nishino, Hideaki Ninomiya
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Patent number: 7237335Abstract: A method and apparatus are provided for servicing a telecommunication junction box. The method enables a reduced number of tools to be utilized to service a telecommunication junction box.Type: GrantFiled: February 25, 2005Date of Patent: July 3, 2007Inventor: John C. Stuart
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Patent number: 7231712Abstract: A module includes a ceramic substrate, first and second electrodes provided on the ceramic substrate, a component having third and fourth electrodes connected to the first and second electrodes, respectively, and a resin filled in a space between the component and the ceramic substrate. The ceramic substrate has a surface thereof having a recess formed therein. The first and second electrodes are provided on the surface of the ceramic substrate so that the recess is located between the first and second electrodes. The component is located over the recess and spaced from the ceramic substrate with a space including the recess. The space including the recess is filled with the resin. The module allows each component to be surface mounted at higher bonding strength, thus preventing short-circuit between the electrodes on the substrate and improving the operation reliability.Type: GrantFiled: September 29, 2004Date of Patent: June 19, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Ryuichi Saito, Hiroshi Kagata, Masaaki Katsumata
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Patent number: 7200927Abstract: A wiring transfer sheet including a carrier base and a wiring layer formed thereon is produced so that an exposed area of a surface of the carrier base on which the wiring layer is formed has a plurality of concavities. By transferring the wiring layer to an electrically insulating substrate with this wiring transfer sheet, convexities which are complementary to the concavities are formed on the electrically insulating substrate. The convexities improve adhesion between a wiring board and a resin stacked thereon. Therefore, the wiring board thus obtained has surface coplanarity suitable for mounting a semiconductor bare chip and an electronic component as a whole, and a microscopical surface structure which adheres to a material stacked thereon.Type: GrantFiled: January 16, 2004Date of Patent: April 10, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Hideki Higashitani
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Patent number: 7174632Abstract: A circuit board including a desired number of electrically insulating layers and wiring layers laminated alternately, and an inner via hole for securing an electrical connection between the wiring layers by compressing and hardening a conductive paste including a conductive particle and a resin. In the electrically insulating layer, a porous sheet is provided a resin sheet at least one surface, and the porous sheet is not impregnated with a resin at least at a central portion. A through hole penetrating the electrically insulating layer in the direction of the thickness of the electrically insulating layer is filled with a conductive paste including a conductive particle and a resin, and pores that are present inside the porous sheet are filled with laminated resin. The average hole diameter of the pores inside the porous sheet may be smaller than the average particle size of the conductive particle.Type: GrantFiled: January 9, 2004Date of Patent: February 13, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Yoshihiro Kawakita, Daizo Andoh, Fumio Echigo, Tadashi Nakamura
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Patent number: 7171746Abstract: A process is described in which surfaces of foamed plastics are provided with electrical conductor tracks, with the aid of selectively ablating processes. The process permits low-cost production of moldings from plastic with conductor tracks integrated on the surface. The products of the process may be used in the electrical and electronics industries, for example.Type: GrantFiled: January 16, 2004Date of Patent: February 6, 2007Assignee: Ticona GmbHInventors: Frank Reil, Stefan Diel
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Patent number: 7162794Abstract: A multilayer integrated substrate includes breaking grooves arranged in a grid pattern so as to section the main surface of the substrate into a plurality of blocks, and also includes fracture-preventing conductor films arranged so as to cross the breaking grooves. The fracture-preventing conductor films contain a metal component that prevents undesirable fracturing of the multilayer integrated substrate along the breaking grooves.Type: GrantFiled: January 22, 2003Date of Patent: January 16, 2007Assignee: Murata Manufacturing Co., Ltd.Inventors: Norio Sakai, Kazuhiro Iida
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Method of mounting electronic component on substrate without generation of voids in bonding material
Patent number: 7159309Abstract: When an electronic component is mounted on a substrate, the electronic component is first placed on the substrate with a solid support interposed between the electronic component and the substrate. The solid support serves to space a terminal conductor of the electronic component from a corresponding terminal pad on the substrate. A conductive bonding material is then melted on the terminal pad. The melted conductive bonding material gets exposed to the peripheral atmosphere over a larger area. Even if a bubble is generated within the melted conductive bonding material, the bubble is allowed to easily get out of the melted conductive bonding material. Removal of the gas is promoted in the melted conductive bonding material. The solid support is subsequently melted. The electronic component is moved down toward the substrate, thereby contacting the terminal conductor with the melted conductive bonding material on the corresponding terminal pad.Type: GrantFiled: February 12, 2002Date of Patent: January 9, 2007Assignee: Fujitsu LimitedInventors: Tsuyoshi Yamamoto, Mitsuo Suehiro, Hiroshi Yamada -
Patent number: 7127809Abstract: An LTCC module includes a base on one or more surfaces for receiving one or more external components to be attached to the module. A base is formed of a plurality of layers of metallization in a predetermined pattern. The layers include an adhesion layer on the LTCC module surface, with one or more intermediate layers, followed by a top layer. The module is fired with each application of the layers at a reduced temperature lower than the normal cofiring temperature of the LTCC module, but of sufficient value to partially sinter the layers. After the last applied top layer, the module is fired once at an elevated temperature to fully sinter the layers.Type: GrantFiled: March 18, 2004Date of Patent: October 31, 2006Assignee: Northrop Grumman CorporationInventors: Cynthia W. Berry, Alex E. Bailey, Robert Fisher, Tapan K. Gupta, Daniel Brosey, Steve M. Smalley, William A. Thomas
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Patent number: 7127799Abstract: The present invention provides a method for assembling a head gimbal assembly useful in a hard disk drive and for testing such an assembly. In a method in accord with the present invention a head/slider is mounted to a circuited gimbal in an automated assembly machine. Following this step the head/slider circuited gimbal assembly will be subjected a dynamic electrical test with those head/slider circuited gimbal assemblies not passing being sorted from the lot. Following this step the head/slider circuited assembly will be attached to a suspension.Type: GrantFiled: February 11, 2002Date of Patent: October 31, 2006Assignee: Applied Kinetics, Inc.Inventors: Mark T. Girard, Ryan A. Jurgenson, Susan June Livermore, legal representative, David R. Swift, Joseph P. Tracy, Roger R. Livermore, deceased
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Patent number: 7124502Abstract: The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low-noise high-power distribution layers in a single mechanically stable board.Type: GrantFiled: August 11, 2004Date of Patent: October 24, 2006Assignee: Force10 Networks, Inc.Inventor: Joel R. Goergen
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Patent number: 7082669Abstract: A two-phase rotary encoder is provided which includes a substrate for the encoder which is double-faced and has a copper-foil-bonded substrate etched thereon, a first ring-shaped electrode pattern and a second ring-shaped electrode pattern formed concentrically around a center hole on the substrate, a smooth, level ring-shaped comb electrode pattern formed on an outermost periphery of the substrate, wiring patterns which cover the electrode patterns through each of external connecting terminals provided on the substrate, and a common external connecting terminal provided on an edge of the substrate, formed on a surface thereof via the center hole or a through hole. The rotary encoder further includes a resin-molded case, a shaft, a gear-shaped rotor, a click mechanism and a tact switch mechanism.Type: GrantFiled: June 27, 2003Date of Patent: August 1, 2006Assignee: Tsubame Musen, Inc.Inventor: Masao Imamura