Abstract: Remote indication devices are each a combination of electrical parameter measurement circuitry, a CPU, and a communication device. Each remote indication device is electrically or electromagnetically coupled to a power distribution circuit conductor to monitor the current flowing in the conductor. The monitored conductor may be an energized power line (“phase”), or a current return line (“neutral”). In either case, the direction of power transfer at each measurement point can also be monitored by each remote indication device. Each remote indication device processes the monitored electrical current information to convert it into a form suitable for data transmission. The information is then presented to a monitoring station. The monitoring station collects and analyzes the electrical current information from the plurality of remote indication devices and is programmed to identify one or more particular power line segments that appear to have a fault.

Abstract: An image defect inspection apparatus 1 which performs a defect detection for detecting a defect on a surface of a sample 100 by comparing corresponding portions in an image captured of the surface of the sample 100 that are supposed to be identical to each other, and a reexamination for reexamining a site at which the defect was detected in the captured image, comprises: a plurality of processor elements PE1 to PE3which perform the defect detection in parallel on regions created by dividing the captured image; and a processor unit PU1, which receives defect information in parallel from the plurality of processor elements PE1 to PE3 as information concerning individual defects detected by the processor elements PE1 to PE3 , and which outputs the defect information as a set of defect information.

Abstract: The container inspection system operates globally at container handling facilities around the world and includes at least one transport apparatus located at a container handling facility having a spreader or other framework for connecting and handling cargo containers of all shapes and sizes. The transport apparatus is in communication with a computer network including several computing devices that provide to the transport apparatus comparison data including load models, load signatures, weight profile, and sensory limits related to a particular container. Sensors can be located on the spreader, inside the container, and invasively through the container and provide scanned characteristic data that is compared to the comparison data to determine a pass status or a fail status for the container. Ancillary data and authority input may be provided to the system by outside sources, such as other inspection systems and governmental entities.

Abstract: In a first aspect, a first method of testing a link between a first chip and a second chip is provided. The first method includes the steps of, while operating in a test mode, (1) transmitting test data of sufficient length to enable exercising of worst case transitions from the first chip to the second chip via the link; and (2) performing cyclic redundancy checking (CRC) on the test data to test the link. Numerous other aspects are provided.

Abstract: A status indicator indicates an operating state, including an electrical malfunction, of an electrical load that is located and controlled from locations remote from a monitoring location.

Abstract: A method to locate a fault from one end of a section of a power line utilizing measurements of current, voltage and angles between the phases at a first end of said section. Symmetrical components of currents are calculated for the current and voltage measurement at the first end. A value of impedance is calculated for an extra link between the terminals with the impedance for the positive sequence. A compensation is determined for the shunt capacitance. The zero-sequence current is determined from the healthy line of a section of parallel power lines. A distance to a fault is calculated for the parallel line section. The distance to the fault from the first end is calculated. The fault is located utilizing the calculate distances.

Abstract: A method for locating a fault in three terminal power line, having sections located in front of or behind of the tap point and which assumes occurrence of the fault in at least one of those sections. Three phase currents and voltages are measured at one end of the power lines system. The amplitudes of load currents in the remaining sections of the power lines system are measured before a fault occurs. The measurements of the amplitudes of load currents are stored in the remaining sections of the power lines system. Impedance data of the network are determined. The symmetrical components approach is used when calculating the location of the fault.

Abstract: A system and method for sensing the formation of tin whiskers is presented. An assembly substrate includes whisker detectors at various locations for detecting tin whiskers in an X direction, a Y direction, and a Z direction relative to the assembly substrate. Each whisker detector includes sense traces and a trace bridge that produce “planar gaps” and “orthogonal gaps” that are smaller than trace gaps produced by other traces on the assembly substrate. As such, tin whiskers short across the planar gaps and orthogonal gaps before they short across trace gaps. When the assembly substrate is finished with processing steps, a system tester performs a continuity test on the whisker detectors. When the continuity test fails, an operator is notified to check for tin whiskers on the assembly substrate. Once shipped, a processor monitors the whisker detectors for shorts throughout the product's lifecycle.

Abstract: A polyphase power system with a system safety ground supplies a plurality of power phases over a respective plurality of power lines to power a load. A plurality of phase fault detectors of a fault detection component monitor the plurality of power lines, respectively. A phase fault detector, of the plurality of phase fault detectors, monitors a power line of the plurality of power lines. The phase fault detector outputs a threshold voltage with a voltage divider coupled with the power line. The threshold voltage is a line-to-ground voltage relative to a localized ground. A capacitor coupled between the localized ground and the system safety ground provides a direct current offset to the localized ground upon a ground fault condition. The phase fault detector compares the threshold voltage with a reference voltage to make a determination of an existence of the ground fault condition in the power line.

Abstract: Method, apparatus and computer-readable code are provided for detecting a location of an incipient ground fault in an electrical propulsion system of a relatively large land-based vehicle, such as a locomotive. The detection is performed essentially in real time and without interrupting operation of the electrical devices that make up the propulsion system (e.g., performed “on the fly”), and consequently there is virtually no degradation in the operational performance of the propulsion system.

Abstract: The present invention relates to a method to locate a fault in a section of a transmission line using measurements of current, voltage and angles between the phases at a first (A) and a second (B) end of said section. The invention is characterised by the steps of, after the occurrence of a fault along the section, calculating a distance (dA, dB) to a fault dependent on a fault current measured at one of said first and second ends and phase voltages measured at both of said first and second ends (A, B), where the distance to fault is calculated from the end (A or B) where the fault current is measured. The invention is particularly suitable when a current transformer at either of the first or second ends (A, B) is saturated. If so, then, a distance (d) to a fault is calculated dependent on a fault current measured at the non-affected end and phase voltages measured at both the affected end and the non-affected end.

Abstract: A wiring test structure includes a plurality of wiring traces configured in an interleaving spiral pattern. At least one of the plurality of wiring traces configured for open circuit testing therein, and at least a pair of the plurality of wiring traces is configured for short circuit testing therebetween.

Abstract: A method, computer program, and system for real-time signal analysis providing characterization of temporally-evolving densities and distributions of signal features of arbitrary-type signals in a moving time window by tracking output of order statistic filters (also known as percentile, quantile, or rank-order filters). Given a raw input signal of arbitrary type, origin, or scale, the present invention enables automated quantification and detection of changes in the distribution of any set of quantifiable features of that signal as they occur in time. Furthermore, the present invention's ability to rapidly and accurately detect changes in certain features of an input signal can also enable prediction in cases where the detected changes associated with an increased likelihood of future signal changes.

Abstract: A method for locating a ground fault in an electrical power distribution system includes providing a plurality of current sensors at a plurality of locations in the electrical power distribution system. The method further includes detecting a ground fault in the electrical power distribution system. Current is monitored at a plurality of locations in the electrical power distribution system via the current sensors and a test signal is introduced into the electrical power distribution system via a test signal generating device. The plurality of locations are monitored to locate the ground fault between a location at which the test signal is detected and a downstream location at which the test signal is not detected.

Abstract: The present invention provides novel methods and devices for testing/verifying the configuration of one or more microfluidic elements in a microfluidic device. In particular the methods and devices of the invention are useful in testing for blockages or the presence of air bubbles in microfluidic elements.

Abstract: A system for determining the location of a disturbance event in a power distribution system. More specifically, the present invention provides a system for determining the direction of a disturbance event at the individual meter location and a system for analyzing this data from multiple meter locations to locate the cause of the event in the power system. The system includes a power feed bus for supplying electrical signals and a circuit monitor coupled to the feed bus. The circuit monitor is responsive to detect the disturbance event by comparing a disturbance event signal with a pre-event signal on a plurality of time scales.

Abstract: In an energy-saving evaluation apparatus for evaluating energy conservation for a machine that is to be operated by a user, the energy-saving evaluation apparatus includes: a detection unit that includes a monitor device for measuring a running state of the machine, detects an operating state of the machine operated by the user through measuring the running state of the machine by the monitor device; and an evaluation unit that performs an energy-saving evaluation based on the detected operating state of the machine.

Abstract: A recyclable electric junction box applicable to automotive vehicles, of the type comprising at least one casing housing a series of circuits inside materialized in one or more printed circuit boards with a series of electroconducting tracks on at least one of its sides, and with a series of components assembled on said plates, welded on said tracks and responsible for carrying out at least one power stage and one signal stage.

Abstract: A device for testing for a wiring fault condition is disclosed. The device includes an electrical connector, a first signal generator, a second signal generator, and a user interface. The electrical connector includes first and second contacts that are configured to establish an electrical connection to the wiring. The first signal generator is in signal communication with the electrical connector, and is configured to generate a signal on the wiring and to receive a reflected signal therefrom. The second signal generator is in signal communication with the electrical connector, and is configured to generate a radio frequency signal on the wiring. The user interface is in signal communication with either or both of the first and second signal generators.

Abstract: A detection module and remote load voltage sensor determine a location of a parallel arc for a power circuit between a power source and a load in real time. The detection module provides a value of voltage from the power source. A current sensor measures a value of current flowing in the power circuit to or from the power source. The remote load voltage sensor measures a value of voltage at the load. A microprocessor determines the parallel arc location from the value of voltage from the power source, the value of current, the value of voltage at the load, and a wire resistance or conductance per unit length of the power circuit. In one case, connector resistance is accounted for. In another case, the load voltage is encoded at a predetermined frequency using a switched precision resistor near the load, thereby providing a power line carrier type communication.

Abstract: A method of fault identification on a semiconductor manufacturing tool includes monitoring tool sensor output, establishing a fingerprint of tool states based on the plurality of sensors outputs, capturing sensor data indicative of fault conditions, building a library of such fault fingerprints, comparing present tool fingerprint with fault fingerprints to identify a fault condition and estimating the effect of such a fault condition on process output. The fault library is constructed by inducing faults in a systematic way or by adding fingerprints of known faults after they occur.

Abstract: A fiber optic tester (10) broadly comprises a testing unit (16) to take measurements across two test points (27), a processing unit (18) to locate faults by analyzing the measurements, a switching unit (20) that can connect termination points (13) of a electrical circuit (12) to the test points (27) in a sequence controlled by the processing unit (18), and a fiber unit (22) to test a optical circuit (14). The tester (10) may also include an electrical harness (24) or an optical harness to connect the electrical circuit (12) to the switching unit (20) or the optical circuit (14) to the fiber unit (22). The processing unit (18) is preferably programed with interconnection information of the circuits (12, 14) and internal characteristics of the tester (10). Using the interconnection information and the internal characteristics, the processing unit (18) may accurately detect faults within the circuits (12, 14).

Abstract: The invention provides a test apparatus for testing circuit units (101a–101k) to be tested by means of a test system (100), having a connection device (102), tester channels (103a–103m) for connecting the test system (100) to the connection device (102) and receptacle units (104a–104k), having a number (n1, n2, . . . , nk) of circuit unit data channels dependent on the circuit units (101–101k) to be tested, provision being made of a changeover device (200) for changing over the tester channels (103a–103m) to the receptacle units (104a–104k), and it being possible to divide a number (m) of tester channels (103a–103m) between the number (n1, n2, . . . , nk) of circuit unit data channels in a predeterminable manner.

Abstract: A benchmarking apparatus includes an interface, storage medium containing software instructions that determine and report a performance result of a computer system. The benchmarking apparatus is a handheld device and can be provided to consumers to aid in determining the performance of one or more computer systems, for example, to aid in purchase decisions. The software instructions include a benchmark routine which is loaded onto and executed by the computer system to determine the performance result. The benchmarking apparatus can be removably coupled to a computer system, for example, through a standard computer interface such as a USB port.

Abstract: For testing a device under test (“DUT”) a test specification is converted in a computer system by a pin vector generator process, which includes generating test vectors. The DUT has numerous input pins and such a pin vector is for a signal to drive one such pin. The pin vectors are compressed and saved. Ones of the pin vectors are loaded, upon initialization of a test, into a pipeline having a series of memory stages and extending from the computer system to channel cards in a test head. The pipeline is operated in data transfer cycles, delivering W bits per cycle. The pin vectors are decompressed at the respective channel cards in decompressor read cycles. X bits are read per decompressor cycle, W being greater than X, so that the pipeline may perform its data transfer cycles less frequently than the decompressor performs its read cycles.

Abstract: Disclosed is a method for detecting a fault by using harmonics and a state transition diagram. When the fault occurs on transmission lines, the fault is detected by using harmonics and the state transition diagram. Two logic signals are outputted by using apparent impedance of a steady state characteristic and a sum of harmonics components of a transient state characteristic. Such two logic signals are used as input parameters of the state transition diagram so that the state of an electric power system is presumed based on a state transition of the electric power system. It is possible to prevent a distance relay from being malfunctioned under an increase of load and unstable voltage. The state of the electric power system is presumed by using harmonics and the state transition diagram, and the fault on the transmission line is reliably detected.

Abstract: The present invention relates to a method for calculating the distance to fault in a section of a power transmission network, which section is arranged with line terminals at both ends, each terminal including impedance relays (AA, BB), including the steps of, at the occurence of a fault; measuring the apparent impedances by each relay, measuring the relaying currents, determining the type of fault, checking whether the fault involves a fault resistance or not, and, if so, solving a quadratic equation for complex numbers, resolving the quadratic equation for the real and imaginary components, obtaining two quadratic equations for a fault distance in which the coefficients are real numbers, combining the two equations and obtaining a distance to fault, or, if not so, solving a quadratic equation for real numbers, obtaining two solutions for the distance to fault d1, d2 and comparing the solutions as 0<(d1 or d2)<1 pu, where pu is the length of transmission lines between the line terminals.

Abstract: A method for testing a core power distribution system for an integrated circuit chip which includes arranging a plurality of experiments for an integrated circuit chip, performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances, generating a schmoo diagram for each of the plurality of experiments, and analyzing the schmoo diagrams to determine whether the core power distribution system functions is acceptable at a particular frequency.

Abstract: Disclosed is a semiconductor die having a scanning area. The semiconductor die includes a first plurality of test structures wherein each of the test structures in the first plurality of test structures is located entirely within the scanning area. The semiconductor die further includes a second plurality of test structures wherein each of the test structures in the first plurality of test structures is located only partially within the scanning area. The test structures are arranged so that a scan of the scanning area results in detection of defects outside of the scanning area.

Abstract: Fault detection and power network quality monitoring are performed for a power line network using power line communications (“PLC”) signal transceiving and data processing capabilities. Power line signals are continuously received and processed to obtain signal data representative of power line network operating conditions that are expressed in the received power line signals. The harmonic content and noise signature of the signal data are evaluated with reference to known fault signature data and power line network topology properties for detecting and identifying the location of an existing or anticipated fault in the power line network and assessing power transmission quality of the network.

Abstract: An apparatus and a method for electrically testing a semiconductor wafer, the method including: (i) depositing electrical charges at certain points of a test pattern; (ii) scanning at least a portion of the test pattern such as to enhance charge differences resulting from defects; and (iii) collecting charged particles emitted from the at least scanned portion as a result of the scanning, thus providing an indication about an electrical state of the respective test structure.

Abstract: A gate comparator control panel, in accordance with the subject invention, allows a user to define up to four different gate regions that may exist on any of the live waveforms, maths waveforms, or REF waveforms. A menu for each gate controls the position of each gate and selects the source for the signal that is to be gated. All gates must be the same width. A high level application copies the gated region of a waveform into a REF memory. For example, Gate 1 would go into REF 1, gate 2 into REF2 and so on. A user-settable tolerance value is used to determine if difference between the waveforms of the gates reaches a point at which a violation is indicated. A master gate position control causes all gates to move by the same amount, thus maintaining a constant distance between them. A master gate width control causes all gates to change width.

Abstract: A printed circuit board assembly adapted for immersion cooling is disclosed. The assembly includes a first circuit board having a first device side with a first portion configured to mount a first plurality of semiconductor devices. A second circuit board having a second device side with a second portion configured to mount a second plurality of semiconductor devices is disposed in confronting parallel relationship to the first circuit board. The assembly further includes a border element interposed between the first and second boards and disposed around the respective first and second portions. The border element cooperates with the first and second boards to form a liquid-tight container. An inlet formed in the border receives an electrically nonconducting liquid that is subsequently discharged through an outlet.

Abstract: A method for evaluating the upper bound fault coverage of an integrated circuit (IC) or a portion thereof from register transfer level (RTL) description is provided. The method requires the analysis of a circuit described in RTL consisting of primary input and output pins as well as devices connected to each other and/or to the primary pins to determine the controllability and observability of each pin of the circuit to ‘stuck at zero’ and ‘stuck at one’ conditions. The upper bound fault coverage is then determined based on the ratio between the number of pins that are both controllable and observable and twice the number of pins in the circuit. The method does not require a dynamic simulation for its fault coverage assessment and hence is advantageous over other methods consuming significant time and resources.

Abstract: The invention relates to a method for detecting accidental arcs (arc tracking) on a cable (1), especially on a cable of an aircraft electrical system. According to said method, an alternating current signal (I(t)) that has been detected is sampled time-discretely and a trigonometric function (I(k)) imitating the alternating current characteristic is determined by interpolation of a number of sampling values (y(k)). The current alternating frequency (?) is then derived from this trigonometric function. The result of a comparison of the current alternating current frequency (?) and a set or reference frequency (??) is used to determine the presence of an accidental arc (ISA,IGA) and a warning signal (Sarc) is optionally generated. A device which functions according to this method is advantageously integrated into a circuit-breaker (7) for the aircraft electrical system, so that the latter is equipped to detect and deactivate accidental arcs that occur on the electrical system cable (1).

Abstract: The invention relates to a method, a computer program and a device (20) for the plausibility checking of current transformers (7) in an electrical switchgear assembly (1) and to a switchgear assembly (1) having such a device (20). According to the invention, zones (1a, 1b, 1c) bounded by current transformers (7) and possibly by open switches (3-5) are detected for an instantaneous topology of the switchgear (1), in each zone (1a, 1b, 1c) the signed current measurement signals are added and in the case of significant deviations of the current sum from zero, all current transformers (7) of the associated zone (1a, 1b, 1c) are identified as being problematic. Exemplary embodiments relate to, among other things: a warning counter (2e) for problematic current transformers (7); in the case of a defective current transformer (7), an operation with calculated currents or an automatic combining of zones (1a, 1b, 1c); and coordinating the plausibility test with switching actions.

Abstract: A self-compensating fault locator (10) broadly comprises a testing unit (16) to take measurements across two test points (18), a processing unit (20) to locate faults by analyzing the measurements, and a switching unit (22) that can connect termination points (14) of an electrical circuit (12) to the test points (18) in a sequence controlled by the processing unit (20). The fault locator (10) may also include a harness (24) to connect the electrical circuit (12) to the switching unit (22). The processing unit (20) is preferably programed with the electrical circuit's (12) interconnection information. The processing unit (20) also preferably stores internal characteristics of the fault locator (10). Using the interconnection information and the internal characteristics, the processing unit (20) may accurately locate faults within the electrical circuit (12). Additionally, the processing unit (20) may locate faults within the fault locator (10) and/or the harness (24).

Abstract: Common path distortion (CPD) is an impairment that afflicts two-way cable systems. Point contact diodes caused by metallic corrosion in the plant mix downstream signals. Some of the mixing products fall into an upstream frequency band where they interfere with upstream signals. A good way to locate the sources of CPD is to use a system that ranges the distance to source of CPD. One prior art system uses custom-built software and hardware, injects test signals into the downstream signal path, and looks for resulting mixing products on the upstream signal path. Unfortunately, some cable systems do not have any available vacant bandwidth for testing. Digital downstream signals, which are already being carried on the plant, can be used for testing by mixing them at the test location to create a local distortion signal. The local distortion signal may be processed with an actual distortion signal using cross-correlation to range a distance to a source of CPD.

Abstract: A method of precisely determining velocity of propagation and the location of a fault on an electric transmission line, using a system of high frequency transmitter and receiver combinations to monitor and detect high frequency bursts produced by the transmitters and by faults, including memory and analysis capability to store and analyze high frequency data before and after a detected fault.

Abstract: Disclosed are techniques for efficiently inspecting defects on voltage contrast test structures. Improved test structures for facilitating such techniques are also provided. In one embodiment, the methodologies and test structures allow inspection to occur entirely within a charged particle (e.g., e-beam) system, such as a step and repeat e-beam system. In a specific embodiment, a method of localizing and imaging defects in a semiconductor test structure suitable for voltage contrast inspection is disclosed. A charged particle beam based tool is used to determine whether there are any defects (e.g., open or short defects) present within a voltage contrast test structure. The same charged particle beam based tool is then used to locate defects determined to be present within the voltage contrast test structure.

Abstract: The invention relates to a method, a computer program product, a computer program and a device (20) for the plausibility checking of voltage transformers (8) in an electrical switchgear (1) as well as a switchgear (1) with such a device (20). According to the invention, a topological sub-area (1a; 1b) with several galvanically connected voltage transformers (8) is recorded for an instantaneous topology of the switchgear (1), groups of voltage transformers (8) with the same measured signals are identified and, if more than one group is present, an indication or alarm signal is generated by the substation control system (2). Amongst other things, exemplary embodiments relate to: Criteria for the production of warning or alarm messages for problematic voltage transformers (8) and/or sub-areas (1a; 1b); presentation of the results of the plausibility test; coordination of the plausibility test with switching operations.

Abstract: A method of precisely determining velocity of propagation and the location of a fault on an electric transmision line, using a system of high frequency transmitter and receiver combinations to monitor and detect high frequency bursts produced by the transmitters and by faults, including memory and analysis capability to store and analyze high frequency data before and after a detected fault.

Abstract: A fuel cell resistance test system includes a contact head having a plurality of spaced electrical contacts for contacting multiple ones of the fuel cells composing the stack. In one embodiment, a plurality of selectively actuable switches produce a short between respective pairs of adjacent ones of the electrical contacts. A processor opens each of the switches, one at a time in succession, to apply a defined voltage from a voltage source, successively across pairs of adjacent ones of the electrical contacts. A current sensor measures a resulting current and the processor or other computer determines whether a short exists based on the magnitude of the defined voltage and the magnitude of the resulting current. Alternatively, the test system may include a current source and a voltage sensor.

Abstract: The field ground fault detector of the present invention detects a ground fault that occurs in the field circuit and in any associated circuits galvanically connected to the field. The field ground fault detector discerns the ground resistance so that it can be monitored to detect gradual degradation of the ground resistance. The detector estimates the resistance of the ground fault and the location of the ground fault. The detector is able to estimate the location of the ground fault during system operation and during periods of non-operation. The invention utilizes a low frequency square wave oscillator to permit measurement of the ground fault resistance when field voltage is not applied, to insure that there are no blind spots when the field is energized, and to provide a method for estimating the ground fault resistance. The field ground detector can differentiate between ground faults that occur on the AC side form those on the DC side of the Thyristor Bridge.

Abstract: A device-under test (DUT) assembly includes a DUT board having a plurality of spine assemblies. Each spine assembly has a first outer face, a second outer face, and a first plurality of contacts on at least one of the first and second outer faces in electrical contact with a subset of the first signal lines. A connector assembly includes a plurality of clamping assemblies arranged to receive the plurality of spine assemblies. Each clamping assembly includes a first inner face, a second inner face, and a second plurality of contacts on at least one of the first and second inner faces in electrical contact with a subset of the second signal lines. Electrical connections between the first and second contacts are formed when the first and second inner faces of each clamping assembly are clamped to the first and second outer faces of the corresponding spine assembly.

Abstract: A control device for electric motors and a method for monitoring the serviceability of a transmission part arranged for transmission of torque between an electric motor and a load during operation. The method comprises the steps of initiating at least one test sequence, and sending a signal indicating an error if said at least one test sequence indicates that the serviceability of the transmission part is not acceptable and if no further test sequences are to be performed. Additionally, said at least one test sequence includes the steps of setting a rotation speed of the electric motor at a test rotation speed, which differs from the rotation speed of the electric motor immediately prior to said setting, and measuring at the electric motor, within a period starting from the setting of the rotation speed of the motor and ending when the rotation speed of the electric motor has reached the test rotation speed.

Abstract: An Addressable Electronic Switch (AES) is disclosed together with unique S/W (software) procedures for a system control to detect, locate, and isolate shorts, overloads, and other troubles, such as temporary breaks or disconnects, on a Vplex or similar 2-wire polling loop. The addressable electronic switches are placed at strategic locations throughout the polling loop, and are individually commanded by the system control to either connect or disconnect its respective branch from the rest of the polling loop, to locate and isolate a troubled area from the rest of the polling loop.

Abstract: A system and method for detecting defects in TFT-array panels is provided that improves defect detection accuracy by adjusting the thresholding parameters used to classify defective pixels when the number of defects reported by a TFT-array testing system exceeds a predetermined critical number. In a preferred embodiment, the thresholding parameters are adjusted until the number of reported defects is less than or equal to the predetermined critical number. The predetermined critical number represents a threshold number for determining if the number of reported defects is abnormally high.

Abstract: The present invention relates to a method for detecting a line-to-ground fault location in power network, and more particularly, detecting the line-to-ground fault location by direct 3-phase circuit analysis without using a symmetrical component transformation, so even in an unbalanced 3-phase circuit, the line-to-ground fault location can be accurately detected. In the method using direct 3-phase circuit analysis of this invention, inverse lemma is used to simplify matrix inversion calculations, thus the line-to-ground fault location can be easily and accurately determined even in the case of an unbalanced network without symmetrical component transformation.

Abstract: A method and apparatus for producing a fault signal are disclosed which indicate a short to ground on a polyphase power transmission line, in which, the phase currents on the power transmission line are detected by means of current transformers in order to form a sum current measured value. Furthermore, a first short to ground suspicion signal is produced if the sum current measured value is greater than a predetermined current threshold value, the phase voltages on the power transmission line are detected in order to form a residual voltage measured value, and a second short to ground suspicion signal is produced if the residual voltage measured value is greater than a predetermined voltage threshold value, and a fault signal which indicates a short to ground is produced if at least one short to ground suspicion signal is present.