Integrated Circuit Die Patents (Class 324/762.03)
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Publication number: 20130234749Abstract: In a testing apparatus, an electronic equipment to be an equipment under test; EUT is exposed to an electric field by unit of an emission electrode, and an intensity of the electric field applied to the electronic equipment during a test is fluctuated by electric field fluctuating unit. Operating characteristics of the electronic equipment are tested by generating induction charging inside the electronic equipment by the fluctuation electric field during the test. As a result, it becomes possible to test malfunction caused by a discharge phenomenon generated inside the electronic equipment, which cannot be tested with a conventional ESD testing apparatus.Type: ApplicationFiled: November 10, 2011Publication date: September 12, 2013Applicant: TOKYO ELECTRONICS TRADING CO., LTD.Inventors: Masamitsu Honda, Satoshi Isofuku, Hideki Arai
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Patent number: 8531202Abstract: A probe card analyzer mounts on a probe card in a wafer prober and a use a fixture in the wafer probe and switch electronics in place of an ATE head. Methods of testing can confirm that probe cards are operating within their specifications over large temperature ranges and the mechanical force ranges seen in real manufacturing environments. This reduces the cost and improves the accuracy and speed of analyzing probe cards and improves diagnosing problems with probe cards.Type: GrantFiled: October 10, 2008Date of Patent: September 10, 2013Assignee: VeraConnex, LLCInventors: Sammy Mok, Frank Swiatowiec, Fariborz Agahdel
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Patent number: 8519732Abstract: The invention relates to a method for monitoring the breakdown of a pn junction in a semiconductor component and to a semiconductor component adapted to carrying out said method. According to the method, optical radiation which is emitted if a breakdown occurs on a pn junction is detected by a photosensitive electronic component (8) integrated into the semiconductor component. The supply of the pn junction is controlled according to the detected radiation to prevent a complete breakdown during operation of the semiconductor component. The method according to the invention and the semiconductor component adapted thereto permit the operating range of the semiconductor component to be extended and the power output to be increased without the risk of destruction.Type: GrantFiled: January 11, 2008Date of Patent: August 27, 2013Assignee: Universitat StuttgartInventors: Erich Kasper, Michael Morschbach
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Publication number: 20130207686Abstract: In a method of testing integrated circuit devices, a parameter, such as initial voltage may first be measured. A low pass filter operation may be applied to the measured data to generate peer data. A particular integrated circuit device may be identified as failed or rejected when its measured parameter varies sufficiently relative to the peer data.Type: ApplicationFiled: February 13, 2012Publication date: August 15, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Ronald Andrew Michallick, Michael Nolan Jervis, Rex Warren Pirkle
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Patent number: 8502553Abstract: A semiconductor package test apparatus having a test head and a test handler is provided. The semiconductor package test apparatus may include an insert in which a plurality of semiconductor packages are stacked and received in an offset fashion. Further, the semiconductor package test apparatus may include a plurality of sockets located adjacent to the insert and each of the inserts may have a plurality of socket pins. The sockets have different surface levels and are aligned with the semiconductor packages.Type: GrantFiled: January 17, 2011Date of Patent: August 6, 2013Assignee: Samsung Electronics Co., Ltd.Inventor: Soon-Geol Hwang
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Publication number: 20130193997Abstract: System and method for test structure on a wafer. According to an embodiment, the present invention provides a test structure for testing an integrated circuit. For example, the test structure and the integrated circuit are manufactured on a same substrate material and the testing being conducted is in a temperature-controlled environment. The test structure includes a top structure positioned above the integrated circuit, the top structure including a first metal material, which includes a first electrical terminal and a second electrical terminal. The test structure also includes a bottom structure positioned below the integrated circuit, the bottom structure including a first silicon material. A first side structure is positioned between the top structure and the bottom structure and located next to a first side of the integrated circuit. A second side structure is positioned between the top structure and the bottom structure and located next to a second side of the integrated circuit.Type: ApplicationFiled: March 13, 2013Publication date: August 1, 2013Applicant: Semiconductor Manufacturing International (Shanghai) CorporationInventor: Semiconductor Manufacturing International (Shanghai) Corporation
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Publication number: 20130191047Abstract: An on-chip poly-to-contact process monitoring and reliability evaluation system and method of use are provided. A method includes determining a breakdown electrical field of each of one or more shallow trench isolation (STI) measurement structures corresponding to respective one or more original semiconductor structures. The method further includes determining a breakdown voltage of each of one or more substrate measurement structures corresponding to the respective one or more original semiconductor structures. The method further includes determining a space between a gate and a contact of each of the one or more original semiconductor structures based on the determined breakdown electrical field and the determined breakdown voltage.Type: ApplicationFiled: January 20, 2012Publication date: July 25, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Fen CHEN, Roger A. DUFRESNE, Timothy D. SULLIVAN, Yanfeng WANG
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Publication number: 20130169308Abstract: A test structure for an integrated circuit device includes a series inductor, capacitor, resistor (LCR) circuit having one or more inductor elements, with each inductor element having at least one unit comprising a first segment formed in a first metal layer, a second segment connecting the first metal layer to a semiconductor substrate beneath the first metal layer, and a third segment formed in the semiconductor substrate; and a capacitor element connected in series with each inductor element, the capacitor element defined by a transistor gate structure including a gate electrode as a first electrode, a gate dielectric layer, and the semiconductor substrate as a second electrode.Type: ApplicationFiled: January 4, 2012Publication date: July 4, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Xu Ouyang, Yunsheng Song, Tso-Hui Ting, Yongchun Xin
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Publication number: 20130147510Abstract: A monitoring testkey for a wafer is provided. The monitoring testkey includes a first metal oxide semiconductor (MOS) transistor having a channel extending in a first direction, a second MOS transistor having a channel extending in a second direction, a common gate pad electrically connected to gate electrodes of the first MOS transistor and the second MOS transistor, a first source pad electrically connected to source electrodes of the first MOS transistor and the second MOS transistor, a first drain pad electrically connected to a drain electrode of the first MOS transistor, and a second drain pad electrically connected to a drain electrode of the second MOS transistor. The monitoring testkey helps to improve the critical dimension uniformity and electrical characteristics uniformity of elements in a wafer.Type: ApplicationFiled: December 7, 2011Publication date: June 13, 2013Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Chin-Chun HUANG, Ji-Fu Kung, Wei-Po Chiu, Nick Chao
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Patent number: 8461859Abstract: A semiconductor device includes a common probing pad; an internal voltage generation unit having a plurality of internal voltage generation blocks configured to generate a plurality of internal voltages; and a probing voltage selection unit configured to transfer an internal voltage selected from the internal voltages to the common probing pad in response to a plurality of voltage selection signals.Type: GrantFiled: June 30, 2009Date of Patent: June 11, 2013Assignee: Hynix Semiconductor Inc.Inventor: Khil-Ohk Kang
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Publication number: 20130135004Abstract: Each chip in a three-dimensional circuit includes a pair of connections, a test signal generation circuit, and a test result judgment circuit. The connections are electrically connected with an adjacent chip. The test signal generation circuit outputs a test signal to one of the connections. The test result judgment circuit receives a signal from the other of the connections and, from the state of the signal, detects the conducting state of the transmission path for the signal. Before layering the chips, a conductor connects the connections to form a series connection, and the conducting state of each connection is detected from the conducting state of the series connection. After layering the chips, the test signal generation circuit in one chip outputs a test signal, and the test result judgment circuit in another chip receives the test signal, and thus the conducting state of the connections between the chips is tested.Type: ApplicationFiled: June 4, 2012Publication date: May 30, 2013Inventors: Takashi Hashimoto, Takashi Morimoto
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Publication number: 20130132007Abstract: Systems and methods for scanning and characterizing an integrated circuit for transient events. Embedded apparatus can detect transient events that may be incident on the integrated circuit, and moreover, identify particular nodes of the integrated circuit that are affected by the transient event. Additionally, the integrated circuit can be characterized by applying known transient pulses of varying severity to selected nodes of the integrated circuit, detecting the severity levels at which the selected nodes can fail, and storing indications pertaining to pulse severity at which selected nodes can fail. Moreover, based on the characterization, targeted protection mechanisms can be provided for nodes that are characterized as being susceptible.Type: ApplicationFiled: October 31, 2012Publication date: May 23, 2013Applicant: Pragma Design, Inc.Inventor: Pragma Design, Inc.
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Patent number: 8443246Abstract: A system and method for detecting transition delay faults decouples the test enable pins of the clock gating cells from other elements in the circuitry. The test enable pins are controlled during test mode by a unique signal, allowing the tester to independently control the clock gating logic of the circuitry. By being able to ungate the clock, the tester can ensure that the two clock pulses needed to check for transition delay faults will always be present.Type: GrantFiled: January 27, 2011Date of Patent: May 14, 2013Assignee: Marvell International Ltd.Inventor: Darren Bertanzetti
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Patent number: 8441275Abstract: An electronic device test fixture deploys a plurality of contact elements in a dielectric housing. The plumb arrangement of contact elements each include an armature or transversal configured to first depress and then slide laterally when urged downward by the external contacts of a device under test. The rotary movement of the transversal is optimized via the configuration of a surrounding forked regulator such that surface oxide deposition on the external device under test terminal is disrupted to reliably minimize contact resistance without damaging or unduly stressing the electrical junction of the device under test.Type: GrantFiled: January 13, 2011Date of Patent: May 14, 2013Assignee: Tapt Interconnect, LLCInventor: Patrick J Alladio
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Patent number: 8436639Abstract: A multiple level integrated circuit uses an array of oppositely oriented individually enabled buffers between through-silicon vias (TSVs) and a clocked flip-flop, for each of multiple signal lines that include TSVs. Applying and/or reading logic levels to and from the TSVs and associated flip-flops produces values that a logic element compares to expected values characterizing nominal operation or detects open and short circuit defects. A process associated with testing the TSVs during assembly comprises testing for short circuits and then exposing and connecting the TSVs via a conductive layer to check for open circuits.Type: GrantFiled: March 22, 2011Date of Patent: May 7, 2013Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Sandeep Kumar Goel
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Patent number: 8432181Abstract: A reconfigurable number of at-speed pulses and reconfigurable dead cycles between pulses is utilized to enhance test coverage of an Integrated Circuit. A reconfigurable number of programmable at-speed phase-locked loop clock pulses without a dead cycle is emitted through an integrated circuit. Further, a plurality of programmable at-speed phase-locked loop clock pulses is emitted through the Integrated Circuit such that a reconfigurable number of dead cycles is between the plurality of programmable at-speed phase locked loop clock pulses. In addition, data associated with the reconfigurable number of programmable at-speed phase-locked loop clock pulses is capture. Finally, data associated with the reconfigurable number of dead cycles is captured.Type: GrantFiled: July 25, 2008Date of Patent: April 30, 2013Assignee: Thomson LicensingInventor: Dinakaran Chiadambaram
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Publication number: 20130099816Abstract: An active matrix substrate includes a plurality of bus lines (1, 2) provided in a pixel region, a plurality of signal terminals (5) provided in a connection terminal region (K), connection lines (3), additional signal terminals (11), test lines (8), and switching elements (4). The switching elements (4) are divided into a plurality of groups, and can control connections between the bus lines and the test lines (8) on a group basis, and connection elements (12) that each include a diode or a switching element and connect the signal terminals (5) to each other are provided in the connection terminal region (K).Type: ApplicationFiled: June 22, 2011Publication date: April 25, 2013Applicant: SHARP KABUSHIKI KAISHAInventors: Nobuyuki Kawase, Isao Ogasawara, Kazuhide Ikuta
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Publication number: 20130093455Abstract: The disclosure describes a novel method and apparatus for testing TSVs in a single die or TSV connections in a stack of die.Type: ApplicationFiled: October 11, 2012Publication date: April 18, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventor: TEXAS INSTRUMENTS INCORPORATED
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Publication number: 20130076387Abstract: In a semiconductor device in which semiconductor chips having a number of signal TSVs are stacked, a huge amount of man-hours have been required to perform a continuity test for each of the signal TSVs. According to the present invention, no continuity test is performed directly on signal TSVs. Dummy bumps are arranged in addition to signal TSVs. The dummy bumps of the semiconductor chips are connected through a conduction path that can pass the dummy bumps between the semiconductor chips with one stroke when the semiconductor chips are stacked. A continuity test of the conduction path allows a bonding defect on bonded surfaces of two of the stacked semiconductor chips to be measured and detected.Type: ApplicationFiled: September 10, 2012Publication date: March 28, 2013Applicant: ELPIDA MEMORY, INC.Inventors: Toru ISHIKAWA, Machio SEGAWA
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Patent number: 8400181Abstract: A wafer is disclosed that includes a plurality of pipeline interconnected integrated circuit dies that form a plurality of pipelines. A plurality of dies in each pipeline is connected to receive scanned output test data from a neighboring die in a pipeline. A wafer level test access mechanism (TAM) transceiver circuitry, located outside the plurality of pipeline interconnected IC dies, is connected in common to each of the pipelines to provide input test data in a parallel fashion to the plurality of pipelines. The wafer level test access mechanism transceiver circuitry also provides output test results from each of the pipelines for evaluation by a computerized test system. In one embodiment, the wafer level test access mechanism transceiver circuitry is wireless so that it wirelessly receives test data to be passed through the multiple pipelines on a wafer and also includes wireless transmit circuitry to transmit test results from each of the pipelines.Type: GrantFiled: April 28, 2010Date of Patent: March 19, 2013Assignee: Advanced Micro Devices, Inc.Inventor: Sravan Kumar Bhaskarani
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Patent number: 8395406Abstract: An integrated circuit is provided with first and second variable delay circuits, a test data feeding circuitry, a test control circuit, and a wire-connection line. The test data feeding circuitry feeds first and second test data signals to the first and second variable delay circuits, respectively. The first and second test data signals are complement to each other. The test control circuit feeds first and second drive capability control signals to the first and second variable delay circuits to control drive capabilities of the first and second variable delay circuits. The wire-connection line provides a wire-connection for outputs of the first and second variable delay circuits.Type: GrantFiled: August 26, 2009Date of Patent: March 12, 2013Assignee: Renesas Electronics CorporationInventors: Tooru Iwashita, Masahiko Shihara, Atsushi Tangoda
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Publication number: 20130049792Abstract: A measuring device is provided, the measuring device including: a power supply to provide electric power to a chip via at least one of a chip connection and a chip-carrier connection; a chip arrangement receiving portion configured to receive a chip arrangement, the chip arrangement including a chip and a plurality of chip-to-chip-carrier connections; a detection portion including: a plate; a detection circuit coupled to the plate and configured to detect an electrical signal from the plate; wherein the plate is configured such that it covers at least part of the chip arrangement; and wherein at least one chip-carrier connection is in electrical connection with the plate.Type: ApplicationFiled: August 31, 2011Publication date: February 28, 2013Applicant: INFINEON TECHNOLOGIES AGInventor: Ming Xue
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Publication number: 20130049793Abstract: A testing structure, system and method for monitoring electro-migration (EM) performance. A system is described that includes an array of testing structures, wherein each testing structure includes: an EM resistor having four point resistive measurement, wherein a first and second terminals provide current input and a third and fourth terminals provide a voltage measurement; a first transistor coupled to a first terminal of the EM resistor for supplying a test current; the voltage measurement obtained from a pair of switching transistors whose gates are controlled by a selection switch and whose drains are utilized to provide a voltage measurement across the third and fourth terminals. Also included is a decoder for selectively activating the selection switch for one of the array of testing structures; and a pair of outputs for outputting the voltage measurement of a selected testing structure.Type: ApplicationFiled: August 31, 2011Publication date: February 28, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Fen Chen, Roger A. Dufresne, Kai D. Feng, Richard J. St-Pierre
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Patent number: 8384411Abstract: A method and device for measuring a signal of a die to be placed within a package is disclosed. At least one die as a Device Under Test (DUT) is mounted on a substrate and a chip-type measurement instrument is mounted on the substrate, or embedded into the substrate, wherein the instrument analyzes and/or processes the signal of the DUT and may provide stimulus signal to the DUT. The substrate having the DUT and the measurement instrument is mounted on a circuit board that has plural electrodes to be connected to the signal paths of the DUT and the instrument. An electrode is coupled to a standard interface port to provide the signal of the chip-type instrument to an external instrument.Type: GrantFiled: December 18, 2009Date of Patent: February 26, 2013Assignee: Tektronix, Inc.Inventors: Bart A. Mooyman-Beck, Robert J. Woolhiser, Kevin E. Cosgrove, Daniel G. Knierim
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Publication number: 20130043897Abstract: An integrated circuit configured for at-speed testing is described. The integrated circuit includes a first die. The first die includes a transition launch point. The integrated circuit also includes a second die. The second die includes a first observe point. The integrated circuit further includes a first through silicon via. The first through silicon via couples the first die to the second die.Type: ApplicationFiled: January 30, 2012Publication date: February 21, 2013Applicant: QUALCOMM INCORPORATEDInventors: Rajamani Sethuram, Karim Arabi, Sarath Chandra Kasarla
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Patent number: 8344749Abstract: A method of testing electronic assemblies including singulated TSV die attached to a ML package substrate, on a substrate carrier. The substrate carrier includes through-holes for allowing probe contact to the BGA substrate pads on a bottomside of the package substrate that are coupled to the frontside of the TSVs. Contactable TSV tips on the bottomside of the TSV die are contacted with a topside coupler that includes a pattern of coupling terminals that matches a layout of at least a portion of the TSV tips or pads coupled to the TSV tips. The topside coupler electrically connects pairs of coupling terminals to provide a plurality of TSV loop back paths. The BGA substrate pads are contacted with a plurality of probes tips that extend through the through-holes to couple to the frontside of the TSVs. Electrical testing is performed across the electronic assembly to obtain at least one test parameter.Type: GrantFiled: June 7, 2010Date of Patent: January 1, 2013Assignee: Texas Instruments IncorporatedInventors: Daniel Joseph Stillman, James L. Oborny, William John Antheunisse, Norman J. Armendariz, Ramyanshu Datta, Kenneth M. Butler, Margaret Simmons-Matthews
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Patent number: 8339152Abstract: A test structure (200) in an integrated circuit (100) includes a probe pad (210) disposed at a surface of a die (102) of the integrated circuit, a transmission gate (202) for connecting portions of an electronic circuit within the integrated circuit in response to a momentary signal applied to the probe pad, a first inverter (221) having an input coupled to the probe pad and having an output coupled to a control input of the transmission gate, and a second inverter (222) having an input coupled to an output of the first inverter and having an output coupled to another control input of the transmission gate. The output of the second inverter is coupled to the input of the first inverter. Upon power-up, the transmission gate is open. After the momentary signal is applied to the probe pad, the transmission gate closes and remains closed until power is disconnected.Type: GrantFiled: March 30, 2010Date of Patent: December 25, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Fabio Duarte De Martin, Andre Luis Vilas Boas
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Patent number: 8324922Abstract: An integrated circuit includes switching circuits for selectively connecting the bond pads to functional core logic and isolating the bond pads from second conductors, and the switch circuits for selectively connecting the bond pads to the second conductors to provide bi-directional connections between the bond pads on opposite sides of the substrate and isolating the bond pads from the functional core logic.Type: GrantFiled: August 31, 2010Date of Patent: December 4, 2012Assignee: Texas Instruments IncorporatedInventor: Lee D. Whetsel
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Patent number: 8327198Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.Type: GrantFiled: August 14, 2009Date of Patent: December 4, 2012Assignee: Intel CorporationInventors: Tina C. Zhong, Jason G. Sandri, Kenneth P. Griesser, Lori R. Borger
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Patent number: 8327201Abstract: A method of testing an integrated circuit (IC) having a plurality of dies can include receiving, within a master die of the plurality of dies of the IC, a configuration data set specifying a circuit design, wherein the circuit design is instantiated within the master die. The method can include broadcasting the configuration data set to at least one slave die, wherein the circuit design is instantiated within each slave die and receiving, within the master die, a test vector set. The method also can include broadcasting the test vector set to the at least one slave die and responsive to each die executing the test vector set, storing test output data generated by each die.Type: GrantFiled: May 5, 2010Date of Patent: December 4, 2012Assignee: Xilinx, Inc.Inventor: Andrew W. Lai
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Publication number: 20120293197Abstract: At least one N-type transistor and at least one P-type transistor separate from the digital circuit are sized to represent the total area of the corresponding type transistors in the digital circuit. The gates of the N-type transistor and P-type transistors are set to voltages according to the corresponding off-state logic levels of the digital circuit. The N-type and P-type transistors form a portion of corresponding current mirror circuits, which can provide outputs to a leakage current monitor and/or a control circuit such as a comparator that determines when leakage current for the N-type or P-type devices has exceeded a threshold. The output of the measurement/control circuit can be used to determine a temperature of and/or control operation of the digital circuit or the system environment of the integrated circuit.Type: ApplicationFiled: May 31, 2012Publication date: November 22, 2012Applicant: International Business Machines CorporationInventors: Rajiv V. Joshi, Rouwaida N. Kanj, Jente B. Kuang, Sani R. Nassif
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Publication number: 20120280708Abstract: An integrated circuit chip is provided. The integrated circuit chip includes a pad, a first resistor, a second resistor, a first switch, a second switch and a controller. The first resistor and the first switch are serially connected between the pad and a first reference voltage terminal. The second resistor and the second switch are serially connected between the pad and a second reference voltage terminal. The controller selectively turns on and off the first and second switches according to an error determining mechanism. The error determining mechanism determines whether an error condition associated with the pad is present.Type: ApplicationFiled: October 24, 2011Publication date: November 8, 2012Applicant: MStar Semiconductor, Inc.Inventors: CHIH-CHENG KU, Shan-Cheng Sun, You-Kuo Wu
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Patent number: 8286043Abstract: A system for testing a logic circuit which has two or more test routine modules. Each module contains a set of instructions which is executable by (a part of) the logic circuit. The set forms a test routine for performing a self-test by the part of the logic circuit. The self-test includes the part of the logic circuit testing itself for faulty behavior, and the part of the logic circuit determining a self-test result of the testing. The system includes a test module which can execute a test application which subjects the logic circuit to a test by performing the self-test on at least a part of the logic circuit by causes the part of the logic circuit to execute a selected test routine, and determining, by the test module, an overall test result at least based on a performed self-tests. The test module includes a control output interface for activates the execution of the a selected test routine. A second test module input interface can receive the self-test result from a selected test routine.Type: GrantFiled: February 16, 2007Date of Patent: October 9, 2012Assignee: Freescale Semiconductor, Inc.Inventors: Oleksandr Sakada, Florian Bogenberger
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Publication number: 20120249178Abstract: A monitoring method of a three-dimensional integrated circuit (3D IC) is provided, wherein the method includes: providing a plurality of TSVs, providing a plurality of inverters; connecting the inverters with the plurality of TSVs as a circuit loop; enabling the circuit loop to oscillate; measuring an output signal on an output end of one of the plurality of inverters; and determining the manufacturing state of the plurality of TSVs of the 3D IC based on the output signal and apparatus using the same.Type: ApplicationFiled: June 11, 2012Publication date: October 4, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Keng-Li Su, Chih Sheng Lin, Chih-Wen Hsiao
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Patent number: 8278962Abstract: There is provided a transfer circuit including a transmitter that outputs a transmission signal and a receiver that receives the transmission signal. Here, the receiver supplies to the transmitter a feedback signal for controlling a common level of the transmission signal output from the transmitter, and the transmitter controls the common level of the transmission signal output therefrom, in accordance with the feedback signal received from the receiver. The receiver includes a receiving section that operates in accordance with the transmission signal, a reference level generating section that generates a reference level representing an expected level for the common level of the transmission signal input into the receiving section, and a comparing section that compares the common level of the transmission signal input into the receiving section against the reference level and generates the feedback signal in accordance with a result of the comparison.Type: GrantFiled: February 4, 2010Date of Patent: October 2, 2012Assignee: Advantest CorporationInventors: Daisuke Watanabe, Toshiyuki Okayasu
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Patent number: 8253420Abstract: A detection circuit and one or more wires or circuit traces are included in a die. The combination is used to detect mechanical failure of the substrate, e.g. silicon after singulation of the dice from the wafer. Failures may be detected at different regions or planes within the die, and the tests may be performed during operation of the packaged die and integrated circuit, even after installation and during operation of a larger electronic device in which it is incorporated. This is especially useful for chip scale packages, but may be utilized in any type of IC package.Type: GrantFiled: December 4, 2009Date of Patent: August 28, 2012Assignee: Volterra Semiconductor CorporationInventors: Charles Nickel, Katherine Nickel, legal representative, David Lidsky, Seth Kahn
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Publication number: 20120161808Abstract: Methods and systems to measure a signal on an integrated circuit die. An on-die measurement circuit may measure an on-die signal relative to an off-die generated reference signal, which may include a series of increasing voltage steps. The on-die measurement circuit may continuously compare voltages of the on-die signal and the off-die generated reference signal, and may generate an indication when the off-die reference signal exceeds the on-die signal. The measurement circuit may generate the indication from a voltage source other than the on-die signal to be measured, and/or may generate the indication with a relatively large voltage swing. The indication may be output off-die for evaluation, such as for testing, debugging, characterization, and/or operational monitoring. A unity gain analog buffer may be provided to tap the on-die signal proximate to a node of interest, which may be implemented within the on-die measurement circuit.Type: ApplicationFiled: December 24, 2010Publication date: June 28, 2012Inventor: Vinu K. ELIAS
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Publication number: 20120139575Abstract: An apparatus, suitable for coupling a pads of integrated circuits on wafer to the pogo pins of a pogo tower in a test system without the need of a probe card, includes a body having a first surface and a second surface, the body having a substantially circular central portion, and a plurality of bendable arms extending outwardly from the central portion, each bendable arm having a connector tab disposed at the distal end thereof; a first plurality of contact terminals disposed on the second surface of the central portion of the body, the first plurality of contact terminals arranged in pattern to match the layout of pads on a wafer to be contacted; at least one contact terminal disposed on the first surface of the plurality of connector tabs; and a plurality of electrically conductive pathways disposed in the body such that each of the first plurality of contact terminals is electrically connected to a corresponding one of the contact terminals on the first surface of the connector tabs.Type: ApplicationFiled: March 10, 2011Publication date: June 7, 2012Applicant: Advanced Inquiry Systems, Inc.Inventor: Morgan T. Johnson
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Patent number: 8190391Abstract: A method includes receiving a first set of parameters associated with a plurality of die. A first die performance metric associated with a selected die is determined based on the first set of parameters. At least one neighborhood die performance metric associated with a set comprised of a plurality of die that neighbor the selected die is determined based on the first set of parameters. A second die performance metric is determined for the selected die based on the first die performance metric and the neighborhood die performance metric.Type: GrantFiled: March 29, 2007Date of Patent: May 29, 2012Assignee: GLOBALFOUNDRIES Inc.Inventors: Daniel Kadosh, Gregory A. Cherry, Carl I. Bowen, Luis De La Fuente, Rajesh Vijayaraghavan
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Publication number: 20120126846Abstract: The present invention discloses a method of testing a partially assembled multi-die device (1) by providing a carrier (300) comprising a device-level test data input (12) and a device-level test data output (18); placing a first die on the carrier, the first die having a test access port (100c) comprising a primary test data input (142), a secondary test data input (144) and a test data output (152), the test access port being controlled by a test access port controller (110); communicatively coupling the secondary test data input (144) of the first die to the device-level test data input (12), and the test data output (152) of the first die to the device-level test data output (18); providing the first die with configuration information to bring the first die in a state in which the first die accepts test instructions from its secondary test data input (144); testing the first die, said testing including providing the secondary test data input (144) of the first die with test instructions through the device-Type: ApplicationFiled: September 26, 2009Publication date: May 24, 2012Applicant: NXP B.V.Inventors: Franciscus Gerardus Maria De Jong, Alexander Sebastian Biewenga
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Publication number: 20120113556Abstract: An apparatus is described for burn-in and/or functional testing of microelectronic circuits of unsingulated wafers. A large number of power, ground, and signal connections can be made to a large number of contacts on a wafer. The apparatus has a cartridge that allows for fanning-in of electric paths. A distribution board has a plurality of interfaces that are strategically positioned to provide a dense configuration. The interfaces are connected through flexible attachments to an array of first connector modules. Each one of the first connector modules can be independently connected to a respective one of a plurality of second connector modules, thereby reducing stresses on a frame of the apparatus. Further features include for example a piston that allows for tight control of forces exerted by terminals onto contacts of a wafer.Type: ApplicationFiled: January 18, 2012Publication date: May 10, 2012Applicant: Aehr Test SystemsInventors: Donald P. Richmond, II, Kenneth W. Deboe, Frank O. Uher, Jovan Jovanovic, Scott E. Lindsey, Thomas T. Maenner, Patrick M. Shepherd, Jeffrey L. Tyson, Mark C. Carbone, Paul W. Burke, Doan D. Cao, James F. Tomic, Long V. Vu
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Publication number: 20120112784Abstract: An IC package includes an integrated circuit for transmitting and receiving a pair of differential signals composed of a signal having positive polarity and a signal having negative polarity, a first signal terminal for transmitting the signal having positive polarity, a second signal terminal for transmitting the signal having negative polarity, and a third terminal arranged between the first signal terminal and the second signal terminal. The first and second terminals are electrically connected to the integrated circuit, and the third terminal is not electrically connected to the integrated circuit.Type: ApplicationFiled: April 13, 2011Publication date: May 10, 2012Inventors: Kohei Masuda, Osamu Shibata, Hiroshi Suenaga, Yoshiyuki Saito
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Publication number: 20120092038Abstract: The present invention provides semiconductor integrated circuit, inspection device and inspection method for inspecting whether inspection target is functioning normally regardless to start-up period of a power supply voltage. The inspection device includes a reset control circuit and a tester. When a reset signal is inputted from a power-on reset circuit to a first terminal, the reset control circuit starts output of a reset execution signal having the same level as the reset signal. When a trigger signal is inputted from a control device to the second input terminal, the reset control circuit finishes the output of the reset execution signal and starts output of a release execution signal that has the same level as a reset release signal from the output terminal. The tester determines whether the power-on reset circuit is functioning normally by determining whether signals outputted from the reset control circuit are at predetermined levels.Type: ApplicationFiled: October 12, 2011Publication date: April 19, 2012Applicant: LAPIS Semiconductor Co., Ltd.Inventor: Shuichiro FUJIMOTO
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Patent number: 8148996Abstract: The invention discloses a circuit testing apparatus for testing a device under testing. The circuit testing apparatus includes a logic tester and a signal-measuring module. The logic tester is coupled to the device under testing for providing a testing signal and a trigger signal, and then determining a testing result for the device under testing according to a digital measuring result. The signal-measuring module coupled to the device under testing and the logic tester, is utilized for measuring a DC signal generated by the device under testing according to the testing signal after receiving the trigger signal, and generating the digital measuring result.Type: GrantFiled: May 9, 2007Date of Patent: April 3, 2012Assignee: Princeton Technology CorporationInventors: Cheng-Yung Teng, Hung-Wei Chen, Yung-Yu Wu
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Publication number: 20120068730Abstract: A device is configured to evaluate electromagnetic characteristics of an integrated circuit. The device includes a fluid chamber, a first impeller, a second impeller, and a radio frequency measurement antenna. The fluid chamber is configured to receive the integrated circuit and to cool the integrated circuit. The first impeller is disposed within the fluid chamber and configured to distribute a first electromagnetic field produced by the integrated circuit within the fluid chamber along a first axis. The second impeller is within the fluid chamber and configured to distribute the first electromagnetic field produced by the integrated circuit within the fluid chamber along a second axis. The radio frequency measurement antenna is disposed proximate the fluid chamber and configured to measure an electric field and a magnetic field of the first electromagnetic field.Type: ApplicationFiled: November 21, 2011Publication date: March 22, 2012Applicant: DELL PRODUCTS, LPInventors: Jeffrey C. Hailey, Todd W. Steigerwald
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Publication number: 20120056639Abstract: A semiconductor integrated circuit device comprising: a circuit block formed on a semiconductor substrate; an electrically conductive pattern formed in an upper layer of a portion to be protected of the circuit block; an oscillation circuit connected to the electrically conductive pattern, and configured to oscillate at an oscillation frequency determined by a circuit constant of the electrically conductive pattern; and a detection circuit configured to determine whether a preset range includes the oscillation frequency of the oscillation circuit is provided.Type: ApplicationFiled: August 2, 2011Publication date: March 8, 2012Applicant: CANON KABUSHIKI KAISHAInventor: Masanobu Oomura
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Publication number: 20120056640Abstract: A compliant printed circuit semiconductor tester interface that provides a temporary interconnect between terminals on integrated circuit (IC) devices being tested. The compliant printed circuit semiconductor tester interface includes at least one dielectric layer printed with recesses corresponding to a target circuit geometry. A conductive material is deposited in at least a portion of the recesses comprising a circuit geometry and a plurality of first contact pads accessible along a first surface of the compliant printed circuit. At least one dielectric covering layer is preferably applied over the circuit geometry. A plurality of openings in the dielectric covering layer are provided to permit electrical coupling of terminals on the IC device and the first contact pads. Testing electronics that to test electrical functions of the IC device are electrically coupled to the circuit geometry.Type: ApplicationFiled: June 28, 2010Publication date: March 8, 2012Applicant: HSIO TECHNOLOGIES, LLCInventor: James Rathburn
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Publication number: 20120049884Abstract: Crack sensors for semiconductor devices, semiconductor devices, methods of manufacturing semiconductor devices, and methods of testing semiconductor devices are disclosed. In one embodiment, a crack sensor includes a conductive structure disposed proximate a perimeter of an integrated circuit. The conductive structure is formed in at least one conductive material layer of the integrated circuit. The conductive structure includes a first end and a second end. A first terminal is coupled to the first end of the conductive structure, and a second terminal is coupled to the second end of the conductive structure.Type: ApplicationFiled: November 8, 2011Publication date: March 1, 2012Applicant: Infineon Technologies AGInventor: Erdem Kaltalioglu
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Patent number: RE43607Abstract: Wire bond pad and solder ball or controlled collapse chip connections C4 are combined on a planar surface of a an integrated circuit device to provide a die. Known good die (KGD) testing is optionally performed using wire bond connections or stress tolerant solder ball connections. The KGD testing is conducted after the integrated circuit dies are diced from a wafer. Solder ball or C4 array connections which withstand thermal stress are used to KGD test the die prior to final use of the wire bond pad connections to an end use device. Alternatively, wire bond pads are used to test the die while maintaining the solder ball or C4 array in a pristine condition for bonding to a final end product device. Both testing with the solder ball C4 array contacts and with the wire bond connections provides metallurgical connections for the KGD test. The solder ball or C4 array is connected to the wire bond pads and either connection can be used to burn-in test the die.Type: GrantFiled: May 31, 2007Date of Patent: August 28, 2012Assignee: Jones Farm Technology, LLCInventors: Steve M. Danziger, Tushar Shah
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Patent number: RE44407Abstract: Method and apparatus for electrical testing of a device under test (DUT) that employs a connection board with signal contacts for applying test signals and a space transformer that has low pitch contacts arranged on one or more circumferential shelves that define an enclosure in the space transformer. The apparatus has a substrate with fine pitch contacts positioned such that these are within the enclosure. A set of wire bonds is used for pitch reduction by interconnecting the fine pitch contacts with the low pitch contacts arranged on the shelves. The probes are connected to the fine pitch contacts and are used to apply the test signals to a DUT by contacting its pads. In some embodiments, the fine pitch contacts may be embodied by plugs or by blind metal vias.Type: GrantFiled: December 23, 2009Date of Patent: August 6, 2013Assignee: FormFactor, Inc.Inventor: January Kister