Abstract: An integrated circuit includes an electronic circuit in a housing and a first contacting device for soldering the circuit to a corresponding second contacting device of a circuit board. The first and second contacting devices are each divided into a first section and a second section, the sections of one of the contacting devices being fixedly electrically connected to each other, and the sections of the other contacting device being selectively connectable to a device for resistance determination.

Abstract: A method for verifying stitching accuracy of a stitched chip on a wafer is disclosed. Initially, a set of test structures are inserted within a reticle layout. An exposure program is executed to control a photolithography equipment having a stepper to perform multiple exposures of the reticle on a wafer to generate a stitched chip on the wafer. Electrical measurements are then performed on the test structures at actual stitch boundaries of the stitched chip to evaluate stitching accuracy of the stitched chip.

Abstract: An integrated circuit chip is provided. The integrated circuit chip includes a pad, a first resistor, a second resistor, a first switch, a second switch and a controller. The first resistor and the first switch are serially connected between the pad and a first reference voltage terminal. The second resistor and the second switch are serially connected between the pad and a second reference voltage terminal. The controller selectively turns on and off the first and second switches according to an error determining mechanism. The error determining mechanism determines whether an error condition associated with the pad is present.

Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.

Abstract: A method includes contacting a first group of through-silicon vias (TSVs) contacts with a multi-contact probe and applying a first voltage value to each of the first group of TSV contacts via the multi-contact probe, where the first group of TSV contacts corresponds to a first group of TSVs. The method also includes determining, based on a second voltage value detected at a particular TSV of the first group of TSVs, whether the particular TSV corresponds to a TSV test result.

Abstract: In accordance with one aspect of the present description, integrated circuits may tested by optically transmitting test data over a light beam in addition to or instead of transmitting the test data using mechanical probes. Optically transmitted test data is detected by a photon detector on board the die to be tested. Individual circuit portions of the die may be tested using test data associated with each individual circuit portion. Other aspects are described.

Abstract: The present invention provides semiconductor integrated circuit, inspection device and inspection method for inspecting whether inspection target is functioning normally regardless to start-up period of a power supply voltage. The inspection device includes a reset control circuit and a tester. When a reset signal is inputted from a power-on reset circuit to a first terminal, the reset control circuit starts output of a reset execution signal having the same level as the reset signal. When a trigger signal is inputted from a control device to the second input terminal, the reset control circuit finishes the output of the reset execution signal and starts output of a release execution signal that has the same level as a reset release signal from the output terminal. The tester determines whether the power-on reset circuit is functioning normally by determining whether signals outputted from the reset control circuit are at predetermined levels.

Abstract: An integrated circuit integrated on a semiconductor material die and adapted to be at least partly tested wirelessly, wherein circuitry for setting a selected radio communication frequencies to be used for the wireless test of the integrated circuit are integrated on the semiconductor material die.

Abstract: A sensor system includes a sensor device and a cover device. The sensor device includes an external surface on which at least one electrical test contact is arranged. The cover device includes at least partially an electrically insulating material and is mechanically connected to the sensor device. The cover device is configured to cover the at least one electrical test contact of the sensor device so as to prevent contact from being made to the at least one electrical test contact from outside the sensor system.

Abstract: A semiconductor chip may include a die having one or more circuits. The semiconductor chip may include a plurality of die bumps, each having a first geometry, a first vertical profile, and a first volume. The die bumps may be coupled to the die and in electrical communication with the one or more circuits. The semiconductor device may include a plurality of test bumps each having a second geometry, a second vertical profile, and the first volume. The test bumps may be coupled to the die and in electrical communication with the one or more circuits. The first geometry and the second geometry may be adapted for the plurality of test bumps to make connection with a wafer probe to the test bumps without making a connection to any of the die bumps during a die test.

Abstract: A transition delay test is conducted such that an internal circuit that is a test object circuit in a semiconductor device is divided into a plurality of circuit blocks and a determination test is conducted while changing concurrently operating circuit blocks, a power supply noise generated during conduction of the determination test is detected, a suitable circuit scale on which the transition delay test can be normally conducted without being affected by the influence of the power supply noise is determined based on the result of the determination test and the detected power supply noise, and clocks to be supplied to the circuit blocks are controlled based on the determination result to limit the number of the concurrently operating circuit blocks.

Abstract: Disclosed are embodiments of an integrated circuit chip designed for reliability at low ambient temperatures. The chip substrate can be divided into zones, including at least one temperature-sensitive zone (TSZ) that contains one or more temperature-sensitive circuits. Temperature sensor(s) can be positioned in the semiconductor substrate adjacent to the TSZ. Thermal radiator(s) can be embedded in a metal wiring layer and aligned above the TSZ. The temperature sensor(s) can be operatively connected to the thermal radiator(s) and can trigger operation of the thermal radiator(s) when the temperature in the TSZ is below a predetermined threshold temperature. Additionally, an on-chip power control system can be operatively connected to the thermal radiator(s) so that operation of the thermal radiator(s) is only triggered when a circuit within the TSZ is about to be powered up. Also disclosed are associated embodiments of a system and method for designing such an integrated circuit chip.

Abstract: A semiconductor device includes a monitor including a first element coupled between a first power supply line and a second power supply line, and a load for increasing a load value between the first element and the first power supply line or the second power supply line, and a determination unit which determines an operating state of the first element based on an output of the monitor.

Abstract: An on-chip technique for noncontact electrical testing of a test structure on a chip is provided. On-chip photodiodes receives pump light from a pump light source, where the on-chip photodiodes are electrically connected to the test structure and are configured to generate power for the test structure. An on-chip coupling unit receives probe light from a probe light source, where the on-chip coupling unit is optically connected to on-chip waveguides through which the probe light is transferred. On-chip switches open in response to receiving voltage output from the test structure, and the on-chip switches remain closed when the voltage output is not received from the test structure. The on-chip switches pass the probe light when opened by the voltage output from the test structure. The on-chip switches block the probe light by remaining closed, when the voltage output is not received from the test structure.

Abstract: A device for monitoring the latency of electronic circuits based on microtechnology and/or nanotechnology, said circuits to be tested being supplied with the aid of a voltage Vdd, having a low level and a high level, for the detection of delay faults of said circuits, comprises: at least one device of type I placed between the high level of the power supply voltage and the elements of the circuit to be tested, and/or at least one device of type II placed between the low level of the power supply voltage of the elements of the elements of said circuit to be tested, the device of type I and the device of type II comprising at least one low-latency electrical path said low-latency path being connected in parallel with a high-latency electrical path, a test signal monitoring the opening of the low-latency paths while the high-latency electrical paths are open.

Abstract: By constructing a universal test circuit on a tester chip, and stacking the tester chip in an IC package together with operational circuit chips to be tested, the problems inherent with external IC testing are reduced. The tester chip can be standardized across a number of different chip combinations and, if desired, pre-programmed during manufacturing for a particular package. The tester chip interfaces to other chips in the stack advantageously are standardized.

Abstract: A semiconductor apparatus (IPD) includes a set value storage unit that stores a set value determined based on an initial characteristic value of the IPD, and a detector that detects characteristic degradation of the IPD based on a characteristic value of the IPD at given timing and the set value stored in the set value storage unit. Further, a method of detecting characteristic degradation of a semiconductor apparatus (IPD) includes storing a set value determined based on an initial characteristic value of the IPD, and detecting characteristic degradation of the IPD based on a characteristic value of the IPD at given timing and the stored set value.

Abstract: A test system and method for selecting a derating factor to be applied to a ratio of transistors having disparate electrical characteristics in a wafer fabrication process. In one embodiment, the test system includes: (1) structural at-speed automated test equipment (ATE) operable to iterate structural at-speed tests at multiple clock frequencies over integrated circuit (IC) samples fabricated under different process conditions and (2) derating factor selection circuitry coupled to the structural at-speed ATE and configured to employ results of the structural at-speed tests to identify performance deterioration in the samples, the performance deterioration indicating the derating factor to be employed in a subsequent wafer fabrication process.

Abstract: A circuit test interface and a test method are disclosed. The circuit test interface may include a test voltage input pad, a test voltage output pad, and a plurality of input buffers. Each of the plurality of input buffers may have a first input terminal, a second input terminal, and an output terminal. The first input terminal of each respective input buffer may be coupled to one of a plurality of through-silicon vias (TSVs). The circuit test interface may further include a plurality of switch units. Each of the plurality of switch units may have a first terminal and a second terminal. The circuit test interface may further include a scan chain, coupled to both the output terminal of each of the plurality of input buffers and to the test voltage output pad.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

Abstract: A system and method for detecting transition delay faults decouples the test enable pins of the clock gating cells from other elements in the circuitry. The test enable pins are controlled during test mode by a unique signal, allowing the tester to independently control the clock gating logic of the circuitry. By being able to ungate the clock, the tester can ensure that the two clock pulses needed to check for transition delay faults will always be present.

Abstract: An interposer for a 3D-IC is provided with a plurality of functional metal wiring segments where the plurality of functional metal wiring segments are connected in series by a plurality of dummy metal wiring segments thus allowing the plurality of functional metal wiring segments to be electrically tested for continuity Each of the plurality of dummy metal wiring segments is provided with a laser fuse portion for disconnecting the dummy metal wiring segments upon completion of the electrical test.

Abstract: A device includes a test unit in a die. The test unit includes a physical test region including an active region, and a plurality of conductive lines over the active region and parallel to each other. The plurality of conductive lines has substantially a uniform spacing, wherein no contact plugs are directly over and connected to the plurality of conductive lines. The test unit further includes an electrical test region including a transistor having a gate formed of a same material, and at a same level, as the plurality of conductive lines; and contact plugs connected to a source, a drain, and the gate of the transistor. The test unit further includes an alignment mark adjacent the physical test region and the electrical test region.

Abstract: An embodiment of a probe card adapted for testing at least one integrated circuit integrated on a corresponding at least one die of a semiconductor material wafer, the probe card including a board adapted for the coupling to a tester apparatus, and a plurality of probes coupled to the said board, wherein the probe card comprises a plurality of replaceable elementary units, each one comprising at least one of said probes for contacting externally-accessible terminals of an integrated circuit under test, the plurality of replaceable elementary units being arranged so as to correspond to an arrangement of at least one die on the semiconductor material wafer containing integrated circuits to be tested.

Abstract: In accordance with one aspect of the present description, an integrated circuit die has a plurality of through-body-vias and a testing circuit on board the die which allows charges on a first and second through-body-via to redistribute between them to provide an indication whether one or both of the first and second through-body-vias has a defect. Other aspects are described.

Abstract: An integrated circuit includes switching circuits for selectively connecting the bond pads to functional core logic and isolating the bond pads from second conductors, and the switch circuits for selectively connecting the bond pads to the second conductors to provide bi-directional connections between the bond pads on opposite sides of the substrate and isolating the bond pads from the functional core logic.

Abstract: A test system includes a test printed circuit board (PCB), a flip chip package mounted on the PCB, one or more test probes coupled to the flip chip package and a first integrated circuit (IC) coupled to the test probes to enable testing of the first IC using electrical circuitry of the flip chip package.

Abstract: Consistent with an example embodiment, there is integrated circuit (IC) die responsive to a reset signal. The IC die includes a detector coupled to a power supply of the die for generating the reset signal in response to the detection of a voltage increase of the power supply. Coupled to the detector, a reset signal output, coupled to the detector, provides the reset signal to an external device.

Abstract: Some aspects of the present disclosure relate to an apparatus that includes an integrated chip having a bandgap reference circuit and one or more heating elements. The bandgap reference circuit is located within a subset of the integrated chip and outputs a reference voltage having a temperature dependence. The one or more of the heating elements vary the temperature of the subset of the integrated chip.

Abstract: An integrated circuit integrated on a semiconductor material die and adapted to be at least partly tested wirelessly, wherein circuitry for setting a selected radio communication frequencies to be used for the wireless test of the integrated circuit are integrated on the semiconductor material die.

Abstract: A performance characteristic monitoring circuitry includes a first delay circuitry providing a first delay path, where transmission of a data value over that first delay path incurs a first delay that varies in dependence on the performance characteristic. Reference delay circuitry is also included to provide a reference delay path, where transmission of the data value over the reference delay path incurs a reference delay. The reference delay circuitry includes components configured to provide a capacitive loading on the reference delay path in order to produce a self-compensating effect on the reference delay that causes the reference delay to be less sensitive than the first delay to variation in the performance characteristic. Comparison circuitry is then used to generate the output signal of the monitoring circuitry in dependence on a comparison of the first delay and the reference delay.

Abstract: A chip diagnostics management system includes secure design information that define production features of integrated circuit devices and are accessible according to selected levels of access privilege. A database of device defect information includes information of defects of devices produced according to the production features of the design information and associated wafers, production lots, and dies in or with which the devices were produced. A diagnostic manager correlates device defect information from plural wafers with the design information to identify a device location with a probability of being associated with the device defect information. A diagnostic manager viewer indicates the device location together with an amount of design information correlated the level of access privilege assigned to a selected user.

Abstract: Embodiments of the invention provide a method to detect pick and place indexing errors on each manufacturing batch (lot) of semiconductor wafer processed during a die attach process using a preselected skeleton of check die. The known locations of the check skeleton die are verified during picking of die from the wafer. If the check skeleton cannot be correctly verified at the known locations, then a pick error is indicated. The embodiments may be implemented on existing die attach equipment.

Abstract: A short dummy test structure is disclosed, including a grounded shield layer above a substrate, at least two signal test pads, and a signal transmission line above the grounded shield layer and between the two signal test pads, wherein the signal transmission line is electrically coupled to the grounded shield layer. In one embodiment, the signal transmission line has a smaller total length than a total length of a corresponding signal transmission line and a device-under-test (DUT) of a test structure including the DUT. A de-embedding apparatus and method of de-embedding utilizing such a short dummy test structure are also disclosed.

Abstract: A continuity test circuit for a boundary pad includes a pull-up transistor electrically connected between the boundary pad and a first power supply, and a pull-down transistor electrically connected between the boundary pad and a first reference ground potential. A normal output conductor is electrically connected to have a same electrical state as the boundary pad during normal operation. A continuity test output conductor is electrically connected to have a same electrical state as the boundary pad during continuity test operation. Continuity testing control circuitry is defined to control the pull-up transistor, the pull-down transistor, and the normal output conductor during continuity test operation such that an electrical state present on the continuity test output conductor indicates a status of electrical continuity between the boundary pad and either a second power supply or a second reference ground potential to which the boundary pad should be electrically connected.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: An overvoltage protection circuit connected to protect electrical components from overvoltage conditions includes a blocking diode connected in series with a transient voltage suppression device (TVS) via a first node and includes a reference voltage for biasing the first node at a voltage sufficient to reverse bias the blocking diode during normal operations. A built-in test circuit associated with the overvoltage protection circuit includes a resistor connected to the first node and a switch connected in series with the resistor that is selectively turned On and Off. The built-in test circuit monitors voltage on a control line associated with the electrical components and at the first node while the switch is Off and while the switch is On, and detects fault conditions based on the monitored voltages.

Abstract: An integrated circuit includes a monitoring circuit and a monitored circuit connected with the monitoring circuit. The monitoring circuit is operable to determine during fabrication if a resistance of a connection between an in-fab redistribution layer connector and a post-fab redistribution layer connector exceeds a threshold.

Abstract: A method and device for testing through-substrate vias (TSVs) in a 3D chip stack are disclosed. In one aspect, the 3D chip stack includes at least a first die having a first electrical circuit and a second die having a second electrical circuit. The first die further includes at least one first TSV for providing electrical connection between the first electrical circuit and the second electrical circuit. The first die further includes test circuitry and at least one second TSV electrically connected between the first TSV and the test circuitry. The electrical connection between the first TSV and the second TSV is made outside the second die. In one aspect, this allows testing the first TSV in the first die even if the second die is not provided with dedicated test circuitry.

Abstract: A method of testing a semiconductor device includes a conductive foreign matter test step of measuring the resistance value between the first and second conductive patterns to determine whether conductive foreign matter is present between the first and second conductive patterns, a first open circuit test step of measuring the resistance value between two points on the first conductive pattern to determine whether there is an open circuit in the first conductive pattern, and a second open circuit test step of measuring the resistance value between two points on the second conductive pattern to determine whether there is an open circuit in the second conductive pattern. The measurement of the resistance value in each of the test steps is accomplished by pressing probes vertically against the first conductive pattern or the second conductive pattern or both.

Abstract: A semiconductor test device including a plurality of conductive layers, each of the layers comprising integrated circuit devices, a plurality of insulating layers between the conductive layers, a plurality of heat generating structures positioned between the insulating layers and the conductive layers, each of the heat generating structures being sized and positioned to only heat a predetermined limited area of the plurality of layers, a plurality of thermal monitors positioned within each of the plurality of layers, a control unit operatively connected to the heat generating structures and the thermal monitors, the control unit individually cycling the heat generating structures on and off for multiple heat cycles, such that different areas of the layers are treated to different heat cycles.

Abstract: In one embodiment, the present invention includes a semiconductor die such as a system on a chip (SoC) that includes a logic analyzer with a built-in trace buffer to store information communicated between on-die agents at speed and to provide the information to an off-die agent at a slower speed. Other embodiments are described and claimed.

Abstract: A method is provided for design and programming of a probe card with an on-board programmable controller in a wafer test system. Consideration of introduction of the programmable controller is included in a CAD wafer layout and probe card design process. The CAD design is further loaded into the programmable controller, such as an FPGA to program it: (1) to control direction of signals to particular ICs, even during the test process (2) to generate test vector signals to provide to the ICs, and (3) to receive test signals and process test results from the received signals. In some embodiments, burn-in only testing is provided to limit test system circuitry needed so that with a programmable controller on the probe card, text equipment external to the probe card can be eliminated or significantly reduced from conventional test equipment.

Abstract: A method of integrated circuit (IC) disposition includes the steps of determining one or more disposition criteria based at least in part on statistical timing of a given IC design; and determining whether a given IC according to the given IC design satisfies the one or more disposition criteria based at least in part on one or more measurements of at least one test structure.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: A device and method are disclosed wherein a receiver signal line within an integrated circuit may be selected for probing. In one embodiment, a plurality of signal pads and a test pad are provided on an external surface of an integrated circuit chip. A plurality of signal lines extends through the integrated circuit chip to the signal pads. A multiplexer on the integrated circuit chip is configured for individually selecting any of the signal lines. An amplifier on the integrated circuit chip amplifies a selected signal and communicates the amplified signal to an externally-accessible test pad to be probed.

Abstract: Current tests for I/O interface connectors are described. In one example a test may include applying a forced energy to a first pin of an interface of a data communications bus of an integrated circuit on a die, sensing the energy caused by the forced energy at a second pin of the interface, and comparing the forced energy and the sensed energy to determine an amount of current leaked by at least a portion of the interface.

Abstract: A multi-interface integrated circuit in which, during the chip's lifetime in use, only one interface is active at a time. However, special test logic powers up all of the on-chip interface modules at once, so that a complete test cycle can be performed. All of the interfaces are exercised in one test program. Since some pads are inactive in some interface modes, mask bits are used to select which pads are monitored during which test cycles.

Abstract: A method of integrated circuit (IC) disposition includes the steps of determining one or more disposition criteria based at least in part on statistical timing of a given IC design; and determining whether a given IC according to the given IC design satisfies the one or more disposition criteria based at least in part on one or more measurements of at least one test structure.