Abstract: The present invention is a method for evaluating a silicon wafer by measuring, after fabricating a MOS capacitor by forming an insulator film and one or more electrodes sequentially on a silicon wafer, a dielectric breakdown characteristic of the insulator film by applying an electric field from the electrodes thus formed to the insulator film, the method in which the silicon wafer is evaluated at least by setting an area occupied by all the electrodes thus formed to 5% or more of an area of a front surface of the silicon wafer when the one or more electrodes are formed. This provides an evaluation method that can detect a defect by a simple method such as the TDDB method with the same high degree of precision as that of the DSOD method.

Abstract: An integrated circuit includes an electronic circuit in a housing and a first contacting device for soldering the circuit to a corresponding second contacting device of a circuit board. The first and second contacting devices are each divided into a first section and a second section, the sections of one of the contacting devices being fixedly electrically connected to each other, and the sections of the other contacting device being selectively connectable to a device for resistance determination.

Abstract: Special test circuitry in an IC for wafer level testing selectively connects the specialized test circuitry to the functional circuitry during wafer test. Following wafer test the special test circuitry is electrically isolated from the functional circuitry and power supplies such that it does not load functional circuit signals nor consume power.

Abstract: An electronic device includes an electronic component and a protection circuit configured to protect the component from overvoltages. A control circuit is configured to inhibit a part of the protection circuit in the presence of a test voltage across terminals of the component.

Abstract: A method, system, and computer usable program product for in an integrated circuit are provided in the illustrative embodiments. A signal to be measured is identified in the IC. The signal is provided as a first control voltage input to a first VCO in the IC. A first output frequency is generated from the first VCO, the first output frequency having a first frequency value corresponding to the signal. The signal is provided as a second control voltage input to a second VCO in the IC. A second output frequency is generated from the second VCO, the second output frequency having a second frequency value corresponding to the signal. The first and the second output frequency values are exported from the IC. A mean value and a standard deviation of the signal are computed using the output first and second frequency values.

Abstract: A method of testing a multi-die integrated circuit (IC) can include testing an inter-die connection of the multi-die IC. The inter-die connection can include a micro-bump coupling a first die to a second die. The method can include detecting whether a fault occurs during testing of the inter-die connection. Responsive to detecting the fault, the multi-die integrated circuit can be designated as including a faulty inter-die connection. Also described is an integrated circuit that includes a first die, a second die on which the first die may be disposed, a plurality of inter-die connections coupling the first die to the second die, and a plurality of probe pads, where each probe pad is coupled to at least one of the inter-die connections.

Abstract: A method of testing electronic assemblies including singulated TSV die attached to a ML package substrate, on a substrate carrier. The substrate carrier includes through-holes for allowing probe contact to the BGA substrate pads on a bottomside of the package substrate that are coupled to the frontside of the TSVs. Contactable TSV tips on the bottomside of the TSV die are contacted with a topside coupler that includes a pattern of coupling terminals that matches a layout of at least a portion of the TSV tips or pads coupled to the TSV tips. The topside coupler electrically connects pairs of coupling terminals to provide a plurality of TSV loop back paths. The BGA substrate pads are contacted with a plurality of probes tips that extend through the through-holes to couple to the frontside of the TSVs. Electrical testing is performed across the electronic assembly to obtain at least one test parameter.

Abstract: A voltage measuring apparatus for a semiconductor integrated circuit includes a first delay unit configured to delay a reference clock in a first region, a second delay unit configured to delay the reference dock in a second region and an analysis unit configured to analyze a difference in voltage level between the regions based on the phases of associated with the delayed clock signals generated by the first and second delay units.

Abstract: An integrated circuit device includes a stacked die and a base die having probe pads that directly couple to test logic of the base die to implement a scan chain for testing of the integrated circuit device. The base die further includes contacts disposed on a back side of the base die and through-die vias coupled to the contacts and coupled to programmable logic of the base die. The base die also includes a first probe pad configured to couple test input, a second probe pad configured to couple test output, and a third probe pad configured to couple control signals. Test logic of the base die is configured to couple to additional test logic of the stacked die to implement the scan chain. The probe pads are coupled directly to the test logic such that configuration of the programmable logic is not required to implement the scan chain.

Abstract: A method of enabling a circuit board analysis is disclosed. The method comprising removing a portion of the circuit board on a first side of the circuit board opposite a second side of the circuit board having an integrated circuit package; removing the circuit board from the integrated circuit package; performing a dye mapping to analyze bonds between the integrated circuit package and the circuit board; and performing an analysis of the integrated circuit package.

Abstract: System and methods transfer data over a microcontroller system test interface. The system can read data from and write data to microcontroller system memory using the described method. The method provides for the efficient transfer of data, minimizing redundancies and overhead present in conventional microcontroller test system protocols.

Abstract: Disclosed is a method and a system for automatically managing probe mark shifts. A determination is made from test data as to whether a die on a wafer is defective. A probe mark check on the wafer is made to determine whether a probe mark is shifted. Necessary recovery action is performed in response to the probe mark being shifted. In the probe mark check, a plurality of probe mark positions are selected from the test data. A determination is then made as to whether at least one of the plurality of probe mark positions violates an engineering rule.

Abstract: An integrated circuit die includes a plurality of interconnects including a first test data input, a second test data input and a test dat a output, and a test arrangement for testing the integrated circuit die. The test arrangement includes a further multiplexer coupled to the test data output, a multiplexer coupled to the first test data input and the second test data input, a plurality of shift registers including an instruction register, each of the shift registers being coupled between the multiplexer and the further multiplexer and a controller for controlling the multiplexer and the further multiplexer in response to the instruction register. Such a test arrangement facilitates JTAG compliant testing of a system in package by providing a direct connection between the SiP test data input pin and the second test data input of the IC die, and the SiP test data output pin and the test data output of the IC die, thus facilitating the bypassing of other test arrangements in the SiP.

Abstract: A semiconductor wafer includes a plurality of integrated circuit (IC) die areas for accommodating IC die that include at least a first subcircuit having at least one matched component portion that includes at least two matched devices. The first subcircuit is arranged in a layout on the IC die. A plurality of scribe line areas having a scribe line width dimension are interposed between the plurality of IC die areas. At least one subcircuit-based test module (TM) is positioned within the scribe line areas, wherein the subcircuit-based TMs implement a schematic for the first subcircuit with a TM layout that copies the layout on the IC die for at least the two matched devices in the matched component portion and alters the layout on the IC die for a portion of the first subcircuit other than the matched devices in matched component portion to fit the TM layout of the first subcircuit within the scribe line width dimension.

Abstract: A wafer is disclosed that includes a plurality of pipeline interconnected integrated circuit dies that form a plurality of pipelines. A plurality of dies in each pipeline is connected to receive scanned output test data from a neighboring die in a pipeline. A wafer level test access mechanism (TAM) transceiver circuitry, located outside the plurality of pipeline interconnected IC dies, is connected in common to each of the pipelines to provide input test data in a parallel fashion to the plurality of pipelines. The wafer level test access mechanism transceiver circuitry also provides output test results from each of the pipelines for evaluation by a computerized test system. In one embodiment, the wafer level test access mechanism transceiver circuitry is wireless so that it wirelessly receives test data to be passed through the multiple pipelines on a wafer and also includes wireless transmit circuitry to transmit test results from each of the pipelines.

Abstract: A semiconductor integrated circuit wafer includes: a plurality of semiconductor integrated circuit regions each of which includes a semiconductor integrated circuit formed thereon; a scribe region which separates the semiconductor integrated circuit regions adjacent to each other; a build in self test (BIST) circuit which is provided in the scribe region and inspects the semiconductor integrated circuit; a connection wiring which is formed ranging from the scribe region to the semiconductor integrated circuit region and connects the semiconductor integrated circuit and the BIST circuit; a BIST switching signal input pad which is provided in the semiconductor integrated circuit region; and a BIST switching circuit which is provided in the semiconductor integrated circuit region and is driven by a driving signal input from the BIST switching signal input pad, the BIST switching circuit including: an input-output pad which connects with the semiconductor integrated circuit; a circuit wiring which connects the in

Abstract: A method and device for measuring a signal of a die to be placed within a package is disclosed. At least one die as a Device Under Test (DUT) is mounted on a substrate and a chip-type measurement instrument is mounted on the substrate, or embedded into the substrate, wherein the instrument analyzes and/or processes the signal of the DUT and may provide stimulus signal to the DUT. The substrate having the DUT and the measurement instrument is mounted on a circuit board that has plural electrodes to be connected to the signal paths of the DUT and the instrument. An electrode is coupled to a standard interface port to provide the signal of the chip-type instrument to an external instrument.

Abstract: The present invention relates to a detection circuitry for detecting bonding conditions on segmented bond pads of a semiconductor device, the bonding conditions representing good or bad contacts on the bond pads. The detection circuitry comprises a segmented bond pad (1, 11) having at least two parts (2, 3, 12, 13) being electrically separated from each other, and a supplying unit (S1, S2, R1, R2) being adapted for supplying predetermined signals to at least one of the at least two parts of the segmented bond pad. Furthermore, a detector (4, 14) is provided for receiving from at least one of the at least two parts of the segmented bond pad sensing signals derived from said predetermined signals, and for determining the bonding conditions based on said received sensing signals indicative of a good or bad bonding contact on the segmented bond pad.

Abstract: An integrated circuit for detecting a bonding defect in a multi-bonding wire. The integrated circuit includes a plurality of pads each connectable by a bonding wire to a lead terminal. Voltage supplied to the lead terminal is applied in common to the plurality of pads. A detection circuit is operably connected to the plurality of pads. The detection circuit detects breakage of the bonding wires based on potentials at the plurality of pads.

Abstract: A detection circuit and one or more wires or circuit traces are included in a die. The combination is used to detect mechanical failure of the substrate, e.g. silicon after singulation of the dice from the wafer. Failures may be detected at different regions or planes within the die, and the tests may be performed during operation of the packaged die and integrated circuit, even after installation and during operation of a larger electronic device in which it is incorporated. This is especially useful for chip scale packages, but may be utilized in any type of IC package.

Abstract: A reconfigurable number of at-speed pulses and reconfigurable dead cycles between pulses is utilized to enhance test coverage of an Integrated Circuit. A reconfigurable number of programmable at-speed phase-locked loop clock pulses without a dead cycle is emitted through an integrated circuit. Further, a plurality of programmable at-speed phase-locked loop clock pulses is emitted through the Integrated Circuit such that a reconfigurable number of dead cycles is between the plurality of programmable at-speed phase locked loop clock pulses. In addition, data associated with the reconfigurable number of programmable at-speed phase-locked loop clock pulses is capture. Finally, data associated with the reconfigurable number of dead cycles is captured.

Abstract: A method and device for testing through-substrate vias (TSVs) in a 3D chip stack are disclosed. In one aspect, the 3D chip stack includes at least a first die having a first electrical circuit and a second die having a second electrical circuit. The first die further includes at least one first TSV for providing electrical connection between the first electrical circuit and the second electrical circuit. The first die further includes test circuitry and at least one second TSV electrically connected between the first TSV and the test circuitry. The electrical connection between the first TSV and the second TSV is made outside the second die. In one aspect, this allows testing the first TSV in the first die even if the second die is not provided with dedicated test circuitry.

Abstract: An integrated circuit integrated on a semiconductor material die and adapted to be at least partly tested wirelessly, wherein circuitry for setting a selected radio communication frequencies to be used for the wireless test of the integrated circuit are integrated on the semiconductor material die.

Abstract: A circuit testing apparatus for testing a device under test is disclosed. The device under test comprises a first output end and second output end for generating a first output signal and a second output signal, respectively. The circuit testing apparatus determines a test result for the device under test according to the first output signal and the second output signal.

Abstract: A method for wafer level testing is provided which includes providing a wafer having an integrated circuit formed thereon, applying a signal to energize the integrated circuit, the signal including increasing steps or decreasing steps that range between a first level and a second level, and determining whether the integrated circuit complies with a test criteria after applying the signal.

Abstract: A time-to-breakdown for a dielectric layer in a semiconductor device is determined based upon a sudden change in capacitance. An alternating voltage, greater in magnitude than an operating voltage of the device, is applied to the semiconductor device, capacitance is measured across the dielectric layer during the application of the voltage until a sudden change in capacitance occurs, thereby indicating a breakdown in the dielectric layer, and the breakdown time is scaled to the operating voltage.

Abstract: An integrated circuit device is described that includes a stacked die and a base die having probe pads that directly couple to test logic of the base die so as to implement a scan chain for testing of the integrated circuit device. The base die further includes contacts disposed on a back side of the base die and through-die vias coupled to the contacts and coupled to programmable logic of the base die. In addition, the base die includes a first probe pad configured to couple test input, a second probe pad configured to couple test output and a third probe pad configured to couple control signals. Test logic of the base die is configured to couple to additional test logic of the stacked die so as to implement a scan chain for testing of the integrated circuit device.

Abstract: An integrated circuit probing structure (40) is provided for evaluating functional circuitry (42), such as a slow slew-rate square wave signal from a low power circuit, where the probing structure includes two or more probe pads (48, 49) for testing the functional circuitry which are formed to be electrically separate from one another, and a probe test circuit (46) connected to the functional circuitry (42) for conveying a signal from the functional circuitry to a probe needle (47) only when the probe needle (47) electrically connects the two or more probe pads (48, 49).

Abstract: A method, system, and computer usable program product for on-chip measurement of signals in an integrated circuit are provided in the illustrative embodiments. A signal to be measured is identified in the IC. The signal is provided as a first control voltage input to a first VCO in the IC. A first output frequency is generated from the first VCO, the first output frequency having a first frequency value corresponding to the signal. The signal is provided as a second control voltage input to a second VCO in the IC. A second output frequency is generated from the second VCO, the second output frequency having a second frequency value corresponding to the signal. The first and the second output frequency values are exported from the IC. A mean value and a standard deviation of the signal are computed using the output first and second frequency values.

Abstract: By examining scrub mark properties (such as position and size) directly, the performance of a wafer probing process may be evaluated. Scrub mark images are captured, image data measured, and detailed information about the process is extracted through analysis. The information may then be used to troubleshoot, improve, and monitor the probing process.