Abstract: An apparatus includes circuits, a field line configured to generate a magnetic field based on an input, a sensing module configured to determine a parameter of each circuit, and a magnetic field direction determination module configured to determine an angular orientation of the apparatus relative to an external magnetic field based on the parameter. Each circuit includes multiple magnetic tunnel junctions. Each magnetic tunnel junction includes a storage layer having a storage magnetization direction and a sense layer having a sense magnetization direction configured based on the magnetic field. Each magnetic tunnel junction is configured such that the sense magnetization direction and a resistance of the magnetic tunnel junction vary based on the external magnetic field. The parameter varies based on the resistances of the multiple magnetic tunnel junctions. The magnetic field direction determination module is implemented in at least one of a memory or a processing device.

Abstract: A method performed using a resistive device, where the resistive device includes a substrate with an active region separated from a gate electrode by a dielectric and electrical contacts along a longest dimension of the gate electrode, the method comprising, performing one or more processes to form the resistive device, measuring a resistance between the electrical contacts, and correlating the measured resistance with a variation in one or more of the processes.

Abstract: A pressure application technique is provided that enables two objects to be pressurized (e.g., objects to be bonded) to be positioned with greater accuracy before having pressure applied thereto. The objects to be pressurized are moved relative to each other in a Z direction such that the objects are brought into contact with each other (step S13). Then, a horizontal positional shift ?D between the objects to be pressurized is measured in the contact state of the objects to be pressurized (step S14). Thereafter, positioning of the objects to be pressurized is again performed by moving the objects to be pressurized relative to each other in the horizontal direction, as a result of which the positional shift ?D is corrected (step S17).

Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

Abstract: An apparatus of three-dimensional integrated-circuit (3D-IC) chip is provided. The apparatus uses a test through-silicon-via (TSV). The test TSV is used as a redundant TSV operated under a normal mode. Vice versa, the test TSV is remained to be used as a traditional test TSV under a scan mode. The present invention significantly reduces the number of redundant TSVs and the production cost of the chip.

Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

Abstract: A semiconductor device includes a plurality of stacked chips, a reference through silicon via (TSV) set passing through the plurality of stacked chips, a plurality of TSVs passing through the plurality of stacked chips, a reference delay information generation unit suitable for generating a reference delay information indicating an amount of delay of the reference TSV set and a determination unit suitable for determining abnormality of the plurality of TSVs by comparing a first test signal with each of a plurality of second test signals, wherein the first test signal is an initial test signal delayed by an amount of delay corresponding to the reference delay information, and wherein each of the plurality of second test signals is the initial test signal delayed by corresponding one of the plurality of TSVs.

Abstract: A power source circuit includes a voltage converter circuit and a control circuit that includes a voltage divider circuit and a protective circuit. The protective circuit includes a first oxide semiconductor transistor in which an off-state current is increased as temperature is increased, a capacitor that accumulates the off-state current as electric charge, a second oxide semiconductor transistor, and an operational amplifier including a non-inverting input terminal to which a reference voltage is input. The first oxide semiconductor transistor is provided near the voltage converter circuit or an element that generates heat in the control circuit.

Abstract: This disclosure describes die test architectures that can be implemented in a first, middle and last die of a die stack. The die test architectures are mainly the same, but for the exceptions mentioned in this disclosure.

Abstract: An integrated circuit structure can include a plurality of solder bumps coupled in series forming a chain and a plurality of diodes, wherein each diode is coupled to one of the plurality of solder bumps. The integrated circuit structure also can include a first pad coupled to the solder bump of the plurality of solder bumps at an end of the chain. The first pad can be configured to provide a test current responsive to application of a forward bias voltage to each diode of the plurality of diodes.

Abstract: A system and method is disclosed for functional verification of multi-die 3D ICs. The system and method include a reusable verification environment for testing each die in a stack of dies individually without having to simultaneously operate all of the dies in the stack. The system and method includes converting an input/output (“IO”) trace from a die verification test from a first format to a second format to improve performance.

Abstract: A test circuit of a semiconductor integrated circuit includes a through via, a voltage driving unit, and a determination unit. The through via is charged by receiving an input voltage. The voltage driving unit generates a test voltage by charging or discharging the through via in response to a test control signal. The determination unit compares levels of the input voltage and the test voltage and outputs a resultant signal.

Abstract: An integrated circuit (IC) structure can include a first die and a second die. The second die can include a first base unit and a second base unit. Each of the first base unit and the second base unit is self-contained and no signals pass between the first base unit and the second base unit within the second die. The IC structure can include an interposer. The interposer includes a first plurality of inter-die wires coupling the first die to the first base unit, a second plurality of inter-die wires coupling the first die to the second base unit, and a third plurality of inter-die wires coupling the first base unit to the second base unit.

Abstract: A test structure is provided for testing a semiconductor structure having a plurality of tiers. The test structure includes at least one conductive loop. Each respective conductive loop has ends defining at least one opening between the ends, and is embedded inside one or more of the plurality of tiers in the semiconductor structure. The test structure also includes at least two test pads on each respective conductive loop. The at least two test pads are connected with respective ends of each respective conductive loop. The test structure is configured to permit detection of defects within each of the plurality of tiers in the semiconductor structure if the defects exist, using a testing apparatus.

Abstract: In a semiconductor device in which semiconductor chips having a number of signal TSVs are stacked, a huge amount of man-hours have been required to perform a continuity test for each of the signal TSVs. According to the present invention, no continuity test is performed directly on signal TSVs. Dummy bumps are arranged in addition to signal TSVs. The dummy bumps of the semiconductor chips are connected through a conduction path that can pass the dummy bumps between the semiconductor chips with one stroke when the semiconductor chips are stacked. A continuity test of the conduction path allows a bonding defect on bonded surfaces of two of the stacked semiconductor chips to be measured and detected.

Abstract: An integrated circuit (70) having parallel scan paths (824-842, 924-942) includes a pair or pairs of scan distributor (800,900) and scan collector (844,944) circuits. The scan paths apply stimulus test data to functional circuits (702) on the integrated circuit and receive response test data from the functional circuits. A scan distributor circuit (800) receives serial test data from a peripheral bond pad (802) and distributes it to each parallel scan path. A scan collector circuit (844) collects test data from the parallel scan paths and applies it to a peripheral bond pad (866). This enables more parallel scan paths of shorter length to connect to the functional circuits. The scan distributor and collector circuits can be respectively connected in series to provide parallel connections to more parallel scan paths. Additionally multiplexer circuits (886,890) can selectively connect pairs of scan distributor and collector circuits together.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: A method for testing a semiconductor device includes testing the semiconductor device in a plurality of operation modes sequentially, and programming the semiconductor device to operate in at least one of the operation modes when the semiconductor device passes the testing.

Abstract: A mother substrate includes a display substrate cell defined by a scribe line, the display substrate cell including a plurality of gate lines, a gate circuit part driving the gate lines, and a gate pad part connected to the gate circuit part, a gate test pad part in a peripheral area surrounding the display substrate cell, the gate test pad part being configured to receive a gate test signal, a gate test line part connecting the gate test pad part and the gate pad part, and a switching part connected to the gate test line part and configured to control turning on and turning off of the gate test line part.

Abstract: A compliant printed circuit semiconductor tester interface that provides a temporary interconnect between terminals on integrated circuit (IC) devices being tested. The compliant printed circuit semiconductor tester interface includes at least one dielectric layer printed with recesses corresponding to a target circuit geometry. A conductive material is deposited in at least a portion of the recesses comprising a circuit geometry and a plurality of first contact pads accessible along a first surface of the compliant printed circuit. At least one dielectric covering layer is preferably applied over the circuit geometry. A plurality of openings in the dielectric covering layer are provided to permit electrical coupling of terminals on the IC device and the first contact pads. Testing electronics that to test electrical functions of the IC device are electrically coupled to the circuit geometry.

Abstract: A semiconductor integrated circuit device has a circuit block formed on a semiconductor substrate, and an electrically conductive pattern formed in an upper layer of a portion of the circuit block that is to be protected. An oscillation circuit is connected to the electrically conductive pattern, and is configured to oscillate at an oscillation frequency determined by a circuit constant of the electrically conductive pattern, and a detection circuit is configured to determine whether a preset range includes the oscillation frequency of the oscillation circuit.

Abstract: An integrated circuit includes a monitoring circuit and a monitored circuit connected with the monitoring circuit. The monitoring circuit is operable to determine during fabrication if a resistance of a connection between an in-fab redistribution layer connector and a post-fab redistribution layer connector exceeds a threshold.

Abstract: A leakage current detection method and apparatus are provided. The method is applied to leakage current detection for a board-mounted component on a printed circuit board assembly (PCBA) board, and includes: providing a fixed voltage for a leakage current input end of a board-mounted component under detection, and connecting a leakage current output end to an inverting input end of an operational amplifier of a resistance testing module, where the resistance testing module includes the operational amplifier and a reference resistor that is connected between the inverting input end of the operational amplifier and the leakage current output end; detecting an output voltage of the resistance testing module; and calculating, based on Ohm's law and according to the output voltage and the reference resistor, a leakage current flowing through the board-mounted component under detection.

Abstract: A semiconductor device capable of simplifying wiring work is provided. A semiconductor device includes a semiconductor element (insulated gate bipolar transistor IGBT) provided with an emitter main electrode and an emitter sense electrode, an integrated circuit having a detection terminal and a mold resin body that seals the semiconductor element and the integrated circuit, and a lead. The lead is provided with an inner lead part sealed in the mold resin body and electrically connected to the emitter sense electrode, an inner lead part sealed in the mold resin body and electrically connected to the emitter main electrode, and an outer lead part connected to the lead part on one side, connected to the inner lead part on the other side and exposed outside the mold resin body.

Abstract: A method of detecting a defect of a semiconductor device includes forming test patterns and unit cell patterns in a test region a cell array region of a substrate, respectively, obtaining reference data with respect to the test patterns by irradiating an electron beam into the test region, obtaining cell data by irradiating the electron beam into the cell array region, and detecting defects of the unit cell patterns by comparing the obtained cell data with the obtained reference data.

Abstract: Crack sensors for semiconductor devices, semiconductor devices, methods of manufacturing semiconductor devices, and methods of testing semiconductor devices are disclosed. In one embodiment, a crack sensor includes a conductive structure disposed proximate a perimeter of an integrated circuit. The conductive structure is formed in at least one conductive material layer of the integrated circuit. The conductive structure includes a first end and a second end. A first terminal is coupled to the first end of the conductive structure, and a second terminal is coupled to the second end of the conductive structure.

Abstract: In a method of testing integrated circuit devices, a parameter, such as initial voltage may first be measured. A low pass filter operation may be applied to the measured data to generate peer data. A particular integrated circuit device may be identified as failed or rejected when its measured parameter varies sufficiently relative to the peer data.

Abstract: A test circuit is described of a circuit integrated on wafer of the type comprising at least one antenna of the embedded type comprising at least one test antenna associated with said at least one embedded antenna that realizes its connection of the wireless loopback type creating a wireless channel for said at least one embedded antenna and allows its electric test, transforming an electromagnetic signal of communication between said at least one embedded antenna and said at least one test antenna into an electric signal that can be read by a test apparatus.

Abstract: An array substrate has a plurality of gate signal lines, a plurality of source signal lines orthogonal to the plurality of gate signal lines, a plurality of gate-driver mounting terminals, a plurality of source-driver mounting terminals, a plurality of gate-side array inspection terminals connected to the gate signal lines, a plurality of source-side array inspection terminals connected to the source signal lines, a plurality of gate lead wire disconnection inspection circuits connected between the plurality of gate-driver mounting terminals and a common terminal for a gate lead wire disconnection inspection, and a plurality of source lead wire disconnection inspection circuits connected between the plurality of source-driver mounting terminals and a common terminal for a source lead wire disconnection inspection.

Abstract: A measuring device is provided, the measuring device including: a power supply to provide electric power to a chip via at least one of a chip connection and a chip-carrier connection; a chip arrangement receiving portion configured to receive a chip arrangement, the chip arrangement including a chip and a plurality of chip-to-chip-carrier connections; a detection portion including: a plate; a detection circuit coupled to the plate and configured to detect an electrical signal from the plate; wherein the plate is configured such that it covers at least part of the chip arrangement; and wherein at least one chip-carrier connection is in electrical connection with the plate.

Abstract: A method of detecting a crack in a semiconductor die is provided. The method includes the following steps. A semiconductor die having an outer edge is provided, wherein a conductive feature is formed on semiconductor die along the outer edge. The conductive feature is biased, and a leakage current of the semiconductor die is measured, such that the crack propagating in the semiconductor the is detected. A semiconductor the with a layout for detecting a die crack and the method of manufacturing it are also provided. The semiconductor the includes a semiconductor the having an cuter edge, and a conductive feature on the semiconductor die along the outer edge. The conductive feature is configured to be biased by an external pin.

Abstract: An apparatus for a monolithic integrated circuit die is disclosed. In this apparatus, the monolithic integrated circuit die has a plurality of modular die regions. The modular die regions respectively have a plurality of power distribution networks for independently powering each of the modular die regions. Each adjacent pair of the modular die regions is stitched together with a respective plurality of metal lines.

Abstract: An integrated circuit is provided having an active circuit. A heating element is adjacent to the active circuit and configured to heat the active circuit. A temperature sensor is also adjacent to the active circuit and configured to measure a temperature of the active circuit. A temperature controller is coupled to the active circuit and configured to receive a temperature signal from the temperature sensor. The temperature controller operates the heating element to heat the active circuit to maintain the temperature of the active circuit in a selected temperature range.

Abstract: A method of testing an integrated circuit clearance distance device (“ICCDD”) having a predetermined clearance distance in air requirement and a predetermined isolation voltage limit including calculating a value of the breakdown voltage at the predetermined clearance distance for at least one gas; and selecting a gas in which the ICCDD has a breakdown voltage that is less than the predetermined isolation voltage.

Abstract: Provided are microfabricated probe elements, including elastomer elements, and methods of making the same, that can be readily used with fine pitch microelectronic arrays, for instance by providing sufficient compliance in a small package, while minimizing deflection forces, and while precisely maintaining the planarity and positioning of the contact tips across vast grid arrays. Elastomer elements may be generated using photolithography, either directly or through a sacrificial lost-mold process. Elastomer probe elements are provided with rigid tip structures microfabricated thereon to improve contact pressure. A novel space transformation probe card assembly is also provided.

Abstract: A test system for testing an antenna tuning element is provided. The test system may include a tester, a test fixture, and a probing structure. The probing structure may include probe tips configured to mate with corresponding solder bumps formed on a device under test (DUT) containing an antenna tuning element. The DUT may be tested in a shunt or series configuration. The tester may be electrically coupled to the test probe via first and second connectors on the test fixture. An adjustable load circuit that is coupled to the second connector may be configured in a selected state so that a desired amount of electrical stress may be presented to the DUT during testing. The tester may be used to obtain measurement results on the DUT. Systematic effects associated with the test structures may be de-embedded from the measured results to obtain calibrated results.

Abstract: An optical die probe wafer testing circuit arrangement and associated testing methodology are described for mounting a production test die (157) and surrounding scribe grid (156) to a test head (155) which is positioned over a wafer (160) in alignment with a die under test (163) and surrounding scribe grid (161, 165), such that one or more optical deflection mirrors (152, 154) in the test head scribe grid (156) are aligned with one or more optical deflection mirrors (162, 164) in the scribe grid (161, 165) for the die under test (163) to enable optical die probe testing on the die under test (163) by directing a first optical test signal (158) from the production test die (157), through the first and second optical deflection mirrors (e.g., 152, 162) and to the first die.

Abstract: A semiconductor test method includes attaching a sheet to a wafer on which a plurality of chips are formed, the sheet having a plurality of holes, each of which corresponds to a position of one of the chips, dicing the wafer to separate the plurality of chips into individual chips while the sheet remains attached to the individual chips, and after the dicing and while the sheet remains attached to the individual chips, measuring the electrical characteristics of the chips.

Abstract: An electric current application method for applying electric current to a power semiconductor 100 having a first signal pin contact region 102 that conducts a first electric current, and a contacting body contact region 101 that electrically connects with the first signal pin contact region 102 and conducts a second electric current, includes a Step S1 of contacting a first signal pin 32 of a probe device 1 to the first signal pin contact region 102 so as to eliminate residual electricity remaining in the first signal pin contact region 102 and contacting body contact region 101; and Steps S3 and S4 of contacting a contacting part 21 of the contacting body 2 of the probe device 1 to the contacting body contact region 101, and conducting the first electric current and second electric current, after Step S1.

Abstract: A system for monitoring a connection to an active pin of an integrated circuit (IC) die, includes an input/output (I/O) cell of an IC die, where the I/O cell is bonded to a bonding pad on a ball grid array (BGA) substrate. The system includes a test point on a printed circuit board (PCB) coupled to the bonding pad which forms an electrical/conductive pathway between the test point and the I/O cell. The system includes a clock waveform injected through a resistor into the test point.

Abstract: An exemplary structure for testing an integrated circuit includes a semiconductor substrate and first and second via chains disposed over the substrate. The via chains include a substantially same sequence of segments interconnected at N via regions by a respective first and second via arrangement. The first via arrangement includes MN first vias at each respective via region and the second via arrangement includes MN+KN second vias at each respective via region. The first via arrangement is different than the second via arrangement and KN?1 for at least one via region. The structure includes a voltage sensing apparatus in electrical connection with each via chain and configured to drive a first constant current through the first via chain and to drive a second constant current through the second via chain to measure a differential voltage between the via chains.

Abstract: A test controller applies test stimulus signals to the input pads of plural die on a wafer in parallel. The test controller also applies encoded test response signals to the output pads of the plural die in parallel. The encoded test response signals are decoded on the die and compared to core test response signals produced from applying the test stimulus signals to core circuits on the die. The comparison produces pass/fail signals that are loaded in to scan cells of an IEEE 1149.1 scan path. The pass/fail signals then may be scanned out of the die to determine the results of the test.

Abstract: An integrated circuit has a controllable switching element, the load path of which is arranged between an output of the integrated circuit and a supply potential. A test unit is connected to the connections of the switching element in order to carry out tests. A control unit is connected to the test unit via at least one control line. The sequence of tests is carried out dependent on signals on the control line(s). A memory is connected to the control unit the content and the type of which determines the time of the tests. The memory is connected to an input of the integrated circuit in order to enter the content.

Abstract: An embodiment of a method to characterize a die is disclosed. The embodiment of the method includes measuring a quality metric of the die, and determining, prior to a final test stage, whether the quality metric of the die satisfies a first constraint, where the first constraint is more stringent than a second constraint at the final test stage for the quality metric of the die.

Abstract: A system and method is disclosed for adaptively adjusting a driving strength of a signal between a first and second chip in a 3D architecture/stack. This may be used to adaptively calibrate a chip in a 3D architecture/stack. The system may include a transmission circuit on one chip and a receiver circuit on another chip. Alternatively, the system may include a transmission and receiver circuit on just one chip.

Abstract: An embodiment relates to an integrated circuit comprising at least two electrical connections and at least one coil arranged adjacent to at least one of the electrical connection, wherein the at least one coil each comprises at least one winding and wherein the at least one coil is arranged on or in the integrated circuit.

Abstract: Methods and systems to measure a signal on an integrated circuit die. An on-die measurement circuit may measure an on-die signal relative to an off-die generated reference signal, which may include a series of increasing voltage steps. The on-die measurement circuit may continuously compare voltages of the on-die signal and the off-die generated reference signal, and may generate an indication when the off-die reference signal exceeds the on-die signal. The measurement circuit may generate the indication from a voltage source other than the on-die signal to be measured, and/or may generate the indication with a relatively large voltage swing. The indication may be output off-die for evaluation, such as for testing, debugging, characterization, and/or operational monitoring. A unity gain analog buffer may be provided to tap the on-die signal proximate to a node of interest, which may be implemented within the on-die measurement circuit.

Abstract: A plurality of sets of test conditions of a die in a stacked system is established, wherein the plurality of test conditions are functions of temperatures of the die, and wherein the stacked system comprises a plurality of stacked dies. A temperature of the die is measured. A respective set of test conditions of the die is found from the plurality of sets of test conditions, wherein the set of test conditions corresponds to the temperature. The die is at the temperature using the set of test conditions to generate test results.

Abstract: An integrated circuit comprises at least one pin and has at least one resistor connected between a reference voltage and the at least one pin. Current measurement circuitry applies a voltage across the at least one resistor and measures a current at the at least one pin responsive to the applied voltage in a first mode of operation. The measured current enables determination of a current limit set point for the integrated circuit. In a second mode of operation, the at least one resistor comprises a pull up resistor and the at least one pin that is connected to the at least one resistor comprises an open-drain output.

Abstract: The present invention discloses a method of testing a partially assembled multi-die device (1) by providing a carrier (300) comprising a device-level test data input (12) and a device-level test data output (18); placing a first die on the carrier, the first die having a test access port (100c) comprising a primary test data input (142), a secondary test data input (144) and a test data output (152), the test access port being controlled by a test access port controller (110); communicatively coupling the secondary test data input (144) of the first die to the device-level test data input (12), and the test data output (152) of the first die to the device-level test data output (18); providing the first die with configuration information to bring the first die in a state in which the first die accepts test instructions from its secondary test data input (144); testing the first die, said testing including providing the secondary test data input (144) of the first die with test instructions through the device-