Abstract: A system for equalizing transition density in an integrated circuit includes a first circuit configured to transition according to a data stream; and a second circuit configured to transition at a time when the first circuit is not transitioning.

Abstract: An impedance adjusting circuit for adjusting an impedance of an output buffer of a DDR2 memory, using an OCD impedance adjusting function, from a side of a memory controller, includes first and second terminals, first and second switches, a comparator, and a control circuit. The DDR2 memory has an OCD impedance adjusting function and includes a first output buffer and a second buffer each having a pull-up buffer and a pull-down buffer that receive an input signal in common and with impedances thereof capable of being variably set. The first and second terminals receive first and second signals output from the first buffer and the second buffers, respectively. The first and second switches are connected between the first terminal and the second terminal in series. The comparator compares a reference voltage VREF with a voltage at a connection node between the first and second switches.

Abstract: An output buffer for an IC includes a PMOS transistor having a source coupled to an operating voltage, and an NMOS transistor serially coupled between a drain of the PMOS transistor and a complementary operating voltage. A first driver is coupled to a gate of the PMOS transistor for selectively turning on or off the same. A second driver is coupled to a gate of the NMOS transistor for selectively turning on or off the same. A decoder is coupled to the first and second drivers for controlling the first driver or the second driver to turn on the PMOS transistor or the NMOS transistor at a high rate or a low rate in response to slew rate control signals indicating a slew rate control mode or a non-slew rate control mode.

Abstract: A signal encoder and a signal decoder involves the signal encoder for receiving a data signal and a clock signal, including a first code output terminal and a second code output terminal. When the data signal is logic one, the signal encoder outputs a modulated signal through the first code output terminal, and outputs a fixed level signal through the second code output terminal. When the data signal is logic zero, the signal encoder outputs the fixed level signal through the first code output terminal, and outputs the modulated signal through the second code output terminal. The signal decoder converts the modulated signal and the fixed level signal output from the signal encoder into the data signal and the clock signal.

Abstract: An output amplifier is provided for use in a bidirectional communications interface, for example, connecting a transmitter and a receiver to a transmission line. The output amplifier includes a differential amplifier pair connected to output circuitry. The differential amplifier pair receives differential data signal pairs from each of a transmission line and a transmitter. The output circuitry receives signals from the differential amplifier pair and, in response, forms single-ended output logic signals. The output amplifier suppresses electronic input noise throughput using an asymmetric transfer characteristic that offsets output signal logic levels with respect to input noise signal levels. The asymmetric transfer characteristic is produced by skewing a transfer characteristic of the differential amplifier pair using an asymmetrical transistor configuration at an output side of the differential amplifier pair.

Abstract: Apparatus, methods, and systems include an off-chip driver having an output drive coupled in parallel with the off-chip driver to provide initial drive emphasis for a period of time. The output drive may include a first transistor and a second transistor coupled to an output of the off-chip driver to provide additional initial drive emphasis strength when both transistors are energized for an initial period of time. The time period may be set by an inverted delay circuit.

Abstract: A method for saving electrical power for a physical layer (PHY) device including a plurality of sub-circuits is disclosed. The method includes the steps of outputting a plurality of link pulses, asserting a plurality of disabling signals between two adjacent link pulses for disabling the sub-circuits, respectively, and deasserting the disabling signals for enabling the sub-circuits, respectively. The disabling signals are asserted separately for disabling the sub-circuits at different time points. A physical layer device for use in a chip for saving electrical power is also disclosed.

Abstract: The invention relates to a method and a device for transmission with reduced crosstalk in interconnections used for sending a plurality of signals, such as the interconnections made with flat multiconductor cables, or with the tracks of a printed circuit board, or inside an integrated circuit. An interconnection with four parallel transmission conductors plus a reference conductor has each of its ends connected to a termination circuit. The transmitting circuit receives at its input the signals of the four channels of the source and its output terminals are connected to the conductors of the interconnection. The receiving circuit(s) input terminals are connected to the conductors of the interconnection, and its four output channels are connected to the destination. The signals of the four channels of the source are sent to the four channels of the destination, without noticeable crosstalk.

Abstract: An output device is disclosed that includes an impedance matching section including an impedance adjustment section, and a dummy circuit section having the same configuration as the impedance adjustment section and adapted to calculate an adjustment value for matching an output impedance to a characteristic impedance of the transmission line. The impedance matching section sets the adjustment value to an impedance adjustment section, thereby matching the output impedance to the characteristic impedance. The output device further includes a switching transistor configured to be turned on/off so as to switch the output between an H level and an L level, and a constant current driver configured to add a constant current to the output.

Abstract: A method and apparatus for noise suppression. A circuit has a noise detection unit, a noise suppression unit, and a control unit. The noise suppression unit has an input and an output, wherein the input of the noise detection unit is connected to a signal and generates a signal change at the output if a change in the signal is detected. The noise suppression unit has an input and an output, wherein the input of the noise suppression unit is connected to the output of the noise detection unit and generates a correction to the signal in response to detecting the signal change at the output of the noise detection unit. The control unit has an input and an output, wherein input to the control unit is connected to the signal and turns off the noise suppression unit if a state change is detected in the signal.

Abstract: Methods are provided to reduce offsets and timing skews in data signals captured in a data receiver by adaptively adjusting a transition threshold of the data receiver. A set of adjustment vectors for adjusting the transition threshold of the data receiver are generated. In an embodiment, adjustment is provided using differential clock signals and a reference voltage to generate the set of adjustment vectors to be provided to the data receivers.

Abstract: A controlling method of logic operations is used to control a plurality of logics inside a chip, which is in a power peak state. The controlling method comprises the following steps of: providing a control signal to the chip, controlling at least one of the logics based on the control signal at a first timing, and controlling at least another one of the logics based on the control signal at a second timing. The control signal is intent to substantially control actions of the logics synchronously. Moreover, a mainboard and an electronic component, utilizing the controlling method of logic operations, are provided.

Abstract: A signature circuit in a semiconductor chip includes a signature program circuit configured to be programmed with signature information and to output a signature signal in response to the signature information; a signature output circuit configured to block the signature signal output by the signature program circuit during operation in a normal mode, and configured to pass the signature signal during operation in a test mode; and a pad-driving transistor directly coupled to the pad, configured to drive the pad during operation in the normal mode in response to an operation command, and configured to drive the pad during operation in the test mode in response to the signature signal output by the signature output circuit. The signature circuit outputs the signature information through a transistor for adjusting impedance to reduce a chip size by omitting an additional logic circuit for the signature circuit.

Abstract: A description is given of an arrangement for compensation of ground offset in a data bus system comprising a plurality of communication devices (2, 10) which are each supplied with an operating voltage (U0) by a voltage source (4; 14), are connected to ground (G1); G2) and have a data bus connection (6; 12) via which they are connected to a data bus line (8). The special thing about the invention is that between operating voltage (U0) and ground (G2) at least one voltage dividing device (R3, R6) is connected whose output is coupled to the data bus connection (12) of at least one communication device (10) and whose voltage dividing ratio is selected such that an offset of the ground (G2) of the communication device (10), whose data bus connection (12) is coupled to the voltage dividing device (R3, R6), is in essence compensated compared to ground (G1) of another communication device (2).

Abstract: Configurable voltage mode transmitter architectures are based on combinations of drive cells and parallel termination cells connected in parallel across an external load to provide configurable output characteristics. Each drive cell and parallel termination can be individually enabled, various configurations of enabled cells providing the output characteristics configurability. In some embodiments, dedicated or configured pre-emphasis drive cells with individual enablement capability are added. In some embodiments, pull-down and pull-up cells with individual enablement capability are added to provide additional configurability options. When present, the pre-emphasis, pull-down and pull-up cells are connected in parallel across the external load to provide pre-emphasis features to the output.

Abstract: A semiconductor memory device according to the present invention can change adjusting timing of ODT operation in convenience and have an optimized ODT timing whether the semiconductor memory device is putted on ether rank of a module. The present invention includes an impedance adjusting unit for adjusting an impedance value of an input pad in response to an impedance selecting signal; an ODT operating control unit for controlling the impedance adjusting unit as generating the impedance selection signal using an decoding signal and an ODT timing signal; a delay adjusting unit for delaying an internal control clock for a predetermined timing to thereby generate the ODT timing signal; and an ODT timing control unit for controlling the delay adjusting unit to decide the value of the predetermined timing according to whether or not the semiconductor memory device is arranged to a first rank or a second rank in a module.

Abstract: A compensation circuit and a method that compensates for process, voltage and temperature (PVT) variations in an integrated circuit that includes functional modules. The compensation circuit includes a signal generator, a first code generator, a second code generator, and a mapping module. The signal generator generates a first signal and a second signal depending on aligned process corner, voltage and temperature variations and skewed process corner variations respectively. The first code generator receives the first signal, and generates a first calibration code. The second code generator receives the second signal, and generates a second calibration code. The mapping module provides the first and second calibration codes for compensating for the aligned process corner, voltage and temperature variations and the skewed process corner variations associated with the functional modules respectively.

Abstract: In one embodiment of the invention, an integrated circuit, such as an FPGA, has one or more programmable termination schemes, each having a plurality of resistive termination legs connected in parallel, and a calibration circuit designed to control each termination scheme for process, voltage, and temperature (PVT) variations. The sense element in the calibration circuit and each resistive leg in each termination scheme has a transistor-based transmission gate connected in series with a non-silicided poly (NSP) resistor. The negative temperature coefficient of resistivity of each NSP resistor offsets the positive temperature coefficient of resistivity of the corresponding transmission gate to provide a temperature-independent sense element and temperature-independent termination legs.

Abstract: A triple latch flip flop system and method are disclosed. In one embodiment, triple latch flip-flop system includes a pull up latch, a pull down latch, a primary latch and an output. The pull up latch drives a pull up node. The pull down latch driving a pull down node. The primary latch records state of the triple latch flip-flop system. The output for outputting a logic value based upon outputs of the pull up latch, pull down latch and the primary latch.

Abstract: Line load compensation and reflection reduction in a signal transmitting circuit is provided using feedback capacitors. The feedback capacitor serially coupled with a resistance generates an RC rise/fall time that is independent of the line load. Additionally, by selecting a capacitor that yields a rise/fall time of approximately ? of the maximum bit transmission time, signal reflection on the signal line can be reduced. Accordingly, by incorporating the feedback capacitor with a differential drive circuit, such as the IB 485 driver, variations in line load can be compensated for while also reducing signal reflection due to un-terminated or improperly terminated signal lines, thus allowing a free topology implementation.

Abstract: An integrated circuit device having graduated on-die termination. The integrated circuit device includes an input to receive a data signal, and first and second termination circuits. The first termination circuit includes a first load element and a first switch element to switchably couple the first load element to the data signal input. The second termination circuit includes a second load element and a second switch element to switchably couple the second load element to the data signal input.

Abstract: A switching system capable of reducing the noise of the output signal is provided. The switching system includes a first switch and a second switch, wherein the first switch conducts a first signal according to a first control signal; the second switch conducts a second signal according to a second control signal. And the voltages of the first control signal and the second control signal are restricted within a voltage interval to reduce the noise produced during the switching of the switches.

Abstract: The invention relates to a method and a device for transmission with reduced crosstalk in interconnections used for sending a plurality of signals, such as the interconnections made with flat multiconductor cables, or with the tracks of a printed circuit board, or inside an integrated circuit. An interconnection with four parallel transmission conductors plus a reference conductor has each of its ends connected to a termination circuit. The transmitting circuit receives at its input the signals of the four channels of the source and its output terminals are connected to the conductors of the interconnection. The receiving circuit(s) input terminals are connected to the conductors of the interconnection, and its four output channels are connected to the destination. The signals of the four channels of the source are sent to the four channels of the destination, without noticeable crosstalk.

Abstract: Various methods, apparatuses and systems are described in which a skew delay time between communication lanes is determined. A data transfer path is established which includes two or more communication lanes in a communication link. A skew delay time is determined between the communication lanes of the communication link with respect each other with using a clock period of a input output circuit as a reference time.

Abstract: A data input/output circuit of a semiconductor memory device has a data inversion determination function. In an input mode, the data input/output circuit inverts an input data group in response to an input inversion flag and transmits the inverted input data group to a memory cell array. In an output mode, the data input/output circuit inverts a data group, output from the memory cell array, when the output data group satisfies a predetermined inversion condition, and transmits the inverted output data group to the outside of the data input/output circuit. In this case, an output inversion flag, indicating that the output data group is to be inverted, is generated. Further, the data input/output circuit stores the input inversion flag in the memory cell array in the input mode, and compares the input inversion flag, stored in the memory cell array, with the output inversion flag in the output mode.

Abstract: A differential input circuit with lower power consumption and noise is disclosed. Rather than completely discharging output nodes differential circuits, the present invention equalizes the output nodes to conserver power and to reduce noise. Specifically, an equalization circuit is coupled between the output nodes of the low power and low noise differential input circuit.

Abstract: An output buffer includes at least a first and a second stage, wherein each stage is formed by respective first transistors and second transistors coupled in series with each other between a first and a second voltage reference. The coupled first and second transistors have a common conduction terminal connected to an output terminal of the output buffer. An input terminal of the buffer is connected to control terminals of the transistors of the first stage through a first open loop driving circuit. A second feedback driving circuit is connected between the input terminal and the control terminals of the transistors of the second stage. The second feedback driving circuit includes a current detector operating to detect a maximum in the value of the current drawn by and supplied to the output buffer. A comparison block, having a threshold value, detects current in excess of the threshold value and processes information coming from the current detector to regulate an output impedance value of the output buffer.

Abstract: Circuits and methods are provided for producing a rail-to-rail output voltage. A circuit includes a level shifter and a source follower. The level shifter receives an input signal and applies a compensation voltage to the input signal relative to a voltage level of the input signal in steady-state. The source follower produces an output signal and, responsive to variations in the voltage level of the input signal, changes the voltage level of the output signal.

Abstract: Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.

Abstract: An output amplifier is provided for use in a bidirectional communications interface, for example, connecting a transmitter and a receiver to a transmission line. The output amplifier includes a differential amplifier pair connected to output circuitry. The differential amplifier pair receives differential data signal pairs from each of a transmission line and a transmitter. The output circuitry receives signals from the differential amplifier pair and, in response, forms single-ended output logic signals. The output amplifier suppresses electronic input noise throughput using an asymmetric transfer characteristic that offsets output signal logic levels with respect to input noise signal levels. The asymmetric transfer characteristic is produced by skewing a transfer characteristic of the differential amplifier pair using an asymmetrical transistor configuration at an output side of the differential amplifier pair.

Abstract: An open drain output circuit for use as an I2C bus interface. The open drain output circuit includes an output terminal. An input unit performs a first operation causing the potential at the output node to steeply fall and a second operation for gradually raising the potential in accordance with transition of an input signal. An output transistor connected to the output node of the input unit and the output terminal is turned OFF in the first operation and turned ON in the second operation. A delay time adjustment circuit reduces the difference between a delay time from transition of the input signal until when the output transistor is turned OFF in the first operation and a delay time from transition of the input signal until when the output transistor is turned ON in the second operation.

Abstract: Apparatus controlling the driver output slew rate that includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to facilitate control of the slew rate of the output signal. A delay circuit having a time delay proportional to a desired transition time of the driver output signal is coupled to the output of the driver circuit. A first comparator detects when the driver output signal rises through a specified level, and a second comparator detects when the driver output falls through a second specified level. A phase detector is coupled to outputs of the first and second comparators and an output of the delay circuit for aligning the phases of the comparator outputs and the delayed comparator outputs by adjusting the driver output slew rate.

Abstract: A method and system for minimizing sub-threshold leakage in a logic block is disclosed. An NDR isolation device is coupled between the logic block and ground to form a virtual ground node. To put the logic block into sleep mode, the virtual ground control device raises the voltage at the virtual ground node above an isolation voltage, which causes NDR isolation device isolates the virtual ground node from ground. The virtual ground control device can then raise the voltage at the virtual ground node to the positive supply voltage to eliminate sub-threshold leakage currents the logic block. Alternatively, the virtual ground control device can raise the voltage at the virtual ground node to the positive supply voltage minus a retention voltage so that storage elements in the logic block can retain state information while still greatly reducing sub-threshold leakage current.

Abstract: An output buffer having slew-rate control and crossbar current control includes a pull-up PMOS transistor, a pull-down NMOS transistor, a pull-up network coupled to the gate of the pull-up PMOS transistor, and a pull-down network coupled to the gate of the pull-down NMOS transistor.

Abstract: Apparatus for transmitting a digital signal within, for example, an integrated circuit includes a signal transmission line with a directional coupler at one or both ends. The directional coupler blocks the direct-current component of the digital signal while transmitting the alternating-current component, including enough higher harmonics to transmit a well-defined pulse waveform. A suitable directional coupler consists of two adjacent line pairs in materials with different dielectric constants. The apparatus may also include a driver of the inverter type, a receiver of the differential amplifier type, a terminating resistor, and a power-ground transmission line pair for supplying power to the driver. An all-metallic transmission-line structure is preferably maintained from the output interconnections in the driver to the input interconnections in the receiver.

Abstract: A circuit for balancing delays through true and complement phases of complementary drivers includes: a first driver; a second driver; a first delay device coupled to an input of the first driver and having an input coupled to an input signal node; a second delay device coupled to an input of the second driver and having an input coupled to the input signal node through a first inverter, wherein the first and second delay devices are clocked such that an input signal reaches the first driver simultaneously with an inverted input signal reaching the second driver.

Abstract: As technology scales, on-chip interconnects are becoming narrower, and the height of such interconnects is not scaling linearly with the width. This leads to an increase of coupling capacitance with neighboring wires, leading to higher crosstalk. It also leads to poor performance due to poor RC response at the receiving of the wire, which may even result in failure in very noisy environments. An adaptive threshold scheme is proposed in which receiver switching thresholds are adjusted according to the detected noise in bus lines. These noise levels are dependent on both the front-end processing (transistor performance) as well as on the backend processing (metal resistance, capacitance, width and spacing). The circuit therefore automatically compensates for process variations.

Abstract: An integrated circuit requires on-chip termination resistor for minimizing reflections from input signals supplied by an external signal source. The input signal is applied across two bonding pads which serve as input terminals for the integrated circuit. The first bonding pad is coupled to a first on-chip terminating resistor through a first on-chip inductor. The second bonding pad is coupled to a second on-chip terminating resistor though a second on-chip inductor. The two on-chip inductors are arranged in a transformer configuration where the mutual inductance relative to the applied input signal is negative. During operation, the on-chip transformer arrangement effectively shorts common-mode signals to the on-chip terminating resistors and effectively blocks differential-mode signals from the on-chip terminating resistors. Effective bandwidth and common-mode rejection performance is improved with the described on-chip transformer arrangement.

Abstract: Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.

Abstract: Apparatus and method for controlling the driver output slew rate. The apparatus includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to facilitate control of the slew rate of the output signal. A delay circuit having a time delay proportional to a desired transition time of the driver output signal is coupled to the output of the driver circuit. A first comparator detects when the driver output signal rises through a specified level, and a second comparator detects when the driver output falls through a second specified level. A phase detector is coupled to outputs of the first and second comparators and an output of the delay circuit for aligning the phases of the comparator outputs and the delayed comparator outputs by adjusting the driver output slew rate.

Abstract: An output level stabilization circuit being an output level stabilization circuit for a CML circuit, the output level stabilization circuit includes: a replica circuit constituted of transistors respectively having the same characteristics as one of differential-pair transistors of the CML circuit and a current source transistor; a comparison circuit which compares an output of the replica circuit with a reference voltage and supplies the comparison result as a control voltage for the current source transistor of the replica circuit; and a variable impedance circuit arranged between the output of the replica circuit and an input of the comparison circuit.

Abstract: An integrated circuit includes a plurality of inputs, a plurality of output pads, a programmable logic block, an analog circuit block, an analog-to-digital converter programmably coupleable to individual analog circuits in the analog circuit block, and an interconnect architecture programmably coupling selected ones of the plurality of inputs, the plurality of outputs, the programmable logic block, the analog circuit block, and the analog-to-digital converter. At least one of the inputs may be programmably configured as one of a digital input programmably coupleable to elements in the programmable logic block or as an analog input to an analog circuit in the analog circuit block.

Abstract: A data driver drives a data signal on a channel, and a current mode driver drives a varying current on the channel to reduce crosstalk.

Abstract: Circuits and related methods are provided for buffering reference voltages from noise associated with output driver transistors. In one example, an output driver buffer circuit includes an output driver transistor adapted to adjust an output voltage of an output pad. The circuit also includes a pre-driver circuit connected to a gate of the output driver transistor. The pre-driver circuit is adapted to receive a reference voltage to control the output driver transistor. The pre-driver circuit includes a precharged capacitor, a first switch adapted to connect the capacitor to the gate, and a second switch adapted to connect the reference voltage to the gate. The second switch is adapted to operate following a time period after the capacitor is connected to the gate. The capacitor is adapted to buffer noise associated with the output driver transistor during the time period.

Abstract: A high speed serial data communication system includes provisions for the correction of equalization errors, particularly those errors introduced by equalizer non-idealities. The equalization is achieved at the data transmitter, and is based on dynamic current subtraction at the output of a differential pair. When bit time>0, the error current is removed or subtracted from the total driver current, thereby maintaining a constant total current from bit time 0 to bit time>0. The same result can also be achieved by subtracting current when bit time>0 using field effect transistors of the opposite gender. The error current can be determined empirically from simulation or through feedback using a replica of the driver. The circuits for achieving equalization error correction and the resulting electrical network analysis are shown and described.

Abstract: A driving circuit is for an output buffer stage, with high speed and reduced noise induced on the power supply. The driving circuit may include first and second circuit portions, each intended for the generation of a respective driving signal for a corresponding transistor of the buffer stage. Each portion may include a final stage with a complementary pair of MOS transistors inserted between two supply voltage references, and a third MOS transistor having its conduction terminals connected between one of the voltage references and an interconnection node of the complementary pair and receiving, on its control terminal, an activation pulse signal coming from a logic network incorporating at least one delay chain.

Abstract: A static latch circuit is used to suppress crosstalk glitch in a synchronous digital integrated circuit. A static latch is inserted into a selected victim net, and the net is examined if crosstalk glitch induced in the selected victim net is sufficiently suppressed. If not, then the selected victim net is examined to check whether the crosstalk glitch is primarily due to propagated noise from an earlier stage or due to noise injected in the selected victim net. If the crosstalk glitch is propagated from an earlier stage, then a second static latch is inserted before the state in which the first static latch is inserted. Alternatively, another static latch may be inserted in the selected victim net. Cell libraries including a variety of static latch circuit architectures can be designed.

Abstract: A differential line compensation apparatus is disclosed that has a first terminal to receive a first differential signal supplied by a first trace and a second terminal to receive a second differential signal supplied by a second trace. The apparatus has at least one detector to detect a first condition of a first signal at least related to the first differential signal, and a second condition of a second signal at least related to the second differential signal and to provide an output containing the results of the detections. A comparator is coupled to the at least one detector to receive and process the at least one output and to provide a control output. At least one delay controller receives the control output and applies a phase correction to a selected one of the first signal and the second signal. A corresponding method and system are also disclosed.

Abstract: A bussed system with a fast and compact majority voter in the circuitry responsible for the bus inversion decision. The majority voter is implemented in analog circuitry having two branches. One branch sums the advantage of transmitting the bits without inversion, the other sums the advantage of transmitting the bits with inversion. The majority voter computes the bus inversion decision in slightly more than one gate delay by simultaneously comparing current drive in each branch.

Abstract: In a dead time control circuit, a delay circuit is connected to an input terminal and adapted to delay signals therethrough by a delay time corresponding to a dead time. A logic circuit has a first input connected via the delay circuit to the input terminal, a second input connected directly to the input terminal, and an output connected to an output terminal. The dead time having adjustable temperature characteristics.