Abstract: An integrated circuit that includes a gate control voltage generator that supplies a current control gate voltage to a plurality of current control devices of a corresponding plurality of dynamic logic circuits each having a keeper circuit. The gate control voltage generator provides, via current control gate voltage, global control of the amount of keeper current flowing through the keeper circuits so as to enhance the performance of the dynamic logic circuits.

Abstract: A control apparatus comprises a voltage source, a controlling unit and an enabling unit. The controlling unit receives an input signal and generates an output signal. The enabling unit controls whether the controlling unit generates the output signal or not according to an enabling signal. The enabling unit comprises a first switch, a second resistor, a third resistor and a third transistor. The first switch selectively turns on or off according to the enabling signal. A first terminal of the second resistor is coupled to the first switch. A first terminal of the third resistor is coupled to a second terminal of the second resistor and a second terminal of the third resistor is coupled to the ground terminal. A source of the third transistor is coupled to the ground terminal and a gate of the third transistor is coupled between the second and the third resistor.

Abstract: An output circuit includes a differential section configured to amplify an inputted differential signal; a current source section configured to supply a current to the differential section; a load resistance section connected with the differential section; and a control unit configured to set a value of the current from the current source section and a resistance value of the load resistance section based on a signal supplied to the control unit. The output circuit converts the differential signal into an output signal of a different interface level from that of the differential signal and balance-transmits the output signal.

Abstract: In one embodiment, a pre-driver circuit comprises input circuitry connected to receive a digital input signal that alternates between an upper voltage rail and a lower voltage rail and to provide a first inverted signal that is an inversion of the digital input signal and a second inverted signal that is an inversion of the first inverted signal. The pre-driver circuit also includes actuation circuitry connected to be driven by the digital input signal, the first inverted signal, and the second inverted signal to produce a digital output signal that alternates between an upper limit that is less than the upper rail and a lower limit that is greater than the lower rail by at least an amount, wherein all transistors forming the actuation circuitry comprise a single channel type.

Abstract: A driving circuit includes a pair of input ports, a pair of differential output ports, a first differential pair, a second differential pair, a load unit, and a current source. The first differential pair is directly connected to a first voltage level, and is coupled to the pair of input ports and the pair of differential output ports. The second differential pair is coupled to the pair of input ports and the pair of differential output ports. The load unit is coupled to the pair of differential output ports. The current source is coupled between the second differential pair and a second voltage level.

Abstract: A signal conversion circuit for converting an inputted differential signal into a single-ended signal comprises a differential amplifier circuit for amplifying the differential signal, and generating a first non-inverted signal and a first inverted signal being inverted the first non-inverted signal, a first inverter for generating a second non-inverted signal being inverted the first inverted signal and an interpolation unit for interpolating a phase difference between the first non-inverted signal and the second non-inverted signal.

Abstract: A semiconductor integrated circuit that operates upon supply of a plurality of power potentials including a first power potential and a second power potential higher than the first power potential, includes: an internal circuit that operates upon supply of the first power potential; an inverter that inverts an output signal of the internal circuit upon supply of the first power potential; a level shift circuit, which inputs the output signal of the internal circuit into a first input terminal while inputting the output signal of the inverter into a second input terminal, which generates, upon supply of the second power potential and at each of first and second output terminals, a level shift signal input into the first and second input terminals whose signal level has been shifted, and which outputs the level shift signal from one terminal out of the first and second output terminals; an output circuit that operates upon supply of the second power potential based on the level shift signal output from the leve

Abstract: An output buffer circuit, a differential output buffer circuit, an output buffer circuit having a regulation circuit and a regulation function, and a transmission method, capable of improving resolution of a pre-emphasis amount without increasing power consumption or a circuit area, in which the output buffer circuit 10 has a function which includes a delay circuit 23, an inverter 22 and output buffers 3 to 7 to transmit a logical signal to a transmission line 2 and generate a waveform having four or more types of signal voltages on a transmission side according to a signal attenuation amount of the transmission line 2 and the output buffer 3 has a variable resistance portion 12 at an on-resistance to change a pre-emphasis amount according to a change in a variable resistance value. The output buffer 3 has a selector 20 on a forward stage and a variable resistance portion 12 at an on-resistance.

Abstract: A system and method for controlling input buffer biasing current include an input buffer circuit with an input current detector circuit configured to generate a plurality of discrete biasing control signals. At least one input buffer is configured to adjust the biasing current in response to the plurality of discrete biasing control signals. The plurality of discrete biasing control signals is generated in response to variations in biasing current of the at least one input buffer. The method compares a representative bias current indicator from a replica of an input buffer with a reference current to determine variations in biasing current of at least one input buffer. A plurality of discrete biasing control signals is generated indicating a configuration of a biasing control for the at least one input buffer. The at least one input buffer is biased according to the plurality of discrete biasing control signals.

Abstract: Serial data transmitter circuitry on a PLD includes a number of features that enable the transmitter to support many different communication protocols under a wide range of circuit conditions. Examples of features that the transmitter may include are (1) multiple pre-emphasis circuits of selectable strength and polarity, (2) selectable VOD, (3) selectable slew rate, (4) calibratable termination, (5) selectable common mode voltage, and (6) electrical idle mode.

Abstract: A method, system, and output driver calibration circuit determine calibration values for configuring adjustable impedance output drivers. The calibration circuit includes a pull-up calibration circuit configured to generate an averaged pull-up count signal for calibrating p-channel devices in the output driver with the averaged pull-up count signal being an average of a plurality of pull-up count signals. The calibration circuit further includes a pull-down calibration circuit configured to generate an averaged pull-down count signal for calibrating n-channel devices in the output driver with the averaged pull-down count signal being an average of a plurality of pull-down count signals.

Abstract: The invention provides a semiconductor device having a current input type pixel in which a signal write speed is increased and an effect of variations between adjacent transistors is reduced. When a set operation is performed (write a signal), a source drain voltage of one of two transistors connected in series becomes quite low, thus the set operation is performed to the other transistor. In an output operation, the two transistors operate as a multi-gate transistor, therefore, a current value in the output operation can be small. In other words, a current in the set operation can be large. Therefore, an effect of intersection capacitance and wiring resistance which are parasitic on a wiring and the like do not affect much, thereby the set operation can be performed rapidly. As one transistor is used in the set operation and the output operation, an effect of variations between adjacent transistors is lessened.

Abstract: A novel driver circuit that uses a differential driver as a design backbone is described. Unlike a conventional differential interface, which typically has two or more outputs for providing an output signal and its complement, one of the differential driver's outputs is coupled to drive an output signal onto a signal line, while another one of the differential driver's outputs is unused and terminated, for instance by coupling the output to package ground or a voltage source via a capacitor. The performance of the driver circuit is significantly improved over conventional singled-ended driver designs.

Abstract: A power switch driver includes a top driver switch, a bottom driver switch, a driver node between them, and driver logic. The power switch driver can turn on the power switch by controlling a gate voltage of the power switch to a first voltage level and to turn off the power switch by controlling the gate voltage from a lower second voltage level. The driver logic may include a pulse width generator programmer and a pulse width generator. The pulse width generator is controlled by the pulse width generator programmer and an input signal. Some power switch drivers include a feedback loop, coupled to the driver node and to the driver logic. The feedback loop may include a track-and-hold circuit, coupled to the driver node, to the pulse width generator through an error amplifier and to the input terminal.

Abstract: Various embodiments of the present invention provide systems and methods for glitch reduced circuits. As one example, a glitch reduced, variable width driver circuit is disclosed. Such circuits include a data output, and at least two transistors that each includes a gate, a first leg and a second leg. The gate of the first transistor is electrically coupled to a first combined control signal, and the gate of the second transistor is electrically coupled to a second combined control signal. The first leg of the first transistor and the first leg of the second transistor are electrically coupled to a power source, and the second leg of the first transistor and the second leg of the second transistor are electrically coupled to an output signal. The circuits further include a control circuit that combines a first control signal with the data output to create the first combined control signal, and combines a second control signal with the data output to create the second combined control signal.

Abstract: An inverter circuit (500) having a drive transistor (102) that operably couples to a voltage bias input (101) (and where that drive transistor controls the inverter circuit output by opening and closing a connection between the output (105) and ground (104)) is further operably coupled to a feedback switch (401). In a preferred approach the feedback switch is itself also operably coupled to the voltage bias input and the output and preferably serves, when the drive transistor is switched “off,” to responsively couple the voltage bias input to the drive transistor in such a way as to cause a gate terminal of the drive transistor to have its polarity relative to a source terminal of the drive transistor reversed and hence permit the inverter circuit to operate across a substantially full potential operating range of the drive transistor.

Abstract: A receiver is constructed by a signal reception circuit including a first amplifier section adapted to generate a first current in response to a first input signal and a second amplifier section adapted to generate a second current in response to a second input signal, to thereby generate an amplification signal in accordance with a difference between the first and second currents, and a feedback signal generating circuit adapted to generate a feedback signal in accordance with the amplification signal. Driving abilities of the first and second amplifier sections are determined in accordance with the feedback signal.

Abstract: A differential bidirectional transceiver is provided. The differential bidirectional transceiver includes a first current transmitter, a second current transmitter and a receiver. The first current transmitter and the second current transmitter are coupled to a first interconnection and a second interconnection, respectively. Each of the current transmitters includes two current sources and two switches. The receiver includes an input circuit consisting of four differential pairs, a current summation circuit and a buffer.

Abstract: Provided herein are bi-directional buffers, and methods for providing bi-directional buffering. In an embodiment, a bi-directional buffer includes a differential input/differential output amplifier that includes a first input/output node and a second/input output node. The differential input/differential output amplifier is configurable in a first configuration and a second configuration. When in the first configuration, the second input/output node follows the first input/output node. When in the second configuration, the first input/output node follows the second input/output node.

Abstract: An impedance control circuit includes an impedance detector, an output driver and an impedance controller. The impedance detector generates a first output value to a detection pad connected between an external determination resistor and a pull-up transistor array, and outputs a second output value to a resistance divider terminal commonly connected between a pull-up and pull-down transistor array in response to a pull-up control code data and a pull-down control code data. The output driver has a commonly connected pull-up and pull-down transistor array, and a compensating unit connected to the pull-up and pull-down transistor array of the output driver, to compensate for quantization error of the pull-up and pull-down control code data. The impedance controller performs a comparison and counting operation so that the first and second output values of the impedance detector become approximated to a predetermined reference value, and generates the pull-up and pull-down control code data.

Abstract: A liquid crystal display (“LCD”) includes a first voltage shift circuit at a front stage of an inverter circuit. The first voltage shift circuit includes a second transistor having a source serving as an input, and a gate and drain connected to each other, and is operated as a diode, and a first transistor having a source connected to a power supply, a gate connected to a ground, and a drain connected to the drain of the second transistor. An input signal shifts voltage by a threshold of the second transistor, and then is input into the inverter circuit. Further, a first condenser is inserted between an input node and the gate of the second transistor. Therefore, the LCD has a level shift circuit with a small circuit area and a rapid response speed.

Abstract: The present invention provides a source driver comprising a shift register, a line buffer for storing a data signal and outputting a buffered data signal, and a level shifter for generating a level-shifted data signal based on the buffered data signal. The line buffer further comprises a charge pump supplying a pumped voltage based on a voltage source and a buffer powered by the pumped voltage and outputting a buffered data signal based on the data signal.

Abstract: An analog buffer used in a source driver is provided. The analog buffer havs an input end, an output end, a transistor, first and second capacitors, first, second, third, fourth and fifth switches. The source and the drain of the transistor is coupled to the output end and receives a first voltage respectively. The first end of the first and the second capacitors are coupled to the gate of the transistor. The second end of the first and the second capacitors are coupled to the first end of the first, second and fourth switches and the first end of the third and fifth switches respectively. The second end of the first switch receives a second voltage. The second end of the second and third switches are coupled to the input end. The second end of the fourth and fifth switches are coupled to the output end.

Abstract: Leakage current reduction from a logic block is implemented via power gating transistors that exhibit increased gate oxide thickness as compared to the thin-oxide devices of the power gated logic block. Increased gate oxide further allows increased gate to source voltage differences to exist on the power gating devices, which enhances performance and reduces gate leakage even further. Placement of the power gating transistors in proximity to other increased gate oxide devices minimizes area penalties caused by physical design constraints of the semiconductor die.

Abstract: An output buffer for an IC includes a PMOS transistor having a source coupled to an operating voltage, and an NMOS transistor serially coupled between a drain of the PMOS transistor and a complementary operating voltage. A first driver is coupled to a gate of the PMOS transistor for selectively turning on or off the same. A second driver is coupled to a gate of the NMOS transistor for selectively turning on or off the same. A decoder is coupled to the first and second drivers for controlling the first driver or the second driver to turn on the PMOS transistor or the NMOS transistor at a high rate or a low rate in response to slew rate control signals indicating a slew rate control mode or a non-slew rate control mode.

Abstract: An input/output circuit, operable in an input mode and an output mode, for receiving data and an enable signal, the input/output circuit including an input/output terminal; a pull-up output transistor including a gate; a first logic circuit including an output node coupled to the gate of the pull-up output transistor; a pull-down output transistor including a gate; a second logic circuit coupled to the gate of the pull-down output transistor, and the second logic circuit inactivating the pull-down output transistor in the input mode; and a gate signal generation unit configured to generate a gate signal for inactivating the pull-up output transistor in accordance with the enable signal and an input signal provided from an external device to the input/output terminal in the input mode.

Abstract: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic with inductive broadbanding fabricated in conventional CMOS process technology. Optimum balance between power consumption and speed for each circuit application is achieved by combining high speed C3MOS logic with inductive broadbanding/C3MOS logic with low power conventional CMOS logic. The combined C3MOS logic with inductive broadbanding/C3MOS/CMOS logic allows greater integration of circuits such as high speed transceivers used in fiber optic communication systems.

Abstract: disclosed herein are embodiments of a swing compensation scheme for compensating errors in a transmitter driver.

Abstract: A semiconductor device including an AND-NOR composite gate of which AND unit is supplied with input signals IN and VDD and NOR unit is supplied with an inverted signal EB of an enable signal E, and an AND-NOR composite gate of which AND unit is supplied with an input signal INB and an enable signal E and NOR unit is supplied with VSS. These gates are inserted into a path to which the input signals IN and INB are supplied. Thereby, a symmetric property of a complimentary signal can be retained. Further, outputs of the AND-NOR composite gates are fixed irrespective of a logical level of the enable signal E. Thus, a sub-threshold current also is inhibited.

Abstract: A buffer circuit includes pull up and pull down circuits configured to selectively pull up and pull down, respectively, a voltage of an input/output pad. The pull up and pull down circuits are connected to separate power supply lines such that a current path from the input/output pad to the pull down circuit through the pull up circuit does not exist when electrostatic discharge is received at the input/output pad.

Abstract: Three devices such as electric charge-coupled devices are each included in one of three phase impedance circuits composing a 3-phase LC resonance circuit as a device having a capacitive impedance. A driver circuit applies either of a logic level of 0, a high-impedance level or a logic level of 1 to each of nodes Node_A, Node_B and Node_C of the phase impedance circuits so as to result in sequential transitions of a state of resonance among the phase impedance circuits. In an operation to drive the phase impedance circuits, either of the logic level of 0, the high-impedance level and the logic level of 1 is applied to each of the nodes so as to sustain a phase difference of 2?/3 between the phase impedance circuits. In this way, the logical levels and the phases of the logical levels are assigned to the nodes in such a way that the logical levels do not overlap with each other at any timings each corresponding to a point of time.

Abstract: Dual-function drivers capable of outputting LVDS or TMDS differential signals by sharing output terminals under differential modes. In the dual-function driver, an input control unit receives a first input signal compliant with a first specification in a first mode and a second input signal compliant with a second specification in a second mode by sharing a pair of input terminals, and a current steering circuit comprises first and second differential pairs. The input control unit enables the first and second differential pairs to output a first differential signal compliant with the first specification through a pair of output terminals during the first mode, and the input control unit disables the first differential pair and enables the second differential pair to output a second differential signal compliant with the second specification on the pair of output terminals during the second mode.

Abstract: A high voltage circuit driver includes high and low side driver cells to drive a high and a low side power MOSFET, a bootstrap circuit to energize the high side driver cell, a high voltage PMOS transistor (HVPMOS) between a voltage source and the bootstrap circuit, wherein the HVPMOS is embedded in an N-isolation layer and is integrated with the driver cells. A bootstrap control circuit, for controlling the HVPMOS, includes a high voltage level shift stage, which can also be embedded in an N-isolation layer. The circuit driver is operated by switching the high side drive signal from high to low, the low side drive signal from low to high with a first delay, and a bootstrap control signal from high to low with an additional second delay. Also, the bootstrap capacitor is first charged by switching on the HVPMOS, and then it energizes the high side driver cell.

Abstract: A buffer for a programmable logic device has programmable current sink and source circuitry and an independently programmable common-mode voltage reference source. An amplifier, responsive to a common-mode voltage detector and the voltage reference source, forces a common-mode voltage of an output signal from the buffer to approximate the voltage from the common-mode voltage reference source.

Abstract: A mixed-voltage input/output buffer having low-voltage design comprises a pre-driver, a tracking unit, a driving unit, and input/output pad, a floating-well unit and a transporting unit. The pre-driver receives first data signal and enable signal and outputs first and second data voltages. The tracking unit provides Gate-Tracking function. The driving unit couples the pre-driver and the tracking unit for production of a first buffer voltage corresponding to the first data voltage. The input/output pad couples the driving unit to output a first buffer voltage and to receive a second data signal. The output unit is used for outputting a second buffer voltage corresponding to the second data signal. The floating-well unit couples to the driving unit and the input/output pad in order to output first buffer voltage and receive second data signal. The floating-well unit is used for preventing leakage current.

Abstract: Methods, devices, and systems are disclosed, including those for a buffer having pre-driver circuitry configured to provide voltages to thin-gate dielectric transistors One such buffer may comprise a primary pull-up pre-driver operably coupled to a primary pull-up transistor, a secondary pull-up pre-driver operably coupled to a secondary pull-up transistor, a primary pull-down pre-driver operably coupled to a primary pull-down transistor, and a secondary pull-down pre-driver operably coupled to a secondary pull-down transistor. Each of the primary pull-up pre-driver, the secondary pull-up pre-driver., primary pull-down pre-driver, and the secondary pull-down pre-driver are configured to provide a voltage to a gate of a transistor operably coupled thereto at a voltage level so as to sustain gate dielectric integrity of the transistor.

Abstract: A multi-threshold CMOS system and method controls a state of respective blocks individually. Each block includes a logic circuit having a logic transistor and a control transistor connected between the logic circuit and a power line connected to one of a ground and a power source. The control transistor has a higher threshold than the logic transistor. The blocks are controlled by generating an individual block ON/OFF signal for each block, generating an individual control signal in response to the individual block ON/OFF signal, supplying the individual control signal to the control transistor and controlling voltage supply to the logic circuit within each block in accordance with the individual control signal.

Abstract: A swing limiter comprises a logic circuit including a first pull-up transistor and a first pull-down transistor connected between first and second nodes and which generate an output signal; a second pull-up transistor connected between a first power voltage and the first node; a second pull-down transistor connected between the second node and a second power voltage; a first control voltage generator connected between a high voltage which is higher than the first power voltage and a first reference voltage which is lower than the high voltage; and a second control voltage generator connected between a low voltage which is lower than the second power voltage and a second reference voltage which is higher than the low voltage.

Abstract: Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment.

Abstract: Transistors having large gate tunnel barriers are used as transistors to be on in a standby state, MIS transistors having thin gate insulating films are used as transistors to be off in the standby state, and main and sub-power supply lines and main and sub-ground lines forming a hierarchical power supply structure are isolated from each other in the standby state so that a gate tunnel current is reduced in the standby state in which a low power consumption is required. In general, a gate tunnel current reducing mechanism is provided for any circuitry operating in a standby state and an active state, and is activated in the standby state to reduce the gate tunnel current in the circuitry in the standby state, to reduce power consumption in the standby state.

Abstract: A Universal Serial Bus (USB) 2.0 transceiver includes a legacy full speed and low speed (FS/LS) USB driver that includes multiple output stages. The multiple output stages are connected in parallel to an output terminal. By sequentially providing the USB data to the multiple output stages, the USB signal at the output terminal will transition between logic states in an incremental fashion as the multiple output stages sequentially switch their individual output states. Consequently, the rise/fall time for the legacy FS/LS USB driver is controlled not by the strength of the inverter transistors in the output stages, but rather by the number of stages and the time interval between application of the USB data to each stage. Therefore, by selecting an appropriate number of output stages and an appropriate timing interval, accurate control over full speed and low speed USB signal rise/fall times can be provided.

Abstract: Systems and methods are disclosed for operating a core circuitry of an integrated circuit at a lower voltage than the coupled IO circuitry using a tolerant circuit. In one embodiment includes a voltage tolerant circuit comprising a voltage detect module adapted to detect when a voltage is sufficient to switch bias conditions without violating maximum transistor operating conditions and a comparator adapted to detect when a PAD voltage is greater than an IO power supply voltage.

Abstract: The slew rate of signals output from an integrated circuit is selectively controlled to optimize the quality of the output data signal depending upon whether the communication channels require a faster or slower slew rate. Faster slew rates may be utilized when the communication channels are prone to attenuation, while slower slew rates may be implemented in the communication channels when crosstalk is more of a concern.

Abstract: A USB transmitter 3.3V output stage includes a PMOS cascode transistor connected between a PMOS pullup transistor and a USB port data pin, an NMOS cascode transistor connected between an NMOS pulldown transistor and the data pin, and an output driver circuit that generates a pullup signal range of 0.8V to 3.3V, and a pulldown signal range of 0V to 2.5V, whereby the pullup and pulldown transistors are subjected to 2.5V gate-to-source potentials. A protection/bias circuit biases the PMOS cascode transistor during normal operation such that the pullup resistance matches the pulldown resistance, and turns off the PMOS cascode transistor to shut off the pullup path during a 5V short condition. N-wells of the PMOS pullup and cascode transistors are connected to the 3.3V supply via a resistor.

Abstract: Various systems and methods for implementing dynamic logic are disclosed herein. For example, some embodiments of the present invention provide dynamic logic devices with a logic circuit that includes an inverting output buffer, a logic function, a bias transistor, and a current circuit. An input of the logic function is electrically coupled to a logic input, an output of the logic function is electrically coupled to an input of the inverting output buffer, and the logic function exhibits a leakage current. The gate of the bias transistor is electrically coupled to an output of the inverting buffer, and a first leg of the bias transistor is electrically coupled to the input of the inverting buffer. The current circuit supplies a current corresponding to the to a second leg of the bias transistor. In some cases, an improved performance may be achieved for a given leakage, or a reduced leakage may be achieved for a given performance.

Abstract: A current supply circuit is disclosed, which comprises a first circuit configured to generate a first current having a positive dependence with respect to a power supply voltage and not depending upon a variation in temperature and in threshold value of a transistor used, a second circuit configured to generate a second current having a positive dependence greater than that of the first current with respect to the power supply voltage and not depending upon a variation in temperature and in threshold value of a transistor used, and a third circuit configured to subtract the second current form the first current to generate a third current having a negative dependence with respect to the power supply voltage.

Abstract: A semiconductor device which includes a frequency-variable oscillation circuit including plural inverters, each of which features a PMOS transistor and a NMOS transistor, a first substrate bias generator including a first phase/frequency compare circuit that compares an output signal from the frequency-variable oscillation circuit with a reference clock signal and generating a first substrate bias voltage in response thereto, the first substrate bias voltage being supplied to substrates of the PMOS transistors in the oscillation circuit, and a second substrate bias generator including a second phase/frequency compare circuit that compares the output signal from the frequency-variable oscillation circuit with the reference clock and generating a second substrate bias voltage in response thereto, the second substrate bias voltage being supplied to substrates of the NMOS transistors in the oscillation circuit.

Abstract: Recently, the use of class D audio amplifiers has become more and more widespread. In contrast to the generally employed class AB linear amplification technology, class D allows for improved efficiency. However, the class D principle is known for its poor distortion characteristics. According to the present invention, switching delays of the end stage (6) are measured and used for compensating distortions caused by the dead time of the end stage (6). This is done by modifying the switching delay of the power stage. In this way, the output pulse duration is corrected to reflect the input duty cycle. Advantageously, variations in the switching-time due to device property spread, aging, current and temperature may be compensated.

Abstract: An H-tree driver circuit has pull-up and pull-down current sources, each of which is implemented using a low-voltage-cascode topology.

Abstract: When the operation frequency is high, in order to cause the rate of change of outputs from an output terminal (OUT) to be abrupt, a selection control signal is caused to be in a low state, thereby causing MOS transistors (T5b, T6b) to be in ON states, thereby causing the combined resistance of the ON-resistances of the MOS resistors in a NOR gate (NOx) to be small. On the other hand, when the operation frequency is low, in order to cause the rate of change of outputs from the output terminal (OUT) to be gentle, the selection control signal is caused to be in a high state, thereby causing the MOS transistors (T5b, T6b) to be in OFF states, thereby causing the combined resistance of the ON-resistances of the MOS transistors in the NOR gate (NOx) to be large.