Abstract: A differential signal driver includes a pre-driver configured to generate a constant charging current and a constant discharging current. A first capacitor of the pre-driver is charged with the charging current when a differential input signal has a first state, and discharged with the discharging current when the differential input signal has a second state, thereby developing a first output control voltage on the first capacitor. A second capacitor of the pre-driver is discharged with the discharging charging current when the differential input signal has the first state, and charged with the charging current when the differential input signal has the second state, thereby developing a second output control voltage on the second capacitor. An output driver circuit generates a differential output signal in response to the first and second output control voltages. The slew rate of the differential output signal is controlled by the charging and discharging currents.

Abstract: A method and circuit arrangement including driving a field effect controlled transistor. One embodiment provides a first load terminal, a second load terminal and a control terminal. The control terminal is driven, at least during a Miller plateau phase of the transistor, with a pulse-width-modulated control signal whose period duration is shorter than the duration of the Miller plateau phase.

Abstract: An output buffer circuit includes a high voltage detecting circuit, a dynamic gate bias generating circuit, an output stage circuit and a pad voltage detector. The high voltage detecting circuit detects a power supply voltage and generates a first and a second determining signals and a first and a second bias voltages according to the power supply voltage. The dynamic gate bias generating circuit is biased by the first and the second bias voltages and receives the first and the second determining signals, for converting logic control signals into corresponding gate bias voltages according to the first and the second determining signals. The pad voltage detector detects a voltage of an I/O pad and provides a pad voltage detecting signal for the output stage circuit to modify an output signal outputted to an I/O pad. A mixed-voltage input/output (I/O) buffer is disclosed herein.

Abstract: A semiconductor device according to the present invention comprises a first semiconductor integrated circuit 11 having a predetermined function, the first semiconductor integrated circuit outputting a required output signal, a second semiconductor integrated circuit 12 in which a plurality of MOS elements (PMOS transistor or NMOS transistor) for independently switching to and from a conducted state and a non-conducted state in accordance with a plurality of gate signals each having a different timing is provided and the plurality of MOS elements is connected in parallel to an output or an input of the first semiconductor integrated circuit, and a pulse generating circuit 13 for generating and outputting the plurality of gate signals ?i (i=1, 2, 3) each having a different timing with respect to the plurality of MOS elements in the second semiconductor integrated circuit.

Abstract: A level shifter increase a voltage level of an output signal with relatively lower power consumption by adopting current-starved configuration. The level shifter includes an input unit and a driving unit. The input unit includes a current-starved inverter configured to generate a control signal in response to an input signal and a bias voltage. The input unit is powered by a first power supply voltage. The driving unit generates an output signal in response to the control signal. The output signal has a voltage level higher than the input signal, and the driving unit is powered by a second power supply voltage higher than the first power supply voltage.

Abstract: A current source and a method for designing the current source are provided. The current source is designed by a recursive rule and enables controllable delay lines to provide linear delay and occupy smaller area than conventional controllable delay lines with thermometer code current sources do.

Abstract: A source driver includes a receiver for receiving a digital signal at an input node to generate an output signal at an output node, where the receiver includes a first switch, a second switch, a voltage-limiting circuit, a third switch and a channel. The first switch is for selectively connecting the output node of the receiver to a first reference voltage based on the digital signal. The second switch is for selectively connecting the output node of the receiver to a second reference voltage based on the digital signal. The voltage-limiting circuit is coupled between the input node and the output node of the receiver, and is for limiting a voltage level of the input node of the receiver. The third switch is coupled between the voltage-limiting circuit and the output node of the receiver. The channel is for generating a driving voltage based on the output signal.

Abstract: A low power output driver includes one of a regulated reduced voltage source that receives a supply voltage and outputs a regulated reduced voltage that is a lower voltage than the supply voltage. The driver also includes a first driver input that receives a first logic signal, a second driver input that receives a second logic signal, a first driver output that outputs a first output signal and a second driver output that outputs a second output signal. The driver includes first, second, third and fourth n-type metal oxide semiconductor (NMOS) that are cross-connected between the reduced voltage and the first and second driver outputs or a constant voltage internal ground. When the second input is high, the second NMOS and the third NMOS are gated on, the second driver output is raised to the reduced voltage and the first driver output is pulled down to the constant voltage ground.

Abstract: A pre-emphasis circuit which can improve a communication quality of a data transmission at low cost is provided. A current switch circuit, a current adder circuit, and transition detection circuits are provided in a transmitter of a data transmission system. The transition detection circuits detect transitions of transmission data signals which are a differential pair. The current switch circuit receives the transmission data signals, carries driving currents in accordance with the transmission data signals, and outputs output data signals which are a differential pair. The current adder circuit receives detection signals from the transition detection circuits, and adds driving currents in accordance with the detection signals to load resistors. By this means, output data signals in which the transitions are emphasized are inputted to a transmission line.

Abstract: First and second devices may simultaneously communicate bidirectionally with each other using only a single pair of LVDS signal paths. Each device includes an input circuit and a differential output driver connected to the single pair of LVDS signal paths. An input to the input circuit is also connected to the input of the driver. The input circuit may also receive an offset voltage. In response to its inputs, the input circuit in each device can use comparators, gates and a multiplexer to determine the logic state being transmitted over the pair of LVDS signal paths from the other device. This advantageously reduces the number of required interconnects between the first and second devices by one half.

Abstract: A differential output circuit including a first output driving circuit that includes a first PMOS transistor and a first NMOS transistor connected in series to each other, a second output driving circuit that includes a second PMOS transistor and a second NMOS transistor connected in series to each other and a control circuit, wherein, when a control signal has a first value, the control circuit selectively turns on one of the first and second PMOS transistors and selectively turns on one of the first and second NMOS transistors, thereby controlling the first and second output driving circuits to output a first pair of differential signals, and when the control signal has a second value, the control circuit supplies no current to the PMOS transistors and selectively turns on one of the NMOS transistors, thereby controlling the output driving circuits to output a second pair of differential signals.

Abstract: An apparatus for supplying current to a semiconductor memory device. A current supply circuit supplies current to an input/output (I/O) drive circuit responsive to a pattern of data input to the I/O drive circuit. The current supply circuit configured to supply current generated by an external voltage to the I/O drive circuit responsive to a first pattern of data input to the I/O drive circuit, and to prevent the current generated by the external voltage from being supplied to the I/O drive circuit responsive to a second pattern of data input to the I/O drive circuit.

Abstract: A semiconductor chip comprising a reference circuit and a target circuit. The reference circuit comprises a first P-channel field effect transistor (PFET) and a first N-channel field effect transistor (NFET). A reference voltage is connected to gates of the first PFET and first NFET. A body control voltage node is formed by connecting a drain of the first PFET, a body of the first PFET, a drain of the first NFET and a body of the first NFET. A target circuit comprises a second PFET and a second NFET. The body control voltage node is connected to a body of the second PFET and the second NFET. The body control voltage improves duty cycle in the target circuit compared to a similarly designed circuit having PFET bodies connected to Vdd and NFET bodies connected to Ground.

Abstract: A transmission circuit and related method are disclosed. A transmitter in the transmission circuit has CMOS transistors as driving units for responding an input signal to drive an output signal at an output node, and each driving unit has a corresponding charge unit formed by a capacitor-connected MOS of a same type as that of the corresponding driving unit. Each charge unit is controlled by an auxiliary signal inverse to the input signal. When a level transition occurs in the input signal, the charge unit can compensate charge injection and clock feed-through caused by the driving unit at the output node, and form peaks for pre-emphasis. In this way, a better transmission property can be realized by using a simpler and low-power circuit design.

Abstract: Two or more buffers may configured and arranged such that a quiescent current that flows through and biases a first buffer also flows through and biases a second buffer. The first and second buffers may, for example, be source followers used as reference buffers that drive inputs of a switched-capacitor circuit.

Abstract: A differential voltage mode driver and digital impedance calibration of same is provided. In one embodiment, the invention relates to a method of calibrating a differential driver circuit having a plurality of parallel driver stages, the differential driver circuit for driving a differential signal over a transmission line having an impedance, the method including determining an indication of an impedance of a plurality of parallel replica stages, wherein the plurality of parallel replica stages are replicas of the plurality of parallel driver stages, determining a number of the plurality of parallel replica stages to approximately match the measured impedance with the transmission line impedance, and activating a number of the plurality of parallel driver stages equal to the number of the plurality of parallel replica stages. In another embodiment, the invention relates to a differential voltage mode driver using at least one H-bridge driver stage.

Abstract: A high voltage input receiver using low voltage transistors is disclosed. In one embodiment, an input receiver circuit includes a comparator circuit and an inverter circuit. The comparator circuit includes a differential input module for generating a control signal by comparing an external voltage and a reference voltage, and a decision module for generating an inverter input signal based on the control signal. In addition, the reference voltage is used to set dc trip point of the input receiver. Moreover, the input receiver includes one or more stress protection modules to protect key components of the input receiver from exceeding their reliability limits.

Abstract: A voltage buffer with current reuse is described. This voltage buffer can advantageously provide a relatively wide voltage differential using a relatively low current. In one embodiment, a slave branch can be used to minimize potential spikes/glitches in the voltage buffer.

Abstract: An output buffer providing a data signal to a data line and including an input stage circuit, an output stage circuit, and a control circuit is disclosed. The input stage circuit receives an input signal. The output stage circuit generates the data signal according to the input signal and includes a first P-type transistor. The control circuit selectively provides a first voltage or a second voltage to a bulk of the first P-type transistor.

Abstract: An input output device coupled between a core circuit and a pad and including an output cell, an input cell, and a pre-driver. The output cell includes an output stage and a voltage level converter. The output stage includes a first transistor and a second transistor connected to the first transistor in serial between a first supply voltage and a second voltage. The voltage level converter generates a first gate voltage to the first transistor according to the first voltage and a data signal. When the first supply voltage is increased, the first gate voltage is increased. When the data signal is at a high level, the first transistor is turned on. The input cell includes a pull unit and a first N-type transistor. The pre-driver turns off the first and the second transistors.

Abstract: A method and apparatus is provided for a configurable input/output (I/O) interface within an integrated circuit to support a plurality of I/O standards. The configurable I/O interface exhibits a default operation that facilitates hot-swappability, which eliminates current paths within the I/O interface that may be created during plug-and-play operation of the I/O interface. The current paths are eliminated within the I/O interface even while the I/O interface is not receiving operational power, or while the I/O interface is in a power-on reset condition. A programmable option of the configurable I/O interface, on the other hand, alleviates over-voltage conditions while the I/O interface is tri-stated by activating shunt circuitry to conduct a clamp current during the over-voltage condition. The over-voltage condition is further alleviated by passively establishing current paths through existing circuitry within the I/O interface for the duration of the over-voltage condition.

Abstract: A differential CML driver includes an output stage, a control circuit and a reference circuit. The output stage includes a first loading component, a second loading component, a bias component, a first metal-oxide-semiconductor (MOS) transistor and a second MOS transistor. The control circuit is coupled to the output stage and is for receiving a reference bias voltage, a first input signal and a second input signal to make one of the first and the second MOS transistor enter a cut-off region and the other of the first and the second MOS transistor enter a saturation region. The reference circuit is coupled to the output stage and the control circuit, and is for generating a common-mode voltage according to first and second output voltages of the output stage, and outputting the reference bias voltage to the control circuit according to the common-mode voltage.

Abstract: Embodiments of the invention relate to a chip-to-chip communication system including a transmitter and a receiver connected to receive respective transmitter and receiver clock signals. The transmitter includes precharge and evaluation blocks connected to each other and to a transmitter clock terminal. The receiver includes a precharge block connected to a receiver clock terminal. The precharge blocks precharge an output terminal of the transmitter and an input terminal of the receiver, respectively, to a value corresponding to a first voltage reference during a low phase of the transmitter clock signal.

Abstract: This invention is an input bias control for a module input. A clock detect circuit generates a signal indicating whether an external clock signal is detected. An operational state detect circuit receives this signal and is responsive to an operational state of the module. The operational state detect circuit enables one of a pull-up and pull-down transistor corresponding said operational state of the module. The operational state detect circuit may the input buffer a predetermined time following external clock signal detection, which might be a following transition in the external clock signal. The operational state detect circuit enables the pull-up or pull-down transistor a predetermined time following enabling said input buffer.

Abstract: The present invention enables fast transition between sleep and normal modes for circuits such as digital circuits. This invention utilizes chip internal charge transfer operations to put the circuit into fast sleep. The invention reduces external power involvement, and it expedites the sleep mode transition time by limiting charge transfers within the circuit. The fast sleep and fast wake-up enable more efficient power management of the system. This functionality also maximizes performance per power, and provides a more energy efficient computing architecture.

Abstract: Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or analog circuit with such four terminal JFETs operating in a linear or nonlinear mode.

Abstract: A single-channel thin-film transistor buffer includes a first output stage including first and second thin-film transistors connected in series, a seventh thin-film transistor having one main electrode connected to a control electrode of the first thin-film transistor (first control line), the other main electrode connected to a power source of the second thin-film transistor, and a control electrode connected to a second control line, an eighth thin-film transistor having one main electrode connected to a control electrode of the second thin-film transistor (second control line), the other main electrode connected to the power source of the second thin-film transistor, and a control electrode connected to the first control line, and an eleventh thin-film transistor having a control electrode connected to an output terminal of a second output stage connected in parallel with the first output stage and one main electrode connected to the first control line.

Abstract: A semiconductor integrated circuit includes an ODT signal generator that receives an ODT command signal, an ODT reset signal, and an ODT calibration end signal to generate an ODT control signal according to the phase of the ODT calibration end signal, and an ODT resistance adjusting unit that is to perform an on-die termination operation in response to the ODT control signal.

Abstract: A differential-signal output circuit for a timing controller of a display device includes a conversion circuit, a pre-charging circuit and a timing generator. The conversion circuit is used for receiving a differential signal and outputting a current to a load circuit according to polarity of the differential signal. The pre-charging circuit is coupled to a first output end and a second output end of the conversion circuit or is coupled to a first power driving end and a power second driving end of the conversion circuit. The pre-charging circuit is used for pre-charging the load according to a control signal. The timing generator is used for generating the differential signal and a control signal according to display data.

Abstract: A receiver for receiving a reduced swing signal from a transmission channel is disclosed, in which the swing of the reduced swing signal is less than the power supply of the receiver and possibly is less than the power supply of the transmitter. The receiver comprises a level shifter for offsetting the reduced swing signal, and an amplifier which receives both the reduced swing signal and its offset to produce a full swing signal output referenced to the power supply of the receiver. The full swing signal can thereafter be buffered, and eventually can be captured by a clock. Optionally, the disclosed reduced swing receiver also contains calibration circuitry for improving the integrity of the full swing signal output, and in particular for countering the effects of process, and in some embodiments temperature, variations, which alter the characteristics of the transistors which make up the receiver circuitry.

Abstract: A buffer circuit includes at least one part that is powered by a supply voltage by means of a first initialization transistor, and connected to the ground by means of a second initialization transistor. The circuit is capable of transferring, between an input and an output, an input signal including at least one rising edge and/or one falling edge. The circuit includes a first CMOS inverter, of which the input is connected to the input of the circuit, and of which the output is mounted in series with the input of a second CMOS inverter, with the output of the second CMOS inverter being connected to the output of the circuit. A circuit creates an overvoltage on one of the two inverters during operation.

Abstract: A level shifter includes a first level-switching device and a second level-switching device. The first level-switching device includes a first switch device, a second switch device, a first control switch and a third switch device. The first switch device is for receiving the input voltage and outputting a first voltage. The second switch device is coupled to the first switch device for outputting a first operational voltage as the output voltage according to the first voltage. The first control switch is coupled to the first switch device for receiving the first voltage. The third switch device is coupled between the first control switch and the first operational voltage and controlled by the output voltage. The second level-switching device is coupled to the first level-switching device for receiving the input voltage and accordingly outputting a second operational voltage as the output voltage.

Abstract: An output of a driving circuit is controlled by selectively outputting a first voltage or a second voltage as an N-th output voltage level in response to a first control signal and an N-th input voltage level, where N is a natural number, and pre-charging the selected N-th output voltage level to a third voltage or a fourth voltage, in response to a second control signal, the pre-charging being preformed based on the selected N-th output voltage level and a newly input (N+1)th input voltage level.

Abstract: In an output buffer circuit including Inverter 1 to Inverter 3, Delay Circuit 1 to Delay Circuit 3 for delaying an input signal for a specific time, Buffer 1 to Buffer 3, and a function for transmitting a logic signal to a transmission path and in accordance with an amount of signal attenuation in the transmission path, creating at a transmission side a waveform including four or more kinds of signal voltages, the preemphasis amount is made variable and the ON resistance Rs of the buffer is made constant. Selector circuit 1 to Selector circuit 3 are situated before the buffers, the inverter, capable of selecting through selector logic a signal to be inputted to the buffer, inverts a data signal, and the preemphasis amount and the number of preemphasis taps are adjusted through a selection signal for the selector logic.

Abstract: A driver circuit includes a first transistor having a first node coupled to a high supply voltage and a second node coupled to an output node, wherein the first transistor passes the high supply voltage to the output node based on a first gate voltage on a gate of the first transistor. The driver circuit also includes a second transistor having a first node coupled to a low supply voltage and a second node coupled to the output node of the driver circuit, wherein the second transistor passes the low voltage to the output node based on a second gate voltage on a gate of the second transistor. The driver circuit further includes a logic block configured to control a slew rate of an output signal Vout at the output node by controlling a slew rate of the first gate voltage and controlling a slew rate of the second gate voltage.

Abstract: A level shifter includes a voltage distributor for receiving an input signal and respectively outputting a first signal and a second signal at a first node and a second node according to the input signal; and an output circuit coupled to the voltage distributor for generating an output signal according to the first signal and the second signal, wherein the voltage distributor includes: a first transistor having a first electrode, a second electrode coupled to the first node, and a first control electrode for receiving the input signal; a switch coupled between the first node and the second node for selectively establishing an electrical connection between the first and the second nodes; and a second transistor having a third electrode coupled to the second node, a fourth electrode, and a second control electrode coupled to the first node.

Abstract: An IO buffer module optimized for a wide range of drive levels both in terms of area and performance that includes an IO cell module and at least one IO adder module operatively coupled to said IO cell module for enabling the IO buffer module for the wide range of drive levels. The IO adder module can be added with the cell module in a number of different combinations for providing the wide range of drive levels, and the IO buffer module can provide drive solutions from 1 mA to 10 mA or higher, in steps of 0.5 mA drive level.

Abstract: A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.

Abstract: A semiconductor device according to the present invention comprises a first semiconductor integrated circuit 11 having a predetermined function, the first semiconductor integrated circuit outputting a required output signal, a second semiconductor integrated circuit 12 in which a plurality of MOS elements (PMOS transistor or NMOS transistor) for independently switching to and from a conducted state and a non-conducted state in accordance with a plurality of gate signals each having a different timing is provided and the plurality of MOS elements is connected in parallel to an output or an input of the first semiconductor integrated circuit, and a pulse generating circuit 13 for generating and outputting the plurality of gate signals ?i (i=1, 2, 3) each having a different timing with respect to the plurality of MOS elements in the second semiconductor integrated circuit.

Abstract: Provided herein are bi-directional buffers, and methods for providing bi-directional buffering. In an embodiment, a bi-directional buffer includes a differential input/differential output amplifier that includes a first input/output node and a second/input output node. The differential input/differential output amplifier is configurable in a first configuration and a second configuration. When in the first configuration, the second input/output node follows the first input/output node. When in the second configuration, the first input/output node follows the second input/output node.

Abstract: Signal offset variation caused by transistor variation/mismatch in integrated circuits may be reduced. In one embodiment, a buffer circuit has variable-valued circuit elements. Offset variation measurements are made and the variable-valued circuit elements are calibrated to reduce the measured offset variation. In another embodiment, each amplifying stage of a multi-stage buffer provides variable gain. The total DC gain of the cascade is distributed unevenly across the stages, with more DC gain being provided by amplifier stages at the beginning of the cascade than at the end. An additional pre-amplifier stage can also be provided at the beginning of the cascade.

Abstract: An input buffer for an Ultradeep Sub Micron (UDSM) process which allows the UDSM process to interface with a 3V input. The input voltage is applied to a degenerated transistor which forms part of the input buffer. The input buffer effectively drops the input voltage to a voltage suitable for use by the core of the UDSM process.

Abstract: The invention relates to a method and a corresponding circuit for protecting a power MOSFET from thermal overload when switching the MOSFET off and on, wherein the MOSFET is switched on again after at least a determined off-period has passed.

Abstract: A driver circuit and method for generating two complementary output currents from a two-state logic input signal at two outputs for connecting a two-wire conductor provide the following actions: generating from the input signal, an output signal at each output, the amperage of one of the output currents being adjustable by a control signal; analyzing each voltage materializing at the outputs; generating an error signal as a function of the output voltages within each of at least two time slots subsequent to a change in state of the input signal; caching the error signals or signals derived therefrom and adjusting, as a function of cached error signals or of the cached signals as a function thereof, the output current in corresponding time slots subsequent to a resulting change in state of the input signal.

Abstract: The integrated circuit device (1) backs up the configuration of output terminals (O, SP) of said integrated circuit in low-power mode. To do this, the device includes several voltage level shift units (2, 2?, 2?, 2??) and an output stage (3) connected to each output of the level shift units and connected to at least one external contact pad (SP) of said integrated circuit. Each level shift unit includes an input stage powered by a regulated internal voltage (VREG) and a part for transferring the state of a specific output function, which is powered by a supply voltage (VDD) of the integrated circuit. Each level shift unit also includes a memory cell at output powered by the supply voltage, for storing the output state of a specific function of the level shift unit in the idle mode of the integrated circuit where the regulated voltage is cut off.

Abstract: A signal interface circuit has a signal path for communicatively coupling host circuitry to peripheral circuitry of multiple peripherals. Communication signals in the signal path are of a peripheral signal level. The signal path has electronic components adapted for use in communicating signals between the host circuitry and the peripheral circuitry. The electronic components in the signal path have reliability limits less than the peripheral signal level. The configuration of the electronic components in the signal path allow communication of signals at the peripheral signal level.

Abstract: An output buffer circuit, a differential output buffer circuit, an output buffer circuit having a regulation circuit and a regulation function, and a transmission method, to improve resolution of a pre-emphasis amount without increasing power consumption or a circuit area. The output buffer includes a delay circuit, an inverter and output buffers to transmit a logical signal to a transmission line and generate a waveform having four or more types of signal voltages on a transmission side according to a signal attenuation amount of the transmission line. The output buffer has a selector and a variable resistance portion at an output resistance to change a pre-emphasis amount according to a change in a variable resistance value. The inverter is configured to select a signal to input into the output buffer, invert a data signal and adjust a tap pre-emphasis amount by a select signal of the selector logic.

Abstract: An output buffer circuit includes a control unit and an output driver. The control unit generates a control signal in response to a mode signal applied from an internal circuit. The output driver selectively performs a driver operation, a termination operation or an electrostatic discharge (ESD) protection operation in response to the control signal.

Abstract: The present invention discloses an impedance matching circuit for facilitating impedance matching between the characteristic impedance of a cable and the input impedance at the input terminal of a receiver for data transmission comprising: a first transistor, a second transistor, a resistor, a negative feedback control circuit, a multiplexer and a reference voltage generator. When the characteristic impedance of the cable varies, the equivalent resistance of the impedance matching circuit can be kept equal to the resistance of the varied characteristic impedance of the cable by adjusting the reference voltage.

Abstract: The present invention discloses an output circuit that is able to adjust the output voltage slew rate and avoid short-circuit current, comprising: a control circuit for receiving an input data and generating a first set of control signals based on the input data; an output control device consisting of a first field effect transistor (FET) connected in series with a second field effect transistor (FET) and the point of connection is the output end for generating an output signal; a first capacitor having one end connected to a first working voltage and generates a first control voltage by charging/discharging on another end to control the gate of the first field effect transistor; a first switch for controlling charging/discharging of the first capacitor device based on the first set of control signals; a first current source for providing charging current for the first capacitor device; a second capacitor having one end connected to a second working voltage and generates a second control voltage by charging/d