Abstract: An output buffer circuit for improving an output during state transitions of CMOS buffers driving transmission line loads. The circuit generates variable output impedance proportional to the load transmission line impedance. The buffer includes an output stage, such as pull up/pull down drivers for receiving an input signal and generating an output signal. The pull up/pull down drivers are biased by a circuit that generates a control signal and varies its conductivity according to the control signal. The pull up/pull down drivers initially provide a relatively low impedance to reach a desired level during the initial transition period of the output and then slowly varies its impedance in response to the control signal to suppress the ringing effect. The control circuit coupled to the input node, output node and the power supply node to generate a control signal that biases the pull up/pull down driver.

Abstract: A voltage buffer with current reuse is described. This voltage buffer can advantageously provide a relatively wide voltage differential using a relatively low current. In one embodiment, a slave branch can be used to minimize potential spikes/glitches in the voltage buffer.

Abstract: A semiconductor device of the invention has a plurality of P-channel transistors, to which resistance elements are inserted in series, prepared on a pull-up side of a driver such that an ON resistance value on the P-channel transistor side and a resistance value of the resistance element can be selected. In addition, also on a pull-down side of the driver, a plurality of N-channel transistors to which resistance elements are inserted in series are prepared such that an ON resistance value on the N-channel transistor side and a resistance value of the resistance element can be selected. A driver section having a linear current-voltage characteristic is realized by combination of those described.

Abstract: A buffer circuit includes first and second transistors which are connected in series between first and second power supplies and which are controlled to be on/off based on values of signals at their control terminals are provided, in which a connection point between the two transistors is connected to an output terminal (OUT) and a control terminal of the first transistor is connected to an input terminal (IN), and a control circuit for performing on/off control over the second transistor based on an input signal from the input terminal (IN).

Abstract: A buffering circuit includes: a first transistor having a gate terminal coupled to an input signal for buffering the input signal to generate an output signal under an operating current, a second transistor cascoded with the first transistor for generating the operating current for the first transistor according to a control signal at a gate terminal of the second transistor, and a control circuit having a first terminal coupled to the gate terminal of the first transistor and a second terminal coupled to a reference source. The control circuit adjusts the control signal according to the input signal and the reference source, wherein when a voltage level of the input signal varies, the control circuit is arranged to adjust a voltage level of the control signal such that the adjusted voltage level of the control signal varies inversely proportional to the varied voltage level of the input signal.

Abstract: In a case where potential of the first input terminal is lower than that of the second input terminal by an amount of the offset voltage, in a normal operation mode, the control circuit controls the polarity switching circuit so as to input the first contact voltage of the first contact to the first input terminal and input the control voltage to the second input terminal. On the other hand, in a case where the potential of the first input terminal is higher than that of the second input terminal by an amount of the offset voltage, in the normal operation mode, the control circuit controls the polarity switching circuit so as to input the first contact voltage at the first contact to the second input terminal, input the control voltage to the first input terminal, and invert the polarity of the amplified signal.

Abstract: Reducing electromagnetic radiation from semiconductor devices. At least some of the illustrative embodiments are methods comprising driving a Boolean state to a signal pad of a semiconductor device (the driving through a transistor with a first drain-to-source impedance during the driving), and maintaining the Boolean state applied to the signal pad through the transistor with a second drain-to-source impedance, higher than the first drain-to-source impedance.

Abstract: An inverter circuit for generating an output signal at an output node obtained by inverting an input signal level at an input node includes a common-source MOS transistor having a gate node connected to the input node, a source connected to a predetermined voltage and a substrate gate, a load resistor connected in series with the MOS transistor, and a resistor connected between the gate node and the substrate gate of the MOS transistor.

Abstract: A reduced power differential type termination circuit for use in SSTL, HSTL and other transmission line systems reduces power consumption. A differential type termination circuit may comprise first and second nodes for coupling, respectively, to first and second transmission lines; a first impedance coupled between the first transmission line and a third node; a second impedance coupled between the second transmission line and the third node; and a low direct current reference voltage generator for generating a reference voltage applied to the third node. The first and second transmission lines may transmit complimentary signals. The first and second impedances may be symmetric or asymmetric. The first impedance may match the second impedance. The first and second impedances may, respectively, match the impedances of the first and second transmission lines. The first and/or second impedances may include a bidirectional switch, such as a transmission gate, to enable and disable the termination circuit.

Abstract: The present invention discloses a high voltage switching module having reduced stress at its driver output stage which in turn controls the gate of a transistor requiring a high current drive. The switching module includes a negative elevating circuit, a delay module, a pull-up circuit, and a pull down circuit. The negative elevating circuit senses a transition of a logic input signal to generate a control signal. The first pull-up circuit is operatively coupled to this control signal for switching the driver output from a negative voltage to a ground voltage. There is an additional delay module which is configured to provide a delay in the logic input signal. This delayed logic input signal is operatively coupled to the second pull-up stage which takes the output of the driver from GND to VDD. The pull-down circuit is operatively coupled to the negative elevator for controlling a voltage at the driver output to the negative level.

Abstract: An impedance buffer has a single comparator with a first input and a second input. A first leg has a first pull-up array in series with a reference resistor. The first input of the single comparator is electrically coupled to a node between the first pull up array and the reference resistor. A second leg has a second pull-up array in series with a pull-down array. The second leg is coupled through a switch to the second input of the single comparator.

Abstract: A programmable logic device (PLD) data transfer cable includes a parallel interface, a programming interface, and a logic control circuit. The parallel interface is used for connecting to PLDs. The logic control circuit includes a first group of transmission channels, a second group of transmission channels, a first group of switches, and a second group of switches. The first and second group of switches control the working status of the first and second group of transmission channels respectively. The electrical connections between pins of the parallel interface and the programming interface when first group of transmission channels are activated are different with those when second group of transmission channels are activated.

Abstract: At least one of the disclosed systems includes driver logic that is capable of driving a device and pre-driver logic coupled to the driver logic and that drives the driver logic. If the pre-driver logic receives an input signal of a first type, the pre-driver logic activates a first transistor such that the pre-driver logic provides an output signal. If the pre-driver logic receives an input signal of a second type, the pre-driver logic activates a second transistor and a third transistor that together cause the pre-driver logic to provide a different output signal. If the third transistor is not activated, the pre-driver logic provides the output signal.

Abstract: In a semiconductor integrated circuit, a cell arrangement area is provided on a semiconductor substrate to allow a plurality of basis cells to be arranged. A basic power supply line is provided in an upper layer than the cell arrangement area to supply a power. A switch cell is configured to control the power supply from the basic power supply line to an inside of the cell arrangement area. An always operating cell is arranged in the cell arrangement area adjacently to the switch cell, and is configured to receive the power from the switch cell even when the switch cell stops the power supply to the cell arrangement area.

Abstract: The present invention relates to a circuit arrangement and method of controlling power consumption of the circuit arrangement, wherein a load applied at a circuit component is determined and the drive capacity of the circuit component is adjusted responsive to the determination result. In particular, the circuit component is tailored to have just sufficient drive capacity depending on the potential load which may be determined by examining a configuration information loaded to the circuit arrangement. Tailoring for sufficient drive can be achieved either by varying the size or number of circuit components or by adjusting the threshold voltage of circuit elements, or by doing both. Thereby, power consumption can be reduced when circuit components are driven at loads lower than the worst case load.

Abstract: A receiver for receiving a reduced swing signal from a transmission channel is disclosed, in which the swing of the reduced swing signal is less than the power supply of the receiver and possibly is less than the power supply of the transmitter. The receiver comprises a level shifter for offsetting the reduced swing signal, and an amplifier which receives both the reduced swing signal and its offset to produce a full swing signal output referenced to the power supply of the receiver. The full swing signal can thereafter be buffered, and eventually can be captured by a clock. Optionally, the disclosed reduced swing receiver also contains calibration circuitry for improving the integrity of the full swing signal output, and in particular for countering the effects of process, and in some embodiments temperature, variations, which alter the characteristics of the transistors which make up the receiver circuitry.

Abstract: An output buffer circuit includes a first output transistor having a source terminal connected to a voltage supply and a drain terminal connected to an output node. The first output transistor is capable of coupling the output node to the voltage supply when the input signal is at a high voltage in the input voltage range. The circuit also includes a second output transistor having a drain terminal connected to the output node and a source terminal connected to ground. The second output transistor is capable of coupling the output node to ground when the input signal is at a low voltage in the input voltage range. The circuit further includes a current-limiting circuit coupled to a gate terminal of the first output transistor and capable of limiting a current flowing through the gate terminal when the first output transistor is turned on. The output node outputs an output signal in an output voltage range, wherein a high voltage of the output voltage range exceeds the high voltage of the input voltage range.

Abstract: An integrated circuit device includes a high-speed serial interface circuit that includes a receiver circuit that receives differential signals through a serial bus, first and second guard terminals that prevent radiation, first and second terminals that are disposed between the first and second guard terminals and receive the differential signals, a first power supply terminal to which a high-voltage-side power supply voltage for the receiver circuit is supplied, and a second power supply terminal to which a low-voltage-side power supply voltage is supplied. A first switch element is provided between a line from the first guard terminal and a line from the second power supply terminal, and a second switch element is provided between a line from the second guard terminal and a line from the second power supply terminal. The first and second switch elements are turned ON in a high-speed serial interface mode.

Abstract: A level shifter for shifting an input signal to an output signal. The level shifter includes an input buffer biased a first voltage and a ground voltage; an output buffer and a level-processing unit both biased between a second voltage and the ground voltage; and a voltage-drop unit coupled to the level-processing unit and biased between the first voltage and the second voltage. While the first voltage is in an OFF state and the second voltage is switched on, the voltage-drop unit provides an initializing voltage for the level-processing unit according to the second voltage to shift the input signal to provide the output signal.

Abstract: An electronic circuit is provided comprising an input (VIN) for coupling a circuit of a first voltage domain to the electronic circuit, and a first, second, third and fourth transistor coupled between a supply voltage (VDD) and a voltage (VSS). The third transistor (M1) is coupled between the voltage (VSS) and a first node (tn). The second transistor (M2) is coupled between a second node (tp) and the output (VOUT). The third transistor (M3) is coupled between the first node (tn) and the output (VOUT). The fourth transistor (M4) is coupled between the supply voltage (VDD) and the second node (tp). A first reference voltage generating unit (RC) receives the voltage at the first node (tn) and the voltage (VSS) as input, and its output is coupled to the gate of the second transistor (M2). A second reference voltage generating unit (RD) receives the supply voltage (VDD) and the voltage of the second node (tp) as input, and its output is coupled to the gate of the third transistor (M3).

Abstract: A clock driving circuit and a method of driving a plurality of output lines for a PC architecture are disclosed. The clock driving circuit includes a clock generating circuit coupled to an output buffer for the PC having a plurality of output lines connected to a plurality of output loads having output load impedances. The output lines are driven differentially at an output voltage lower than a supply voltage. The circuit includes a voltage node having a voltage node impedance. The voltage node is maintained at substantially the output voltage. The circuit includes a current sinking transistor that sinks current from the voltage node. The current sinking transistor is operated in a linear region characterized by an ohmic resistance determined by the size of the current sinking transistor. The impedance of the voltage node is matched to one of the load impedances by sizing the current sinking transistor.

Abstract: Provided herein are bi-directional buffers, and methods for providing bi-directional buffering. In an embodiment, a bi-directional buffer includes a differential input/differential output amplifier that includes a first input/output node and a second/input output node. The differential input/differential output amplifier is configurable in a first configuration and a second configuration. When in the first configuration, the second input/output node follows the first input/output node. When in the second configuration, the first input/output node follows the second input/output node.

Abstract: An output circuit includes an output block and a predrive block for driving the output block based on an input signal. The predrive block has a clamp unit connected between the gate terminal of a first output transistor and the gate terminal of a second output transistor to limit the potential of the gate terminal of the first output transistor to a value of not more than a first potential and limit the potential of the gate terminal of the second output transistor to a value of not less than a second potential.

Abstract: An off-chip driver (OCD) includes: a logic circuit, for providing a logic signal input; a pre-driver stage, coupled to the logic circuit, for providing a ramped up voltage in response to the logic signal input; a final driver stage, coupled to the pre-driver stage, for providing an output voltage in response to the ramped up voltage; and a bias circuit, coupled to the pre-driver stage, for providing a constant bias voltage to the pre-driver stage, wherein the constant bias voltage keeps the pre-driver stage within an operational range to compensate for variations in process, temperature and supply voltage.

Abstract: An adaptive output driver has a number of transistors connected in series between a power supply and a ground. An adaptive bias input is coupled to a gate of one of the transistors.

Abstract: Embodiments of the present invention provide electronic devices, memory devices and methods of driving an on-chip signal off a chip. In one such embodiment, an on-chip signal and a second signal complementary to the on-chip signal are generated and provided to the two inputs of a differential driver. One output of the differential driver circuitry is coupled to an externally-accessible output terminal of the package. The other output may be terminated off the chip, but within the package. By routing the output signal and a second complementary output through the package, crosstalk potentially caused by the output signal can be reduced. Simultaneous switching output noise may also be reduced through use of a current-steering differential driver topology. Signal symmetry may also improve, reducing inter-symbol interference.

Abstract: A tolerant buffer circuit and interface are provided in which reverse inflow of current to a power supply voltage from an output terminal does not occur even if the output terminal is at a higher potential than an output circuit power supply voltage during open-drain operation in an output circuit of a semiconductor integrated circuit, or if the output circuit power supply voltage becomes 0 V. Tolerant buffer circuit 100 is provided with PMOS transistors Q111 and Q112 that are connected in series and that share a source between power supply terminal VDD1 and output terminal 102, NMOS transistor Q113 connected between output terminal 102 and ground terminal 101, inverter 121 output-connected to the gate of PMOS transistor Q111, inverter 122 output-connected to the gate of PMOS transistor Q112, and control circuit 130 that outputs first, second, and third control signals to PMOS transistor Q111, PMOS transistor Q112, and NMOS transistor Q113 respectively, and controls the on/off state of these MOS transistors.

Abstract: A buffer circuit uses (e.g., active) inductors for driving capacitive loads. In one embodiment, the buffer circuit has one or more stages, each stage having one CMOS inverter. Each CMOS inverter has one NMOS transistor and one PMOS transistor and is coupled to a stage input and a stage output. Additionally, at least one stage of the buffer circuit has two inductors, each coupled between a different voltage reference for the buffer circuit and the stage output. One inductor has a PMOS transistor coupled to the gate of an NMOS transistor and the other inductor has an NMOS transistor coupled to the gate of a PMOS transistor. When driving capacitive loads, the inductors partially tune out the apparent load capacitance CL, thereby improving the charging capabilities of inverter and enabling quicker charge and discharge times. Furthermore, partially tuning out apparent load capacitance facilitates the driving of larger capacitive loads.

Abstract: A desaturation circuit for an IGBT is disclosed. In one embodiment, flooding of the component with charge carriers is reduced before the IGBT is turned off.

Abstract: A floating driving circuit according to the present invention comprises an input circuit to receive an input signal. A latch circuit receives a trigger signal for generating a latch signal. The latch signal is used to turn on/off a switch. A coupling capacitor is connected between the input circuit and the latch circuit to generate the trigger signal in response to the input signal. A diode is connected from a voltage source to a floating supply terminal of the latch circuit for charging a capacitor. The capacitor is coupled between the floating supply terminal and a floating ground terminal of the latch circuit to provide a supply voltage to the latch circuit. The latch circuit is controlled by the input signal via the coupling capacitor.

Abstract: The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switches are included and configured to selectively couple a supply voltage to the output dependent on a mode of operation of the differential signaling circuitry. The circuit also includes a switch control biasing circuit operatively coupled to at least one of the switches and to the output of the differential signaling circuitry. The switch control biasing circuit provides a switch control biasing voltage to control a state of the switch based on a voltage level of the output. Further, a bulk biasing circuit is included and operatively coupled to the switch. The bulk biasing circuit selectively provides a bulk biasing voltage to the switch based on the voltage level of the output.

Abstract: An output buffer circuit is provided that outputs an input signal output from a circuit operating at a first power supply voltage to another circuit operating at a second power supply voltage higher than the first power supply voltage. The output buffer circuit includes an output driver circuit including a pull-up transistor and a pull-down transistor connected between the second power supply voltage and a reference voltage. A first driving circuit outputs a first control signal to control the pull-down transistor. A second driving circuit includes a latch circuit to latch signals and outputs a second control signal to control the pull-up transistor based on retained data in that latch circuit. A level shifter changes the retained data in the latch circuit when logic of the input signal changes.

Abstract: Differential signal output nodes of a novel CML buffer are DC-coupled by contiguous conductors to the differential signal input nodes of a load (for example, a CML logic element). The CML buffer includes a pulldown load latch that increases buffer transconductance and that provides a DC bias voltage across the conductors and onto the input nodes of the load, thereby obviating the need for the load to have DC biasing circuitry. Capacitors of a conventional AC coupling between buffer and load are not needed, thereby reducing the amount of die area needed to realize the circuit and thereby reducing the capacitance of the buffer-to-load connections. Switching power consumption is low due to the low capacitance buffer-to-load connections. Differential signals can be communicated from buffer to load over a wide frequency range of from less than five kilohertz to more than one gigahertz with less than fifty percent signal attenuation.

Abstract: In order to reduce production cost, an output buffer for an electronic device includes a first logic unit, a second logic unit, a first transistor, a second transistor and a control unit. The first logic unit and the second unit are both coupled to an input terminal and conductions of the first logic unit and the second unit are controlled by an input signal from the input terminal. The control unit is coupled to the first logic unit, the second logic unit, the first transistor and the second transistor, for controlling the first transistor and the second transistor to conduct at different times for implementing the non-overlapping function.

Abstract: An interface driver circuit includes a plurality of delay cells. Each delay cell includes a data input, a delayed data output configured to communicate with the data input of an adjacent one of the plurality of delay cells. A delay time input is configured to set a delay value between receiving data at the data input and generating the delayed data output. A plurality of predrivers is configured to receive an output enable signal. A plurality of predrivers is configured to receive a corresponding one of the plurality of delayed data outputs. A plurality of predrivers is configured to generate a predriver output signal based on the output enable signal and the corresponding one of the plurality of delayed data outputs. The output enable signal enables and disables the plurality of predrivers and is independent of data of each delayed data output.

Abstract: A low voltage differential signal (LVDS) transmitter with output power control. Internal sensing circuitry monitors output current flow through the termination impedance. When a proper termination impedance is not connected to the output, the resulting improper output current flow (e.g., zero output current when no termination impedance is connected) is detected by the sensing circuitry, which causes the supply current to the output driver circuitry to be reduced. Additionally, further in response to such detection of improper output current flow, the sensing circuitry can cause the output voltage to be limited, e.g., clamped, at a predetermined maximum magnitude.

Abstract: Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing input/output signals at a second voltage level, different from the first voltage level, to the logic circuit, the bank of gates including a port for setting the operational voltage level thereof; and a control circuit coupled to the port and governed by a control signal to configure the operational voltage level of the bank of gates to render the logic circuit and the interfacing input/output signals voltage level compatible.

Abstract: An output driver of a semiconductor memory apparatus comprises a voltage dividing block configured to generate divide voltages by dividing an internal voltage, a threshold voltage detecting block configured to generate a detecting voltage corresponding to a change in a threshold voltage of a transistor, a drive capability control signal generating block 300 configured to generate a compare signal by comparing the levels of the detecting voltage with the divide voltage and generate a control signal in response to an input signal when the compare signal is enabled, and a drive capability controlling block comprising a driver configured to perform a driving operation in response to the input signal, and a control driver configured to perform a driving operation in response to the control signal.

Abstract: A resistor circuit includes n-stage unit circuits, each of which includes a first resistor element provided between first and second terminals, a first disconnection element provided between the second and third terminals, and a second disconnection element and a second resistor element provided in series between the second and fourth terminals. The first terminal of each of the n-stage unit circuits is connected with a first interconnect, the fourth terminal of each of the n-stage unit circuits is connected with a second interconnect, the third terminal of the first-stage unit circuit is connected with a third interconnect, and the third terminal of the mth-stage unit circuit is connected with the second terminal of the (m?1)th-stage unit circuit.

Abstract: A circuit for de-emphasizing information transmitted via a differential communication link includes a voltage mode differential circuit and a bi-directional current source circuit. The voltage mode differential circuit includes a first and second output terminal. The voltage mode differential circuit provides a first voltage via the first output terminal and second voltage via the second output terminal in response to a differential input voltage. The bi-directional current source circuit is operatively coupled between the first and second terminals. The bi-directional current source circuit selectively provides current in a first and second direction between the first and second terminals based on the first and second voltage.

Abstract: Processor-based systems, memories, signal driver circuits, and methods of generating an output signal are disclosed. One such signal driver circuit includes a signal driver configured to generate an output signal at an output node in response to an input signal and a transistor coupled to the signal driver that is configured to couple and decouple the output node and the voltage supply according to a control signal. A voltage comparator circuit coupled to the output node and the transistor is configured to generate the control signal to control coupling and decoupling of the output node and the voltage supply through the transistor based on a voltage of the output signal relative to the reference voltage.

Abstract: In order to provide a semiconductor device having a circuit for operating normally even when the amplitude of a signal voltage is smaller than the amplitude of a power source voltage, a correcting circuit is provided before a digital circuit to be operated normally. As for a signal outputted from the correcting circuit, when a transistor in the objective digital circuit is required to be turned OFF, the correcting circuit outputs a corresponding signal, namely a first power source potential. At this time, the transistor is turned OFF. On the other hand, when the transistor is required to be turned ON, the correcting circuit outputs a first input potential. Consequently, the objective digital circuit is turned OFF when it is required to be in an OFF state while turned ON when it is required to be in an ON state. Thereby, the objective digital circuit can be normally operated.

Abstract: A circuit for reducing EMI is provided. The circuit includes driver circuitry that drives a power switch, such as a power MOSFET. The power switch provides an output voltage. The circuit decreases the drive strength by which the power switch is driven during each output edge (i.e. when the output goes from low to high (rising edge) or high to low (falling edge)), and returns the drive strength to its normal level when the output edge is complete or approximately complete. Reducing the drive strength of the driver circuitry causes the output edge to occur over a longer period of time. This results in reduction of the EMI of the device.

Abstract: A multistage dual logic level voltage translator for translating both high and low input logic levels to higher levels, at least one of which levels is above the maximum recommended voltage of transistors implementing the stages, includes an input stage for receiving input logic levels and an output stage including a high voltage converter having at least a pair of cross-coupled converter transistors responsive to the input stage and including a pair of clamping circuit connected one across each of the converter transistors, for providing the shifted low and high output logic levels.

Abstract: A source terminated serial link can recover from a low power mode by turning on multiple current-mode drivers in a phased sequence where the phased sequence is related to a resonant characteristic of a power supply net.

Abstract: A driver for a power converter, method of driving a switch thereof, and a power converter employing the same. In one embodiment, the driver includes switching circuitry referenced to a voltage level and configured to provide a drive signal for a switch referenced to another voltage level and subject to a control voltage limit. In a related, but alternative embodiment, the driver is employable with a power converter couplable to a source of electrical power adapted to provide an input voltage thereto. The power converter includes a power train having a switch referenced to the input voltage and subject to a control voltage limit. The driver includes switching circuitry referenced to a voltage level different from the input voltage and configured to provide a drive signal for the switch within the control voltage limit of the switch.

Abstract: Method and apparatus are provided for buffering a data signal to a low voltage logic device. A circuit for buffering the data signal to the low voltage logic device includes an output buffer and an N-type transistor. The output buffer has an input and an output, where the input is configured to receive the data signal. The output buffer is configured to produce an output signal based on the data signal, and the output signal has a maximum potential. The N-type transistor has a source coupled to the output, a drain configured to couple to the low voltage logic device, and a gate configured to receive a bias potential, where the bias potential is greater than the maximum potential.

Abstract: In a circuit to convert a first logic signal having a first range to a second logic signal having a second range, a first metal oxide semiconductor (MOS) transistor selectively couples an output node to a first reference voltage when the output node is to be in a first state. A source-follower circuit includes a current source and a source follower output, and the source follower output is coupled to the output node. A second MOS transistor selectively couples the source-follower circuit to a second reference voltage when the output node is to be in the second state.

Abstract: A level shifter comprises a voltage converting circuit, a voltage pull-up circuit, and a control signal generating circuit. The voltage converting circuit is configured to receive an input signal of a first voltage level and to output an output signal of a second voltage level. The voltage pull-up circuit is coupled to the voltage converting circuit and configured to expeditiously pull up a voltage of an output node of the level shifter to the second voltage level in response to a control signal. The control signal generating circuit is configured to receive the input signal and to provide the control signal to the voltage pull-up circuit. The control signal generating circuit includes three transistors.

Abstract: An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal. The advanced repeater may further include circuitry for producing a delayed version of the signal.