Abstract: A driving circuit includes a common well. The driving circuit further includes a first output buffer having a bulk connected to the common well, the first output buffer having a first terminal configured to receive a first signal, and having a second terminal connected to the common well. The driving circuit further includes a second output buffer having a bulk connected to the common well, the second output buffer having a first terminal configured to receive the first signal, wherein a second terminal of the second output buffer disconnected from the common well. The driving circuit further includes a first driver connected to the second terminal of the first output buffer and a second driver connected to the second terminal of the second output buffer.

Abstract: Techniques for reducing crowbar current are disclosed. In one embodiment, a circuit for reducing crowbar current comprises an inverter having an input and an output, a first switch coupled between the inverter and a first power supply rail, and a second switch coupled between the inverter and a second power supply rail. The circuit also comprises a feedback circuit coupled to the output of the inverter, wherein the feedback circuit is configured to turn off the first switch when the output of the inverter is in a low output state, and to turn off the second switch when the output of the inverter is in a high output state.

Abstract: A driver having low power consumption includes a first input terminal, a second input terminal, an output terminal, a power supply terminal, a ground terminal, a driving circuit, an adjusting circuit connected to the driving circuit and a biasing circuit which is connected to the driving circuit and the adjusting circuit. A method for accomplishing low power consumption of a driver is also provided. The method accomplishes an object of low power consumption by dynamically adjusting a driving current of a driver according to a difference between inputted differential signals.

Abstract: An apparatus includes a number of current steering switches and a power controller. A current source is coupled to the current steering switches and to the power controller. The current source is controlled to provide a first voltage to the current steering switches. The apparatus also includes a number of pre-drivers. The power controller is configured to provide a second voltage to the plurality of pre-drivers. The second voltage is dependent on the first voltage.

Abstract: A semiconductor device and a power voltage supply circuit for a test operation of a semiconductor system including the semiconductor device. The semiconductor device receives first and second power supply voltages in a normal operation mode from an external device and receives the first power supply voltage in a test operation mode. The semiconductor device includes a voltage level setting unit configured to set a power connection node at a voltage between a voltage level of a first power supply voltage terminal and a voltage level of a ground voltage terminal according to an operation mode signal, and a voltage driving unit configured to drive a second power supply voltage terminal with the first power supply voltage in the test operation mode, wherein the driving power is controlled according to the voltage level of the power connection node.

Abstract: A buffer control circuit includes a current supply unit configured to supply current and adjust the current in response to codes, an amplifying buffer configured to operate using the current and output a value obtained by comparing a reference potential and the reference potential, a second buffer configured to buffer an output of the first buffer, and a code generation unit configured to generate the codes in response to an output of the second buffer.

Abstract: A circuit may include an oscillator configured to generate an output signal based on an analog signal and a digital signal and a controller configured to generate an offset signal based on a comparison of a first analog control signal and a second analog control signal. The circuit may also include a divider configured to generate a feedback signal based on the output signal and the offset signal. The circuit may also include an analog control signal unit configured to generate the second analog control signal based on the feedback signal and a reference signal and a coupling unit configured to select either the first analog control signal or the second analog control signal as the analog signal.

Abstract: A semiconductor device includes an information generation circuit configured to generate first information, an information multiplexing circuit configured to multiplex the first information and second information, and an information driving circuit configured to drive an output pad in response to an output signal of the information multiplexing circuit.

Abstract: Current drivers and biasing circuitry at least partly compensate for manufacturing variations and environmental variations such as supply voltage, temperature, and fabrication process.

Abstract: A PWM modulator as might be used in a power converter, a drive signal will be generated on an output pin of an integrated circuit PWM controller device which is used to drive the output when the modulator is required to be on.

Abstract: Described is an apparatus which comprises: a first node to provide an un-gated power supply; a second node to provide a threshold dependent supply; an inverter with an input and an output, the inverter coupled to the first and second nodes, the inverter to receive the un-gated power supply at its power supply node, and to receive the threshold dependent supply for supplying ground supply at its ground node; and a transistor with its gate terminal coupled to the output of the inverter, the transistor to provide gated power supply to one or more logic units.

Abstract: A gate drive circuit includes a power supply circuit that has an output switch function for switching a voltage value of a drive voltage between two levels, a gate-ON drive circuit that outputs a constant electric current toward a gate of an IGBT from an output terminal of the power supply circuit, and a control section performs a constant electric current drive of a gate of the IGBT at a time of a turn-ON by operating the gate-ON drive circuit. At a turn-ON start time, the control section sets the drive voltage to a relatively-high first set value, and then switches the drive voltage to a relatively-low second set value at a switch timing after a mirror period end time.

Abstract: A power control integrated circuit is provided having a voltage switching device and a retention switching device that has an input from an overdrive voltage supply such that in a retention enabled configuration a retention switching device is switched on more strongly relative to being both coupled to and driven from the voltage supply input signal associated with the voltage switching device. An overdriven retention switching device is provided as a separate entity from the voltage switching device itself and a computer readable storage medium is provided storing a data structure comprising a standard cell circuit definition for use in generating validating the circuit layout of a circuit cell of an integrated circuit. The circuit cell comprising an overdriven retention switching device.

Abstract: A circuit includes a first input transistor and a first voltage divider coupled to a source of the first input transistor and a second input transistor and a second voltage divider coupled to a source of the second input transistor. A first set of series connected transistors include a first transistor with a gate coupled to the first input transistor source and a second transistor with a gate coupled to a tap of the first voltage divider. A second set of series connected transistors include a third transistor with a gate coupled to the second input transistor source and a fourth transistor with a gate coupled to a tap of the second voltage divider. An output is coupled to the sources of the first and second input transistors. The first and second sets are coupled to one of the first input transistor drain or second input transistor drain.

Abstract: A semiconductor device includes an external voltage detection unit suitable for detecting a voltage level of an external voltage to output an external voltage detection signal based on the detected result, a reference voltage generation unit suitable for generating a reference voltage based on the external voltage, an internal voltage generation unit enabled in response to the external voltage detection signal, suitable for selectively generating a voltage corresponding to the reference voltage as an internal voltage, and an internal voltage control unit suitable for selectively providing a voltage having a target level corresponding to the internal voltage as the internal voltage in response to the external voltage detection signal.

Abstract: A display apparatus and a source driver thereof are disclosed. The source driver includes a temperature sensor and a power switch. The temperature sensor is configured to measure a first working temperature of the source driver, and generate an over-temperature protection enable signal by comparing the first working temperature with a preset temperature. The power switch is coupled to a power transmission path for a core circuit of the source driver to receive an operating power, and configured to turn on or cut off the power transmission path according to the over-temperature protection enable signal.

Abstract: A bus driver circuit (FIG. 2) is disclosed. The circuit includes a signal lead of a bus (200) and a reference terminal (Vss). A first transistor (MN0) has a first control terminal and has a first current path coupled to the reference terminal. A second transistor (MN1) has a second control terminal coupled to the first control terminal and has a second current path coupled between the signal lead and the reference terminal. A third transistor (MP0) is arranged to provide a first current through the first current path when the signal lead is in a first logic state (high). A fourth transistor (MP1) is arranged to apply a voltage to the second control terminal when the signal lead is in a second logic state (low).

Abstract: In accordance with one or more example aspects of the disclosure, communications are effected on a bus using bit time and slew rate feedback. As consistent with one or more embodiments, communications are effected in a network including a master circuit and a plurality of slave circuits, on bus that is controlled by the master circuit corresponding to master and slave data communication. A feedback signal is provided, which is indicative of a slew rate and bit time of signals communicated between the master and slave circuits on the bus. Data is transmitted on the bus by generating output signals via a waveform corresponding to an input signal, and controlling the waveform based upon the slew rate and bit time indicated via the feedback signal.

Abstract: A source driver with reduced number of latch devices includes a master latch device and at least one slave latch device. The master latch device has a first transmission gate, a first inverter, a second inverter, a first enable gate, and a second enable gate. The output of the second inverter is connected to the input of the first inverter. The at least one slave latch device has a second transmission gate, a third inverter, and a fourth inverter. When the first enable gate and the second enable gate receive a latch enable signal and a complementary latch enable signal respectively, the master latch device and the at least one slave latch device are concurrently driven to latch data.

Abstract: A semiconductor device arrangement and a method. One embodiment includes at least one power transistor and at least one gate resistor located between a gate of the power transistor and a connecting point in the drive circuit of the power transistor. The semiconductor device arrangement includes a switchable element between the connecting point and a source of the power transistor.

Abstract: The present document relates to a reduction of heat generated in driver circuits comprising voltage regulators. A circuit arrangement comprises a driver circuit configured to generate a control signal for driving a power switch. The driver circuit comprises a voltage regulator configured to generate a second voltage from a supply voltage, a drive unit configured to generate the control signal based on the supply voltage and configured to provide the control signal to a control interface of the driver circuit, and a logic component operating at the second voltage and drawing a second current, and configured to control the drive unit. Furthermore, the circuit arrangement comprises bypass circuitry coupled at an input to the control interface and configured to provide at an output at least part of the second current to the logic component.

Abstract: An output driving circuit includes a first pull-up transistor, a first pull-down transistor and a second pull-down transistor. The first pull-up transistor is configured to generate a first output signal at the output node in response to a first control signal. The first pull-down transistor is configured to generate a second output signal at the output node in response to a second control signal. The second pull-down transistor is configured to connect the output node to the first ground voltage in response to a third control signal. The memory device including the output driving circuit may be insensitive to noise and may have little data transmission error.

Abstract: To provide a composite semiconductor device capable of preventing malfunction of preventing electrical circuits and contributing to miniaturization of a power converter. A composite semiconductor device 10 has a structure in which a first power semiconductor element 13 that passes current from a second terminal C1 to a third terminal E1 according to a signal input from a first terminal G1 and a second power semiconductor element 16 that passes current from a second terminal C2 to a third terminal E2 according to a signal input from a first terminal G2 are formed in a single substrate (chip) 20. The third terminal E2 of the second power semiconductor element 16 is electrically connected to the first terminal G1 of the first power semiconductor element 13.

Abstract: Apparatus and methods may operate so that arrival times of a data signal at gates of transistors are controlled to switch the transistors at different times to modulate the slew rate of a signal on a node. Additional embodiments are also described.

Abstract: The impedance of the elements of a capacitor array in the transmitter is kept substantially constant over changes in process, temperature, and supply voltage. The impedance is maintained substantially constant by compensating a gate voltage supplied to switches in each element of the capacitor array to adjust for changes in temperature and supply voltage to thereby maintain a substantially constant RC product for each unit element in the capacitor array and thereby improve the quality factor of the capacitor array.

Abstract: A driving device is disclosed, which relates to a technology for reducing consumption of a leakage current unnecessary for a driver circuit. The driving device includes: a pre-driver configured to output a drive control signal upon receiving a power-supply voltage in response to an input signal, and change a voltage level of the drive control signal in response to a control signal so as to selectively provide the changed voltage level; an output driver configured to receive the power-supply voltage in response to the drive control signal, and output the received power-supply voltage to an output terminal; and a bulk-voltage controller configured to selectively control bulk-voltage levels of the pre-driver and the output driver in response to the control signal.

Abstract: Provided is a semiconductor device with an output circuit in which a variation of a common voltage is suppressed in an idling mode and in a normal mode. The output circuit provided in the semiconductor device includes a first termination resistor and a second termination resistor and a drive circuit which flows current through the termination resistors. The output circuit is configured so as to be able to adjust the value of current which flows through the first termination resistor and the second termination resistor or the value of resistance of the first termination resistor and the second termination resistor.

Abstract: A semiconductor device includes a normal code generation unit capable of generating a normal code, a test code output unit capable of storing a plurality of preliminary test codes to output a test code in response to a test control signal, and a reference voltage generation unit capable of generating a normal reference voltage in a normal operation mode and generating a test reference voltage in a test operation mode in response to the normal code and the test code.

Abstract: A circuit may include an input node configured to receive a signal and an output node configured to be coupled to a load. The circuit may also include a first circuit coupled between the input node and the output node. The first circuit may be configured to receive the signal and to drive the signal on the output node at a first voltage. The circuit may also include an active device coupled to the output node and a second circuit coupled to the active device and the input node. The second circuit may be configured to receive the signal and to drive the signal to the active device at a second voltage. The circuit may also include a tap circuit configured to selectively apply a modified version of the signal to the signal driven by the second circuit before the signal driven by the second circuit reaches the active device.

Abstract: A driving circuit of flat display including a charging circuit path, a discharging circuit path, and a detecting circuit is provided. The charging circuit path has first and second impedance states, wherein an impedance value of the first impedance state is smaller than that of the second impedance state. The discharging circuit path has third and fourth impedance states, wherein an impedance value of the third impedance state is smaller than that of the fourth impedance state. The detecting circuit detects whether the charging circuit path or the discharging circuit path is in an unstable first state or stable second state, controls the charging circuit path to the first impedance state or the discharging circuit path to the third impedance state in the first state, and controls the charging circuit path to the second impedance state or the discharging circuit path to the fourth impedance state in the second state.

Abstract: A circuit may include an input node configured to receive a signal and an output node configured to be coupled to a load. The circuit may also include a first circuit coupled between the input node and the output node, the first circuit being configured to receive the signal and drive the signal on the output node at a first voltage. The circuit may also include a signal adjust circuit configured to adjust a current of the signal driven by the first circuit. The signal adjust circuit may be configured to apply a first current adjustment to adjust the current of the signal at one but not both of a falling edge of the signal or a rising edge of the signal.

Abstract: A signal transmission device includes a driver chip and a receiver. The driver chip is connected to a signal source to receive a first signal. The driver chip compensates the first signal into a second signal according to a preset coefficient. The driver chip outputs the second signal to the receiver.

Abstract: This disclosure provides circuits and methods for reducing sub-threshold leakage currents discharging floating nodes. In one aspect, feedback from a floating node is provided to a feedback transistor configured to bias other nodes such that leakage through turned-off transistors is reduced. Additionally, leakage contributing to static power consumption may also be reduced.

Abstract: A data transfer circuit includes a plurality of first lines, a second line suitable for receiving data from a first line selected among the first lines, a third line suitable for transferring data to the first line selected among the first lines, a plurality of driving units, each suitable for driving the second line based on the data from the corresponding first line in a first operation, and a plurality of connection units, each suitable for coupling the third line to the corresponding first line when the corresponding first line is selected in a second operation.

Abstract: A circuit may include a controller, at least one bridge circuit, and a plurality of switches. The plurality of switches may be connected parallel to each other, each may have a switch output connected to the bridge circuit. The bridge circuit, upon receiving a current from the plurality of switches, may generate an output based on a reference voltage. The controller may generate a plurality of control signals, based on a voltage transition range, to selectively turn on the plurality of the switches in more than one combination, to supply a current to the output.

Abstract: Systems and methods for providing differential line drivers include a device having an input configured to receive an input signal and a driver circuit configured to generate a first output and a second output from the input signal. The second output is a complementary output to the first output, wherein the first output has a first transfer characteristic and the second output has a second transfer characteristic different than the first transfer characteristic. The first and second transfer characteristics include an offset from respective input values of the input signal. The device further includes an output configured to output as a differential signal the first output and the second output generated by the driver circuit, wherein the offset in the first and second transfer characteristics defines a fail-safe output state for the differential signal.

Abstract: An inverter circuit includes an input stage and an output stage, each including pairs of complementary transistors having low-voltage oxides. The transistors within the input stage are configured to receive the input signal and to provide control voltages in response to input signal voltage variations. The voltage level of one control voltage is clamped between an intermediate voltage and a high voltage, and the voltage level of the other control voltage is clamped between the intermediate voltage and a low voltage. The switching states of each complementary transistor in the output stage are controlled by the control voltages, which results in an output signal voltage varying between the high and the low voltage. The voltage clamping advantageously allows the inverter circuit to switch between the high and the low voltage level without exceeding a maximum gate-source or a gate-drain voltage rating for any transistor, and without requiring additional passive components.

Abstract: An H-bridge driver without implementing with the PWM mode is disclosed. The H-bridge driver of the invention includes a non-inverting amplifier and an inverting amplifier commonly connected to the control signal. When the control signal exceeds the reference, the non-inverting amplifier commonly drives the first pair of transistors diagonally connected to the load. The low side transistor fully turns on but the high side transistor linearly operates. When the control signal is less than the reference, the inverting amplifier commonly drives the second pair of transistors also diagonally connected to the load.

Abstract: An adaptive gate drive circuit that can generate a gate bias voltage with temperature compensation for a MOSFET is disclosed. The adaptive gate drive circuit may generate the gate bias voltage with variable drive capability to combat higher gate leakage current of the MOSFET at higher temperature. In one design, an apparatus includes a control circuit and a gate drive circuit. The control circuit generates at least one control signal having a variable frequency determined based on a sensed temperature of the MOSFET. For example, a clock divider ratio may be determined based on the sensed temperature of the MOSFET, an input clock signal may be divided based on the clock divider ratio to obtain a variable clock signal, and the control signal(s) may be generated based on the variable clock signal. The gate drive circuit generates a bias voltage for the MOSFET based on the control signal(s).

Abstract: A circuit includes an input stage configured to receive a regulated input signal and generate an input stage output signal in response to the regulated input signal. An isolation stage can be configured to pass the input stage output signal to a buffered output node. The isolation stage receives feedback from the buffered output node to deactivate the buffer input stage if transient voltages are generated at the buffered output node. An output stage can be configured to provide current to the buffered output node in response to the regulated input signal.

Abstract: The invention relates to a method of opening a shunt switch carrying a current, the switch being connected in parallel with at least one thyristor of a high voltage DC network, interruption of the current flowing through the switch being initiated at the time of a current zero of the current flowing through the switch, the method being characterized in that it includes, based on a measurement effected by means for measuring the current flowing through the switch, a step of adjusting a control angle of the thyristor to position the current zero in a zone in which the time derivative of the measured current is a continuous function and the absolute value of a peak value of the measured current is substantially equal to the absolute value of the inaccuracy of the measurement of the current zero.

Abstract: A control circuit for generating a first control signal and a second control signal includes: an inverter, used for generating an inverted clock according to an input clock; a first delay circuit, used for generating a first delay control signal; a second delay circuit, used for generating a second delay control signal; a first mask circuit, used for generating a first mask signal according to the input clock; a second mask circuit, used for generating a second mask signal according to the inverted input clock; a first logic determining circuit, used for generating the first control signal to the first delay circuit according to the second mask signal and the input clock; and a second logic determining circuit, used for generating the second control signal to the second delay circuit according to the first mask signal and the inverted clock.

Abstract: A driving device is disclosed, which relates to a technology for reducing consumption of a leakage current unnecessary for a driver circuit. The driving device includes: a pre-driver configured to output a drive control signal upon receiving a power-supply voltage in response to an input signal, and change a voltage level of the drive control signal in response to a control signal so as to selectively provide the changed voltage level; an output driver configured to receive the power-supply voltage in response to the drive control signal, and output the received power-supply voltage to an output terminal; and a bulk-voltage controller configured to selectively control bulk-voltage levels of the pre-driver and the output driver in response to the control signal.

Abstract: A population of drivers is provided in parallel to a driver output and a population of pre-emphasis path drivers is provided in parallel to the driver output. The population of drivers is updated and the population of pre-emphasis path drivers is updated in an inverse relation to the updating of the population of pre-emphasis path drivers. Optionally, the population of drivers has an initial value of n and the population of pre-emphasis path drivers has an initial value of m, and the sum of n and m is P. Optionally, the updated population of n is n? and the updated population of m is m?, and n? is approximately equal to P?m?.

Abstract: A driver includes a first driver stage having at least one input node and at least one first output node. The first driver stage includes a T-coil structure that is disposed adjacent to the at least one first output node. The T-coil structure includes a first set of inductors each being operable to provide a first inductance. A second set of inductors are electrically coupled with the first set of inductors in a parallel fashion. The second set of inductors each are operable to provide a second inductance. A second driver stage is electrically coupled with the first driver stage.

Abstract: According to one embodiment, a line driver circuit comprises a plurality of output stages each operable to produce an output signal and one or more pre-output stages operable to perform one or more common functions. The line driver circuit also comprises circuitry operable to selectively couple one or more of the output stages to the one or more pre-output stages based on a wireline communication technology implemented by the line driver circuit.

Abstract: A circuit includes a bipolar transistor circuit including a first node, a second node, and a plurality of bipolar transistors coupled in parallel between the first node and the second node. The circuit further includes a drive circuit configured to switch on a first group of the plurality of bipolar transistors, the first group including a first subgroup and a second subgroup and each of the first subgroup and the second subgroup including one or more of the bipolar transistors. The drive circuit is further configured to switch off the first subgroup at the end of a first time period and switch off the second subgroup at a time instant before the end of the first time period.

Abstract: Methods and apparatus for providing either high-speed, Or lower-speed, flexible inputs and outputs. An input and output structure having a high-speed input, a high-speed output, a low or moderate speed input, and an low or moderate speed output is provided. One of the input and output circuits are selected and the others are deselected. The high-speed input and output circuits are comparatively simple, in one example having only a clear signal for a control line input, and are able to interface to lower speed circuitry inside the core of an integrated circuit. The low or moderate speed input and output circuits are more flexible, for example, having preset, enable, and clear as control line inputs, and are able to support JTAG boundary testing. These parallel high and lower speed circuits are user selectable such that the input Output structure is optimized between speed and functionality depending on the requirements of the application.

Abstract: The present invention discloses a gate driver circuit. The gate driver circuit includes a plurality of driving units electrically connected in series, wherein the gate driver circuit receives a plurality of frequency signals and the driving units transmit a plurality of output signals sequentially. Furthermore, each driving unit includes a primary circuit, a first voltage regulator circuit and a second voltage regulator circuit.

Abstract: An output circuit includes a current source and a first MOS transistor coupled in series between a power supply terminal and an output terminal. The first MOS transistor includes a backgate coupled to a drain of the second MOS transistor. The second MOS transistor includes a source coupled to a source of a third MOS transistor. The second MOS transistor includes a source coupled to backgates of the second and third MOS transistors. The backgates of the second and third MOS transistors are in a floating condition.