Abstract: A transistor being one of an IGBT and a MOSFET and arranged near a gate control circuit applies a gate control signal from the gate control circuit to the gate of a transistor arranged far from the gate control circuit. A gate control signal is applied via a resistive element to the transistor arranged near the gate control circuit.

Abstract: A circuit includes a first power node at a first voltage level, a second power node at a second voltage level, a first voltage driver, a first current driver, and a control unit. The first voltage driver is configured to electrically couple a first output node to the first power node when a first input signal at the first input node is at a first logic state, and electrically couple a first output node to the second power node when the first input signal is at a second logic state. The first current driver is configured to inject or extract a first adjustment current into or out of a first output node. The control unit is configured to generate a measurement result of the first voltage level, and to set the first adjustment current according to the measurement result.

Abstract: An output buffer comprises a series connection of a first field effect transistor and a second field effect transistor, wherein the first field effect transistor is connected to a first supply potential terminal and the second field effect transistor is connected to a second supply potential terminal. An output terminal is connected to a common connection of the first transistor and the second transistor. The output buffer has a series connection of a resistive element and a capacitive element, wherein the capacitive element is connected to the output terminal, and a control circuit, to which an input signal is provided. The control circuit controls the transistors in such a way that turning off of a transistor is performed immediately, while turning on of a transistor is performed depending on the charging or discharging of the capacitive element, thus achieving a defined slew rate of the output signal at the output terminal.

Abstract: A switching device driving apparatus for preventing arm short circuit is provided, including: a first switching device driving unit for receiving a control signal for controlling a first switching device and a second switching device so that they will not turn ON at the same time and outputting an ON/OFF drive signal to the first switching device; and a second switching device driving unit for receiving the control signal and outputting an ON/OFF drive signal to the second switching device, in which the first switching device driving unit outputs a drive signal for increasing the delay of the ON timing of the first switching device with respect to the OFF timing of the second switching device with increase in ambient temperature.

Abstract: A receiver circuit includes a first amplification unit, a second amplification unit, a first equalizing unit, and a second equalizing unit. The first amplification unit is configured to differentially amplify an input signal and a reference signal and generate a first intermediate output signal and a second intermediate output signal. The second amplification unit is configured to differentially amplify the first and second intermediate output signals and generate an output signal. The first equalizing unit is configured to control the level of the second intermediate output signal in response to the output signal. And the second equalizing unit is configured to control the level of the first intermediate output signal in response to the output signal.

Abstract: Aspects of rail-to-rail line drivers using differential cascode bootstrapping are described. In one embodiment, a differential line driver includes first and second differential driver output legs. The first output leg includes a first p-type cascode stack and a first n-type cascode stack, and the second output leg includes a second p-type cascode stack and a second n-type cascode stack. The differential line driver also includes a differential cascode bootstrap circuit arrangement coupled to an output of the differential line driver. More particularly, the differential cascode bootstrap circuit arrangement is coupled between the first and second differential output driver legs and the output of the differential line driver. According to aspects of the embodiments described herein, differential line drivers with overvoltage protection and rail-to-rail output swings may be achieved. Further, the differential line drivers may be generally smaller, with cascode stack transistors of reduced in size.

Abstract: Various aspects are directed to providing an output/state based upon an input value. Consistent with one or more embodiments, an apparatus includes a bias circuit that is connected between power and common rails and includes first and second current paths that provide first and second reference currents. A current-mirroring circuit provides a first mirrored current in response to a voltage input transitioning in a first direction between voltage levels, and a second mirrored current in response to a voltage input transitioning in an opposite direction. A logic circuit operates in a first state based upon the first mirrored current and the first reference current, and operates in a second state based upon the second mirrored current and the second reference current.

Abstract: The present invention relates to a switch controller, a switch control method, and a power supply using the switch controller. A switch controller controls switching operation of a power switch and receives a sense voltage of a sense resistor to which a drain current flowing in the power switch flows. The switch controller generates a sum signal using the sense voltage and a ramp signal having a cycle that is the same as a switching cycle of the power switch. The switch controller determines short-circuit of the sense resistor by detecting slope variation of the sum signal.

Abstract: There is disclosed a gate driver, a driving circuit, and a liquid crystal display (LCD), wherein the gate driver comprises input terminals for inputting a CPV signal, an OE signal, and an STV signal, and output terminals for outputting a CKV signal and a CKVB signal, and a processing circuit is connected between the input terminals and the output terminals for processing the CPV signal, the OE signal, and the STV signal such that a preset time interval is present between the falling edge of the CKV signal and the rising edge of the CKVB signal during one period of the CKV signal, or a preset time interval is present between the rising edge of the CKV signal and the falling edge of the CKVB signal during one period of the CKVB signal.

Abstract: A tunable buffer circuit has a first tunable buffer cell receiving an input signal. A first transmission line is coupled to the first tunable buffer cell. A second tunable buffer cell is coupled to the first transmission line. A center frequency and bandwidth of the second tunable buffer cell is matched to a center frequency and bandwidth of the first tunable buffer cell to achieve low phase noise with low power. Additional transmission lines and tunable buffer cells can be cascaded in the tunable buffer circuit. Each tunable buffer cell has first and second transistors including first and second conduction terminals and control terminal coupled for receiving the input signal. An inductor and tunable capacitor are coupled between the first conduction terminals of the first and second transistor. A digital signal adjusts the tunable buffer cells in response to an RSSI which monitors the output for proper signal strength.

Abstract: A transistor circuit includes at least one transistor, wherein at least part of a connecting portion that connects the transistor (Tr1) and a power supply line (33) is formed from a material of which a channel of the transistor (Tr1) is made. This configuration reduces a circuit area of the transistor circuit.

Abstract: Disclosed herein is a device that includes first and second buffer circuits connected to a data terminal and a first control circuit controlling the first and second buffer circuits. The first control circuit receives n pairs of first and second internal data signals complementary to each other from 2n input signal lines and outputs a pair of third and fourth internal data signals complementary to each other to first and second output signal lines, where n is a natural number more than one. The first and second buffer circuits are controlled based on the third and fourth internal data signals such that one of the first and second buffer circuits turns on and the other of the first and second buffer circuits turns off.

Abstract: A bridge output circuit includes an output terminal, a high side transistor, a low side transistor, a high side driver for controlling a gate voltage of the high side transistor, a low side driver for controlling a gate voltage of the low side transistor, and a controller for controlling the high side and low side drivers. The low side driver includes a first current source, a second current source, and a first assist circuit. The controller is configured to control the turning-on and turning-off states of the first current source, the second current source and the first assist circuit.

Abstract: Described is an integrated circuit (IC) which comprises: an input-output (I/O) pad for coupling to a transmission line; a voltage mode driver coupled to the I/O pad, the voltage mode driver having a pull-up driver and a pull-down driver; and a current mode driver coupled to the I/O pad, the current mode driver operable to function in parallel to the voltage mode driver.

Abstract: The electronic circuit includes a transistor having a gate terminal, a source terminal and a drain terminal. A resistor has a first terminal connected to the gate terminal and has a second terminal connected to an auxiliary pad. When the electronic circuit is operating in a test phase and is configured for receiving a test signal for performing the test of the transistor, the auxiliary pad is electrically floating. When the electronic circuit is operating in a normal phase and is configured for receiving a supply voltage, the auxiliary pad is electrically connected to a voltage value smaller than the sum of the voltage value of the source terminal with the threshold voltage value of the transistor.

Abstract: There is provided a multi power supply type level shifter. The provided multi power supply type level shifter includes a first level shifter and a second level shifter in a two-stage architecture so as to selectively receive first to third power supplies and change a signal level, even when the first to third power supplies are applied in a different sequence from a normal power-on sequence. Output voltages are output without a change in level, and short-circuit currents are not generated in the first and second level shifters.

Abstract: A Tx IC and an Rx IC that use different supply voltages are mounted on a circuit board and interfaced via traces of the board. The configuration of the Tx IC is such that DC decoupling is provided between the ICs while also preventing inadvertent turn-on of the ESD diodes of the Rx IC. These features make it possible to provide DC decoupling between high-performance Tx ICs that use relatively high supply voltages and Rx ICs that use relatively low supply voltages without the need for AC coupling capacitors and while also preventing ESD protection of the Rx IC from being degraded.

Abstract: An electrical-optical modulator may function at high data rates and may be realized in comparably low cost silicon base technology, typically in BJT, BiCMOS or CMOS technologies. The output signal path may include a high transition frequency BJT and by using an active load constituted by a MOS driven by an inverted version of the modulating signal that drives the BJT, the falling edge of the output signal is sped up.

Abstract: Method and apparatus for electrosurgery including tissue coagulation using very high voltage pulses of electrical energy applied to the electrosurgical probe. This minimizes heating of the surrounding tissue in the probe and is especially suitable for precise and limited coagulation and fulguration without excessive tissue charring or other damage. The power at rated load of the applied pulses to the probe is typically over 300W and the duration of the on time is very short, so each group of pulse bursts is of relatively low duty cycle. An RF generator is also provided for delivering electrical energy to an electrosurgical probe with the proper characteristics, including fast switching times.

Abstract: A DC-coupled two-stage gate driver circuit for driving a junction field effect transistor (JFET) is provided. The JFET can be a wide bandgap junction field effect transistor (JFET) such as a SiC JFET. The driver includes a first turn-on circuit, a second turn-on circuit and a pull-down circuit. The driver is configured to accept an input pulse-width modulation (PWM) control signal and generate an output driver signal for driving the gate of the JFET.

Abstract: An output buffer is provided. The output buffer is coupled to a first voltage source providing a first supply voltage and used for generating an output signal at an output terminal according to an input signal. The output buffer includes first and second transistors and a self-bias circuit. The first and second transistors are cascaded between the output terminal and a reference voltage. The self-bias circuit is coupled to the output terminal and the control electrode of the first transistor. When the output buffer does not receive the first supply voltage, the self-bias circuit provides a first bias voltage to the control electrode of the first transistor according to the output signal to decrease voltage differences between the control electrode and the input and output electrodes of the first transistor to be lower than a predetermined voltage.

Abstract: An output driver configured to drive an output node includes a pull-down section having a plurality of legs and a pull-up section having a plurality of pull-up legs. Each leg and pull-up leg includes a data path and a calibration path. The data paths in the pull-down section are configured to conduct to ground responsive to an assertion of a complement data output signal whereas the data paths in the pull-up section are configured to conduct to a power supply node responsive to a de-assertion of the complement data output signal.

Abstract: An output driver circuit includes first, second, third, and fourth transistors having a common current path, wherein a gate of the first transistor receives a first switching signal, a gate of the second transistor receives a first reference voltage, a gate of the third transistor receives a second reference voltage, and a gate of the fourth transistor receives a second switching signal, and wherein a first capacitor is coupled between the gate of the first transistor and the gate of the third transistor, a second capacitor is coupled between the gate of the second transistor and the gate of the fourth transistor, and an output signal is provided at a node coupling the second and third transistors.

Abstract: A receiver circuit for a differential input signal, may include a divider bridge having first and second ends, a midpoint therebetween, and intermediate points on either side of the midpoint. The divider bridge is coupled to receive the differential input signal at the first and second ends. A current generator is coupled to the divider bridge and configured to generate compensation currents associated respectively with components of the differential input signal. The divider bridge is configured to receive the compensation currents respectively at the intermediate points, and generate a compensated differential signal between the intermediate points.

Abstract: An integrated circuit including a high-voltage n-channel MOS power transistor, a high-voltage n-channel MOS blocking transistor, a high-voltage n-channel MOS reference transistor, and a voltage comparator, configured to provide an overcurrent signal if drain current through the power transistor in the on state exceeds a predetermined value. The power transistor source node is grounded. The blocking transistor drain node is connected to the power transistor drain node. The blocking transistor source node is coupled to the comparator non-inverting input. The reference transistor drain node is fed by a current source and is connected to the comparator inverting input. The reference transistor gate node is coupled to a gate node of the power transistor. The comparator output provides the overcurrent signal. A process of operating the integrated circuit is disclosed.

Abstract: One or more resistors or resistances are integrated in a 7-bit DVR or PVCOM integrated circuit. 7-bit DVR or PVCOM integrated circuit includes a 7-bit DAC. The integrated resistors or resistances (R1, R2, or RSET, or any combination) reduces the number of external components, reduces the number of pins, increases the accuracy of the DVR or PVCOM circuit. The least significant bit (LSB) of the DAC depends only on ratios of internal resistors, which can be made very accurate and independent of temperature.

Abstract: A high-side semiconductor-switch driving method includes generating power for controlling a high side semiconductor switch. The high side semiconductor switch has a control terminal and the power allows a current to flow into the control terminal of the high side semiconductor switch to switch the high side semiconductor switch. The voltage at the control terminal of the high side semiconductor switch is quantified. The power dependent on the voltage at the control terminal of the high side semiconductor switch is controlled so that the current provided is increased when the voltage at the control terminal indicates that the current is not sufficient to switch the high side semiconductor switch.

Abstract: There is provided an apparatus for output buffering having a half-swing rail-to-rail structure. The apparatus provides output buffering by using a switch structure in order to attain a high slew rate and low power characteristics, thereby reducing current consumption. The provided apparatus for output buffering having a half-swing rail-to-rail structure includes a first output buffer, driven between a first voltage rail and a second voltage rail and outputting a first output signal in response to a first input signal and a second input signal, and a second output buffer, driven between the first and the second voltage rails and a third voltage rail and outputting a second output signal in response to a third input signal and a fourth input signal.

Abstract: A driver circuit for driving a power transistor includes a converter having a first transistor and a second transistor coupled in series between a supply node and a reference node. The converter is configured to receive a first signal and in response thereto generate a second signal for selectively controlling status of the power transistor. The ratio of a first leakage current of the first transistor to a second leakage current of the second transistor is used in the generation of the second signal which is applied to the control terminal of a transistor switch that is selectively actuated to turn off the power transistor.

Abstract: A semiconductor device with a current sampler and a start-up structure, comprises first, second and third high-voltage transistors, and a resistor, wherein: a drain terminal of the first transistor is respectively connected to a drain terminal of the second transistor, a drain terminal of the third transistor and one end of the resistor; a source terminal of the first transistor is grounded, and a gate terminal of the first transistor is connected to a gate terminal of the second transistor; the other end of the resistor is connected to a gate terminal of the third transistor; wherein the resistor is wound and formed in a common voltage withstand region of the first transistor, the second transistor and the third transistor, or in a voltage withstand region of the first transistor only, or in the voltage withstand region of the third transistor only.

Abstract: A driving circuit includes a common well. The driving circuit further includes a first output buffer having a bulk connected to the common well, the first output buffer having a first terminal configured to receive a first signal, and having a second terminal connected to the common well. The driving circuit further includes a second output buffer having a bulk connected to the common well, the second output buffer having a first terminal configured to receive the first signal, wherein a second terminal of the second output buffer is disconnected from the common well.

Abstract: An apparatus relating generally to a current steering cell includes a first bleeder circuit, a second bleeder circuit, a steering circuit, and an output circuit. The first bleeder circuit and the second bleeder circuit are coupled to receive a first current-source bias voltage. The steering circuit is coupled to receive a second current-source bias voltage independent from the first current-source bias voltage.

Abstract: The gate of a drive transistor having a drain and source is discharged by a circuit including a sensing circuit configured to sense a drain-to-source voltage of the drive transistor. A first current sink path is coupled to the gate of the drive transistor. The first current sink path applies a high discharge current to the gate of the drive transistor when the sensing current senses a lower drain-to-source voltage of the drive transistor. A second current sink path is also coupled to the gate of the drive transistor. The second current sink path is configured to apply a low discharge current to the gate of the drive transistor when the sensing current senses a higher drain-to-source voltage of the drive transistor.

Abstract: A quantizer takes an analog signal as input and produces a quantized signal for output. The quantizer includes a shoot-through current detection unit and a feedback unit. The shoot-through current detection unit is configured to detect a shoot-through current flowing through the quantizer. The feedback unit is configured to feed back a signal from the shoot-through current detection unit and control an electric charge stored at an input of the quantizer.

Abstract: A transmission line driver and a method for driving the same are provided, in which a composite current source is provided as an input current source, such that an output voltage is fixed. The composite current source includes an internal current source and an external current source. The composite current source is supplied to a single-ended transmission line driver or a differential transmission line driver, such that the output voltage is fixed.

Abstract: A semiconductor apparatus include a signal level switching decision unit and a transmitter unit. The signal level switching decision unit generates a switching control signal according to off-current of transistors included therein. The transmitter unit outputs a transmitter input signal as a transmitter output signal in response to a switching control signal.

Abstract: In accordance with an embodiment, a driver circuit includes a low-side driver having a first output configured to be coupled to a control node of a first semiconductor switch, and a reference input configured to be coupled to a reference node of the first semiconductor switch. The low-side driver also includes a first capacitor coupled between an output node of the first semiconductor switch and a first node, a first diode coupled between the first node and a first power input of the driver, and a second capacitor coupled between the first power input of the low-side driver and the reference node of the first semiconductor switch.

Abstract: A clock buffer circuit can include a low voltage drive circuit that receives a clock signal and provides a low voltage drive at a first power supply potential to a load. A boost drive circuit can provide a high voltage drive at a second power supply potential greater than the first power supply potential to the load. The boost drive circuit can provide the high voltage drive in response to a pulse signal generated in response to a transition of a clock input signal. A pulse generator circuit may generate the pulse signal to have a predetermined width to enable the high voltage drive until the load is charged essentially to the first power supply potential.

Abstract: The present invention is directed to prevent occurrence of a problem on a withstand voltage in a circuit group which receives supply of an internal power supply voltage. An error amplifier outputs a control voltage obtained by amplifying a difference voltage between a reference voltage and a divided voltage obtained by dividing an internal power supply voltage to an output node. A drive transistor supplies a drive current according to the control voltage of the output node of the error amplifier from an external power supply line to an internal power supply line. When the divided voltage exceeds a predetermined voltage, a clamp circuit changes the control voltage in the direction of decreasing the drive current.

Abstract: A control voltage is generated at a control input of a semiconductor circuit breaker by an actuation circuit at switching flanks of a switching signal, said control voltage having a profile which is flattened in relation to the profile of the switching signal. With the disclosed method, the switching losses in a semiconductor circuit breaker are reduced. By defining a value for a switching parameter of a control device of the actuation circuit, the switching behavior of the actuation circuit can be influenced by the switching parameter. A specific parameter value of the switching parameter can be varied during operation of the actuation circuit.

Abstract: A high side driver circuit includes a driver stage having an input, an output, a first power terminal and a second power terminal, a transistor having a first power terminal, a second power terminal, and a control terminal coupled to the output of the driver stage, and a switch coupled between the second power terminal of the driver stage and the second power terminal of the transistor.

Abstract: Methods and circuits for providing a minimum driving voltage to a current-driven load (such as a laser diode) are disclosed. The circuit and methods may be useful for efficiently providing a bias and/or driving current to the current-driven load with minimal energy loss. The circuit generally comprises (1) a driver or voltage source configured to provide the bias and/or driving current to the current-driven load, (2) a sense circuit configured to (i) sense the bias and/or driving current and (ii) convert the bias and/or driving current to a first voltage, and (3) a comparator configured to (i) receive the first voltage and first and second reference voltages and (ii) provide a feedback/error signal to the driver or voltage source, the feedback/error signal configured to maintain or adjust the bias and/or driving current at or towards a target value.

Abstract: Provided is a method for driving a semiconductor device, which allows a reduction in scale of a circuit, reduce the power consumption, and increase the speed of reading data. An H level (data “1”) potential or an L level (data “0”) potential is written to a node of a memory cell. Potentials of a source line and a bit line are set to the same potential at an M level (L level<M level<H level) so that the potential of the node is held. When the potential of the bit line is maintained at the M level, data “1” is read and when the potential of the bit line is reduced to an L level, data “0” is read.

Abstract: The invention provides a semiconductor device which performs a write operation of a signal current rapidly to a current input type pixel. Before inputting a signal current, a precharge operation is performed by flowing a large current. After that, a signal current is inputted to perform the set operation. A predetermined potential can be obtained rapidly as the precharge operation is performed before the set operation. The predetermined potential is approximately equal to a potential after completing the set operation. Therefore, the set operation can be rapidly performed and a write operation of a signal current can be rapidly performed. By using two transistors, a gate width W can be long or a gate length L can be short in the precharge operation or the gate width W can be short and the gate length L can be long in the set operation.

Abstract: A circuit having a centralized PT compensation circuit to provide compensation signals to localized I/O blocks on the chip. Process variations and temperature variations tend to be approximately uniform across an integrated circuit chip. Thus, a single, centralized PT compensation circuit may be used instead of one PT compensation circuit per I/O section as with solutions of the past. Further, the PT compensation circuit may generate a digital code indicative of the effects of process and temperature. Further yet, each section of I/O block may have a local voltage compensation circuit to compensate the voltage variation of the I/O block. The voltage compensation circuit utilizes an independent reference voltage. The reference voltage is generated by the PT compensation circuit, which is placed centrally in the IC chip and hence any need to repeat the reference generation for each I/O block is eliminated.

Abstract: A two-stage post driver circuit includes a controlling circuit, a pull-up unit and a pull-down unit. A first N-type transistor of the pull-down unit and a first P-type transistor of the pull-up unit are both connected to an output pad. The controlling circuit is used for controlling the first N-type transistor and the first P-type transistor. Consequently, when the pull-up unit or the pull-down unit is turned on, the voltage difference between the drain terminal and the source terminal of the first N-type transistor or the first P-type transistor is lower than a voltage stress.

Abstract: An internal voltage generation circuit including a voltage generator and a detection voltage generator. The voltage generator generates a temperature reference voltage signal whose level depends on an internal temperature, a division reference voltage signal whose level is constant regardless of the internal temperature, and a selection reference voltage signal obtained by detecting a level of an internal voltage signal. The detection voltage generator compares the division reference voltage signal and the selection reference voltage signal in response to the temperature reference voltage signal to generate a detection voltage signal controlling a pumping operation of the internal voltage signal.

Abstract: Disclosed herein is a gate driver. The gate driver according to an exemplary embodiment of the present invention includes: a first power switch sourcing current according to voltage applied by a voltage source; a second power switch connected with the first power switch in series and sinking current according to the voltage applied by the voltage source; and a speed booster receiving a voltage pulse from the outside to output peak current so as to make a turn on/off operation of the first power switch fast. As set forth above, according to the exemplary embodiments of the present invention, it is possible to improve the driving speed of the gate driver without increasing the current of the current source by further including the speed booster configured of the plurality of MOSFETs and the capacitor.

Abstract: A circuit structure (200) for suppressing single event transients (SETs) or glitches in digital electronic circuits is provided. The circuit structure includes a first input (100) which receives an output of a digital electronic circuit (A), a second input (100?) which receives a redundant or duplicated output of the digital electronic circuit (A?), and two sub-circuits (102, 106) that each receive the inputs and have one output. One of the sub-circuits is insensitive to a change in the value of one of its inputs when the inputs are in a first logic state and the other sub-circuit is insensitive to a change in the value of one of the inputs when the inputs are in a second, inverted logic state. The sub-circuit outputs are input into a two-input multiplexer (202) which has its output (204) connected to its selection port (SEL), and the sub-circuits are arranged so that the sub-circuit which is insensitive to a change in the value of one of its inputs is selected whenever the output of the multiplexer changes.

Abstract: Input-output (IO) buffer circuitry is provided that is operable to drive signals off an integrated circuit. The input-output circuitry may include an input-output driver having an asymmetric transistor and/or a low-threshold voltage transistor. The asymmetric transistor may include a first source-drain region at a first dopant concentration level and a second source-drain region at a second dopant concentration level. The first dopant concentration level and the second dopant concentration level may be different. The IO buffer circuitry may be able to prevent issues with regards to hot carrier injection when driving signals with elevated voltages. The IO buffer circuit may also be manufactured without increasing the overall cost.