Abstract: The invention provides a scan driving circuit for an oxide semiconductor thin film transistor. The scan driving circuit for an oxide semiconductor thin film transistor includes multiple cascade connected GOA units and a shared auxiliary inverter. Each of the GOA units includes a main inverter. The auxiliary inverter is electrically connected to each main inverter to form corresponding pull-down holding parts for the respective GOA units, which can achieve the sharing of the pull-down holding parts of the multiple stages GOA units, the number of TFT elements can be reduced and therefore GOA layout space as well as circuit power consumption can be reduced.

Abstract: A voltage mode transmitter is provided. The voltage mode transmitter includes a control unit and a resistor ladder circuit. The control unit receives a first signal and delays an inverse of the first signal for a time period to obtain a second signal. The resistor ladder circuit is configured to sum up products of the first signal or the second signal and a plurality of weights, thereby generating an output signal. The resistor ladder circuit includes an input terminal, multiple first resistors and a second resistor. The output terminal is configured to output the output signal. Each of the first resistors is coupled between the output terminal and the control unit and receives the first signal or the second signal. The resistances of the first resistors are 2R, 4R . . . and 2nR respectively, where R is a reference resistance. The resistance of the second resistor is 2nR.

Abstract: Driver circuitry for switching systems comprising enhancement mode (E-Mode) GaN power transistors with low threshold voltage is disclosed. An E-Mode high electron mobility transistor (HEMT) D3 has a monolithically integrated GaN driver, comprising smaller E-Mode GaN HEMTs D1 and D2, and a discrete dual-voltage pre-driver. In operation, D1 provides the gate drive voltage to the gate of the GaN switch D3, and D2 clamps the gate of the GaN switch D3 to the source, via an internal source-sense connection closely coupling the source of D3 and the source of D2. An additional source-sense connection is provided for the pre-driver. Boosting the drive voltage to the gate of D1 produces firm and rapid pull-up of D1 and D3 for improved switching performance at higher switching speeds. High current handling components of the driver circuitry are integrated with the GaN switch and closely coupled to reduce inductance, while the discrete pre-driver can be thermally separated from the GaN chip.

Abstract: A stage circuit includes a first driver, a second driver, a first output unit, a second output unit and a controller. The first driver controls voltages of first and second nodes, according to a first power source, a third power source, a start signal or a carry signal of a previous stage input to a first input terminal, and a clock signal supplied to a second input terminal. The second driver controls voltages of third and fourth nodes, according to voltages of the first power source, the third power source, the first input terminal and the first and second nodes. The first output unit outputs a carry signal to a first output terminal, according to voltages of the first power source, the second input terminal and the third and fourth nodes. The second output unit outputs a scan signal to a second output terminal, according to voltages of the second power source, the second input terminal and the third and fourth nodes. The controller is electrically coupled to the first output terminal and the second driver.

Abstract: Provided is a DC/DC converter for a multi-phase switching power supply device which include a plurality of DC/DC converters including a master DC/DC converter and a plurality of slave DC/DC converters that are connected in parallel to each other and operate in different phases. The DC/DC converter includes: first and second terminals to cascade the plurality of DC/DC converters in a line; a phase detector that detects the number of operating converters in the switching power supply device and the phases of the plurality of DC/DC converters, on the basis of a current input to the first terminal and a current output from the second terminal; a phase holder that holds the detected phases and outputs a phase holding signal; and a clock generator that selects a clock corresponding to the phase of a host converter from multi-phase clocks, on the basis of the phase holding signal, and outputs the selected clock. The DC/DC converter performs a switching operation on the basis of the selected clock.

Abstract: A dual mode serial transmission apparatus and method for switching a mode thereof are provided. The dual mode serial transmission apparatus includes a first and second current sources, a first and second inverting circuits, a differential pair and a resistor string. The first inverting circuit receives a mode selecting signal or a first data transmission signal, the second inverting circuit receives the mode selecting signal or a second data transmission signal. First and second load terminals of the differential pair are respectively coupled to the first and second inverting circuits. A common terminal of the differential pair is coupled to the second current source. First and second differential input terminals receive the mode selecting signal or respectively receive the first and second data transmission signals. The resistor string is coupled in series between output terminals of the first and second inverting circuits.

Abstract: The present invention relates in one aspect to a DC linear voltage regulator circuit for generating a regulated DC output voltage based on a DC input voltage. The DC linear voltage regulator circuit comprises a DMOS pass transistor comprising drain, gate, source and bulk terminals wherein the drain terminal is connected to a regulator output which is configured to supply the regulated DC output voltage and the source terminal is connected to a regulator input for receipt of the DC input voltage. The DC linear voltage regulator circuit comprises a switchable leakage prevention circuit, connected to the bulk terminal of the DMOS pass transistor, and configured to automatically detect and interrupt a flow of leakage current from the regulator output to the bulk terminal.

Abstract: The present technology relates to a driving circuit and a driving method, in which power loss at the time of switching an FET (Field Effect Transistor) can be reduced with a simple circuit configuration. A coil constitutes a resonance circuit together with an input capacitance at a gate of the FET. A switch (regeneration switch) turns on or off current flowing in the coil. A DC power source is a power source to replenish the resonance circuit with electric charge and is connected to the gate of the FET. A switch (replenish switch) turns on or off connection between the DC power source and the gate of the FET. The present technology is applicable to, for example, a power source that outputs AC voltage and current by switching operation.

Abstract: A power bank device includes a load node, a power-supply circuit, an output circuit, a detecting unit, and a control circuit. The power-supply circuit provides an output current via the load node. The output circuit generates an output voltage at the load node according to the output current. The detecting unit generates a detecting signal according to the output current. The output circuit includes an impedance circuit. The control circuit, according to the detecting signal, controls the output circuit to switch an impedance of the impedance circuit, thereby down-regulating the output voltage and the output current.

Abstract: An example embodiment discloses a flip-flop including a first inverter configured to invert first data, first and second transistors connected to each other in series and configured to receive the inverted first data and a first clock, respectively, a third transistor and a first gate configured to perform a logic operation on the first data and the first clock, the third transistor configured to receive an output of the logic operation. The second transistor and the third transistor are connected to a first node.

Abstract: A gate potential control circuit includes a driving switching element, a first gate potential supply part, a first switching element, a first resistor, and a first operational amplifier. The first operational amplifier includes an output portion connected to a gate of the first switching element, an inverting input into which a first reference potential is input, and a non-inverting input into which a closer one of a first value and a second value to a potential of the first gate potential supply part is input. The first value is based on a potential difference obtained by subtracting a potential of a terminal of the first resistor on a driving switching element side from a potential of a terminal of the first resistor on a first gate potential supply part side. The second value is based on a potential of a terminal of the first switching element.

Abstract: A drive device that drives a semiconductor switching device includes a capacitor, an output selection unit that selects whether or not to supply a charge of the capacitor to a conduction control terminal of the semiconductor switching device, and a charge consumption unit that supplies the charge of the capacitor to a portion other than the conduction control terminal, thereby consuming the charge of the capacitor.

Abstract: A driver circuit has a gate drive terminal that produces a gate drive signal to control paralleled power semiconductor switches, such as GaN high electron mobility transistor (HEMT) devices. One of the switches is closest to the gate drive terminal such that its gate drive loop inductance is smaller than the remaining switches that are farther away having a larger loop inductance. An additional resistor or gate-source capacitor is provided in the gate drive circuit of the closest switch which increases the total gate resistance of the closest switch compared to the remaining switches, which delays the turn off time of the closest switch. The delay permits zero voltage switching turn-off of the remaining switches to reduce noise. The closest switch is hard switched off but has the smallest loop inductance, which allows optimized turn off.

Abstract: An integrated circuit includes an internal circuit including a input/output unit suitable for inputting/outputting data, and a voltage supplying circuit suitable for supplying a first operating voltage to the internal circuit in response to a first control signal during a general operation, and supplying a second operating voltage that is higher than the first operating voltage to the input/output unit in response to a second control signal during an output of the data.

Abstract: An apparatus comprises a bridge coupled between a bias voltage and ground, wherein the bridge comprises a first switch and a second switch connected in series and coupled between the bias voltage and ground and a third switch and a fourth switch connected in series and coupled between the bias voltage and ground, a resonant device coupled to the bridge, wherein the resonant device comprises a fixed capacitance, a gate capacitance and a magnetizing inductance, a transformer coupled to the resonant device, wherein the transformer comprises a primary winding and a plurality of secondary windings.

Abstract: In one embodiment, a load detection circuit may include a first circuit configured to control a first transistor to form a load current to a load in a first operating mode of the load detection circuit, a second circuit configured to be coupled to form at least a portion of the load current in a second operating mode of the load detection circuit, and a detection circuit configured to detect the control electrode of the first transistor having a value that is less than a threshold value of the first transistor.

Abstract: Aspects of the present invention provides a device that is capable of accurately measuring an output current of a transistor, controls the drive of a switching element, by using an existing IC tester without any evaluation board improvement. The control device according to one aspect of the present invention has: a drive circuit, a plurality of transistors for controlling the drive of a switching element and a transistor operation controller. A transistor for turning the switching element OFF is configured by a plurality of transistors. The transistor operation controller, in a normal operation, performs ON/OFF control on the two transistors simultaneously or collectively by means of the same drive signal output from the drive circuit. In a test operation, the transistor operation controller sequentially selects one of the transistors and supplies the same drive signal to the selected transistor, to drive the transistors individually.

Abstract: The present disclosure provides a device and method for automatically detecting an LVDS interface matching resistor. In the device, multiple detection interface units each including two terminals for being connected with two ends of the LVDS interface matching resistor, are set; at least one switch unit is connected between corresponding detection interface unit and a processing unit and the switch unit and the detection interface unit are set correspondingly; and a processing unit is used for controlling the switch unit to be in the conducting state, so that the detection interface unit corresponding to the switch unit in the conducting state and the processing unit form a detection loop, and by use of the detection loop, the processing unit performs measurement to the LVDS interface matching resistor connected to the detection interface unit corresponding to the switch unit in the conducting state.

Abstract: An electrical circuit includes monolithic integrated circuit (IC) switch devices that are connected in parallel. A monolithic IC switch device includes a first pin, a second pin, and a power switch that connects the first pin to the second pin through the power switch when the electrical circuit is turned ON. The monolithic IC switch device includes a current balancing circuit that controls the power switch to reduce an output current of the monolithic IC switch device when the output current of the monolithic IC switch device increases above the average of the output currents of monolithic IC switch devices in the electrical circuit.

Abstract: Disclosed is a buck converter for converting a high voltage at the input of the buck converter to a low voltage at the output of the buck converter. The buck converter includes a control circuitry configured to control a duty cycle of a control switch, the control switch being interposed between the input and the output of the buck converter. A synchronous switch is interposed between the output and ground. The control switch and the synchronous switch comprise depletion-mode III-nitride transistors. In one embodiment, at least one of the control switch and the synchronous switches comprises a depletion-mode GaN HEMT. The buck converter further includes protection circuitry configured to disable current conduction through the control switch while the control circuitry is not powered up.

Abstract: A circuit for a semiconductor switching element including a transformer. One embodiment provides a first voltage supply circuit having a first oscillator. A first transformer is connected downstream of the first oscillator. A first accumulation circuit for providing a first supply voltage is connected downstream of the first transformer. A driver circuit having input terminals for feeding in the first supply voltage and having output terminals for providing a drive voltage for the semiconductor switching element, designed to generate the drive voltage for the semiconductor switching element at least from the first supply voltage.

Abstract: A semiconductor integrated circuit device that has a high-voltage analog switch circuit and is operable at a low power-supply voltage, and which has a first high-voltage MOSFET HN1, a second high-voltage MOSFET, and a first floating gate voltage control circuit. The first floating gate voltage control circuit operates at a voltage of 5 V or lower, and when turning on the first high-voltage MOSFET and the second high-voltage MOSFET, the first floating gate voltage control circuit sets a voltage in the source terminal of the first high-voltage MOSFET as a reference voltage, adds a floating voltage corresponding to the power-supply voltage to the reference voltage, and supplies the added voltage to the gate terminals of the first high-voltage MOSFET and the second high-voltage MOSFET.

Abstract: A current comparator may include a current comparison block configured to compare current flowing through first and second input terminals; a first current control unit configured to control current flowing through the first input terminal in response to a voltage of a first node; a second current control unit configured to control current flowing through the second input terminal in response to a voltage of a second node; a first driving unit configured to drive the first node with a first voltage higher than a read voltage in a non-comparison period, and drive the first node with the read voltage in a comparison period; and a second driving unit configured to drive the second node with a second voltage higher than a reference voltage in the non-comparison period, and drive the second node with the reference voltage in the comparison period.

Abstract: A transmission channel transmits high-voltage pulses and receives echos of the high-voltage pulses. The transmission channel includes a buffer with anti-memory circuitry to couple drains of the buffer transistors to voltage reference terminals during a clamping phase.

Abstract: A voltage clamping system includes: (a) a first electronic device connected to a first power source and having a signal output node, a voltage clamp high node, and a voltage clamp low node, wherein the voltage clamp high node and the voltage clamp low node are coupled to a second power source different than the first power source; and (b) a second electronic device powered by the second power source and having a signal input node coupled to the signal output node of the first electronic device. The signal output node of the first electronic device is passively clamped, with low distortion, approximately rail-to-rail with respect to the second power source such that the second electronic device is protected from damage due to excessive voltage levels.

Abstract: A power circuit for reducing a leakage power using a negative voltage is provided. The power circuit includes a current source including a transistor including a gate. The power circuit further includes a current source control circuit connected to the gate of the transistor, and configured to apply a positive voltage to the gate of the transistor if the current source is to operate in an active mode, and apply the negative voltage to the gate of the transistor if the current source is to operate in an inactive mode.

Abstract: A driver circuit for driving a switching transistor having a control terminal responsive to a switching control signal includes a plurality of driver stages, each having a control input responsive to a respective driver control signal and an output coupled to the output of the other driver stages and to the control terminal of the switching transistor. At least one of the driver control signals has an on time that is delayed with respect to the other driver control signals. In an embodiment, at least two driver stages are on during a slew time interval.

Abstract: A charge pump circuit is disclosed. The charge pump circuit includes a first circuit powered by a first supply voltage and configured to adjust a voltage of an output in response to first and second sets of control signals. The first circuit includes a set of transistors having respective switching voltages. A control circuit powered by a second voltage, less than the first supply voltage, is configured to generate the first and second sets of control signals. A voltage shifting circuit is configured to bias voltages of the first and second sets of control signals relative to the switching voltages.

Abstract: In a driving system for driving a switching element, a controller controls the switching element. A temperature measuring module measures a temperature of the switching element, and output a first signal representing the measured temperature of the switching element as first information. A state determining module determines whether the switching element is in a specified temperature state based on the first signal, and outputs a second signal representing a result of the determination as second information. A communication medium communicably connects between the controller and the state determining module, and the second signal output from the state determining module being transferred to the controller via the communication medium. The controller determines how to drive the switching element based on the second information in the second signal transferred thereto via the communication medium.

Abstract: A circuit comprises a voltage supply node, a reference voltage node, and a plurality of transistors coupled with the voltage supply node and the reference voltage node. The circuit also comprises a circuit input, a first delay element and a second delay element. The first delay element is coupled with the circuit input and one transistor of the plurality of transistors. The second delay element is coupled with the circuit input and a second transistor of the plurality of transistors. The circuit further comprises a circuit output coupled with the first transistor of the plurality of transistors and the second transistor of the plurality of transistors. The circuit additionally comprises a bias generator coupled with the circuit output, the first transistor of the plurality of transistors and the second transistor of the plurality of transistors.

Abstract: A system may include a plurality of units, wherein each unit has a respective common mode voltage terminal, communication up terminal, and communication down terminal. A first unit of the plurality of units may be configured to generate a first plurality of currents on its communication up terminal, wherein the first plurality of currents corresponds to a first plurality of bits. A second unit of the plurality of units may be configured to receive the first plurality of currents on its respective communication down terminal, and maintain a voltage level at its respective communication down terminal during reception of the first plurality of currents. The voltage level may be equal to a common mode voltage of the respective common mode voltage terminal of the second unit.

Abstract: A gate driving circuit is provided which includes a plurality of stages cascade-connected with each other and outputting a plurality of gate signals. An n-th (n is a natural number) stage includes a gate output part, a first node control part and a carry part. The gate output part includes a first transistor. The first transistor outputs a high voltage of a clock signal to a high voltage of an n-th gate signal in response to a high voltage of a control node. The first node control part is connected to the control node to control a signal of the control node and includes at least one transistor having a channel longer than the channel length of the first transistor. The carry part outputs the high voltage of the clock signal to an n-th carry signal in response to the signal of the control node.

Abstract: Embodiments of the invention are generally directed to elements to counter transmitter circuit performance limitations. An embodiment of an apparatus for driving data on a differential channel including a first output terminal and a second output terminal includes a differential driver circuit; and a first pre-driver and a second pre-driver, where each pre-driver has an output, wherein the first output terminal of the apparatus is coupled to the output of the first pre-driver, and the second output terminal of the apparatus is coupled to the output of the second pre-driver, where each pre-driver includes one or more capacitors, a first end of each capacitor being connected to the output of the pre-driver and a second end of each of the capacitors being connected to a sub-pre-driver circuit.

Abstract: An low voltage differential signaling (LVDS) driver is provide having an output voltage amplitude regulator for regulating an output voltage amplitude of the LVDS driver by receiving a differential output signal from a switched-polarity current generator of the LVDS driver at an output voltage amplitude regulator of the LVDS driver, detecting an output voltage amplitude of the differential output signal, comparing the output voltage amplitude to a reference voltage at the output voltage amplitude regulator and regulating a steering current of the LVDS driver based upon the comparison between the output voltage amplitude and the reference voltage to regulate an amplitude of the differential output signal at one or more loads of the LVDS driver.

Abstract: This application discusses, among other things, an interpolator architecture for digital-to-time converters (DTCs). In an example, an interpolator can include interpolation cells and retention cells configured provide an interpolated output based on at least two offset clock signals. In certain examples, an example interpolator can provide contention free control of the interpolator output with improved noise immunity.

Abstract: A communication system includes a continuous-time linear equalizer in the clock forward path. The equalizer may be adjusted to minimize clock jitter, including jitter associated with the first few clock edges after the clock signal is enabled. Reducing early-edge jitter reduces the power and circuit complexity otherwise needed to turn the system on quickly.

Abstract: A transmitter module having a plurality of semiconductor laser diodes (LDs) as optical signal sources that emit optical respective optical beams with specific wavelengths different from other is disclosed. The transmitter module includes, in addition to the LDs, a driver to drive LDs in the shunt-driving configuration. Inductors through which the bias currents for the LDs are provided are mounted on the driver as interposing a spacer and a top carrier.

Abstract: A high voltage bootstrap gate driving apparatus is provided. The gate driving apparatus includes a high-end transistor, a low-end transistor, a buffer, a boost capacitor, and a high voltage depletion transistor. The high-end transistor receives a first power voltage. The buffer provides a high-end driving signal to the high-end transistor according to a bias voltage. The boost capacitor is serial coupled between a base voltage and a bias voltage. A first end of the depletion transistor is coupled to a second power voltage, a second end of the depletion transistor is coupled to the bias voltage, and a control end of the depletion transistor receives the reference ground voltage.

Abstract: A driver circuit for driving a switch includes a high output impedance driver circuit portion having a high impedance output node coupled to the control terminal of the transistor and a low output impedance driver circuit portion having a low impedance output node also coupled to the control terminal of the transistor. The slew rate of the control signal is established by at least one of the high impedance driver circuit portion and the low impedance driver circuit portion.

Abstract: A signaling bus having a plurality of adjacent logical lanes, each logical lane having an odd signal path and an even signal path. Driving circuitry drives each logical lane by transmitting, if data has changed from an immediately preceding cycle, a one cycle signal having a first transition direction on the even signal path on even cycles and transmitting a one cycle signal having the first transition direction on odd cycles. If data has not changed, transmitting a two cycle signal having a second transition direction on the even signal path on even cycles and transmitting a two cycle signal on the odd path having the second transition direction on odd cycles. Receiver circuitry alternates selection of the even cycle path and the odd cycle path to determine if data has changed from the immediately preceding cycle.

Abstract: An LVDS (Low Voltage Differential Signaling) driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, a second resistor, and a bias driver. The first transistor is coupled between a supply voltage and a first node. The second transistor is coupled between the supply voltage and a second node. The third transistor is coupled between the first node and a ground voltage. The fourth transistor is coupled between the second node and the ground voltage. The first resistor is coupled between the first node and a third node. The second resistor is coupled between the second node and the third node. The bias driver generates bias signals for controlling the first, second, third, and fourth transistors according to a data signal.

Abstract: A low voltage differential signaling generating circuit, which comprises a current source a pair of output nodes for providing a differential signal by virtue of a voltage difference therebetween, first and second differential switch circuitries and a bypass circuitry. The first differential switch circuitry selectively connects the current source to the first output node based on a control signal to cause a current flow from the first output node to the second one. The second differential switch circuitry selectively connects the current source to the second output node based on the control signal to cause a current flow from the second output node to the first one. The bypass circuitry is arranged in parallel to the first and second differential switch circuitries and is selectively switched based on an idle mode signal to prevent a current between the output nodes.

Abstract: A data output circuit of a semiconductor apparatus includes a pull-up driver electrically coupled between a power supply terminal and an output terminal, and configured to drive the output terminal in response to pull-up control signals. The data output circuit may also include a pull-down driver electrically coupled between the output terminal and a ground terminal, and configured to drive the output terminal in response to pull-down control signals. Further, the data output circuit may include a compensation unit configured to open a current path between the output terminal and the ground terminal during an operation period of the pull-up driver, and allow leakage current of the pull-up driver to flow through the current path.

Abstract: A data output circuit of a semiconductor apparatus is provided. The data output circuit may include a pull-up driver including a plurality of leg units configured to provide respective resistance values which are selected based on code signals, provide a total resistance value which is selected in response to one or more of the plurality of leg units being selectively activated based on selection signals, and configured to apply an output voltage with an output voltage level selected according to the selection of the total resistance value among a plurality of output voltage levels, to a data output pad. The data output circuit may include a control block configured to generate the selection signals in response to mode register signals. The data output circuit may include a code generator configured to generate the code signals based on a comparison of a reference voltage to a replica output voltage which varies according to an external resistance.

Abstract: A drive circuit includes a constant current circuit which supplies a constant current to the gate of an IGBT and on-operates the IGBT; a discharge circuit which grounds the gate of the IGBT and off-operates the IGBT; and a switch circuit which operates one of the constant current circuit or discharge circuit in accordance with a control signal and turns on or off the IGBT. In particular, the drive circuit includes a current detection circuit which detects a current flowing through the IGBT when the IGBT is turned on; and a current regulation circuit which feeds the current detected by the current detection circuit back to the constant current circuit and controls an output current of the constant current circuit in accordance with the turn-on characteristics of the IGBT.

Abstract: The present technology relates to a driving circuit and a driving method, in which power loss at the time of switching an FET (Field Effect Transistor) can be reduced with a simple circuit configuration. A coil constitutes a resonance circuit together with an input capacitance at a gate of the FET. A switch (regeneration switch) turns on or off current flowing in the coil. A DC power source is a power source to replenish the resonance circuit with electric charge and is connected to the gate of the FET. A switch (replenish switch) turns on or off connection between the DC power source and the gate of the FET. The present technology is applicable to, for example, a power source that outputs AC voltage and current by switching operation.

Abstract: A method and apparatus are provided for equalizing an output of a level shifter so as to obtain a symmetrical transition. In one implementation, a transition equalizing inverter includes: an NMOS for establishing a high-to-low transition for an equalized signal in response to a low-to-high transition of an asymmetrical signal; a delay circuit for outputting a delayed signal in response to the asymmetrical signal; and a PMOS for establishing a low-to-high transition for the equalized signal in response to a high-to-low transition of the delayed signal, wherein a delay introduced by the delay circuit offsets a timing mismatch between a low-to-high transition and a high-to-low transition of the asymmetrical signal. In an embodiment, the delay circuit comprises a transmission gate. A corresponding method is also provided.

Abstract: A transmitting circuit includes a positive differential node, a negative differential node, a voltage mode driver, and a current mode driver. The voltage mode driver generates a first positive differential signal and a first negative differential signal. The voltage mode driver provides the first positive differential signal to the positive differential node and provides the first negative differential signal to the negative differential node. The current mode driver generates a second positive differential signal and a second negative differential signal. The current mode driver provides the second positive differential signal to the positive differential node and provides the second negative differential signal to the negative differential node. A differential signal voltage swing width between the positive differential node and the negative differential node is based at least on the operational state of the current mode driver and/or the voltage mode driver.

Abstract: The embodiments of the present invention provide a output buffer circuit, comprising: a first stage operational amplifying circuit configured as a differential input circuit; a second stage operational amplifying circuit configured as a common source amplifying circuit having an active load; and a feedback circuit provided between the first stage operational amplifying circuit and the second stage operational amplifying circuit and configured to have driving capability of providing source current and sink current alternately. By forming a unit gain amplifier comprising the first stage operational amplifying circuit, the second stage operational amplifying circuit and the feedback circuit connected therebetween, the output buffer circuit has the driving capability of providing source current and sink current alternately.

Abstract: A memory macro includes a first data line, a second data line, a first switch and a voltage keeper. The first switch is configured between the first data line and the second data line. The voltage keeper is electrically coupled to the second data line. The voltage keeper is configured to control a voltage level at the second data line in response to the voltage level at the second data line during the first switch electrically couples the second data line to the first data line.