Abstract: Direct-path current is reduced in a semiconductor device including CMOS circuits. One embodiment of the present invention is a method for driving a semiconductor device that includes a first CMOS circuit between power supply lines, a first transistor between the power supply lines, a second CMOS circuit between the power supply lines, and a second transistor between an output terminal of the first CMOS circuit and an input terminal of the second CMOS circuit. The first transistor and the second transistor each have lower off-state current than a transistor included in the first CMOS circuit. In a period during which the voltage of a first signal input to the first CMOS circuit is changed, a second signal is input to the first transistor and the second transistor to turn off the first transistor and the second transistor.

Abstract: A circuit includes a first input transistor and a first voltage divider coupled to a source of the first input transistor and a second input transistor and a second voltage divider coupled to a source of the second input transistor. A first set of series connected transistors include a first transistor with a gate coupled to the first input transistor source and a second transistor with a gate coupled to a tap of the first voltage divider. A second set of series connected transistors include a third transistor with a gate coupled to the second input transistor source and a fourth transistor with a gate coupled to a tap of the second voltage divider. An output is coupled to the sources of the first and second input transistors. The first and second sets are coupled to one of the first input transistor drain or second input transistor drain.

Abstract: An isolation receiver includes at least one isolation capacitor to provide a first logic signal in response to a second logic signal that is provided by a transmitter. The receiver includes a signal processing circuit to amplify the first logic signal to generate an amplified signal, and the signal processing circuit includes a an amplifier to apply a nonlinear function. A comparator of the receiver provides a third logic signal in response to the amplified signal.

Abstract: Various aspects of the disclosure are directed to methods and apparatuses involving communications. As consistent with one or more embodiments, first and second sets of multiple current drivers are implemented respectively in a high-side and a low-side circuit. Current is driven via an output port in the high-side circuit by activating the first set of multiple current drivers until a steady-state high voltage is detected, and by deactivating one of the current drivers in the first set when the steady-state high voltage is detected. Current is driven in the low-side circuit by activating the second set of multiple current drivers until a steady-state low voltage is detected, and by deactivating one of the current drivers in the second set when the steady-state low voltage is detected.

Abstract: Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

Abstract: In accordance with embodiments of the present disclosure, systems and methods may include a switch coupled at its gate terminal to an input signal voltage, the input signal voltage for controlling a gate voltage of a gate terminal of a driver device coupled at its non-gate terminals between a rail voltage and an output node. The systems and methods may also include a diode having a first terminal and a second terminal, the diode coupled to a non-gate terminal of the switch such that when the switch is enabled, the first terminal is electrically coupled to the gate terminal of the driver device and the second terminal is electrically coupled to the output node.

Abstract: An electronic circuit for driving an electronic switch includes a first voltage terminal coupled to receive a first voltage from a power supply and a second voltage terminal coupled to receive a second voltage from the power supply. A driver circuit is configured to drive the voltage at a control terminal of the electronic switch to an intermediate voltage level in order to turn on the electronic switch during a high or normal voltage condition. A clamp circuit is configured to clamp the voltage at the control terminal of the electronic switch to the second voltage terminal in order to turn on the electronic switch during a low voltage condition, so that the electronic switch can enhance power provided to a load during the low voltage condition. A low voltage detection circuit detects the low voltage condition and provides a signal to activate the clamp circuit.

Abstract: Aspects of the invention include a constant current source that generates a constant current, apart from a constant current circuit, and a temperature detection zener diode (a temperature detection element). The input side of the constant current source can be connected to a power source. The output side of the constant current source can be connected to the anode of the temperature detection diode. The anode of the temperature detection zener diode can also be connected to one end of a resistor provided in the constant current circuit. Further, the cathode of the temperature detection zener diode can be connected to a GND. Further, the temperature detection zener diode can be incorporated in the same semiconductor substrate as a semiconductor substrate into which an IGBT is built.

Abstract: Methods and apparatuses are disclosed for transmitter circuits. One example apparatus includes a pre-driver circuit configured to provide a transition control signal responsive to received data, and a main driver circuit configured to drive an output node responsive to the transition control signal. The apparatus also includes a feedback circuit configured to provide a feedback control signal responsive to a voltage of the output node reaching or exceeding a predefined threshold, and an equalizer driver circuit configured to assist the main driver circuit in driving the output node responsive to signals from at least one of the pre-driver circuit and the feedback circuit.

Abstract: The present invention relates to a high voltage switch circuit, comprising an input port adapted to receive a pulse type input current and an output port, which can be used selectively to conduct an output current to a corresponding electrical load. The switch circuit comprises a buffer stage adapted to sense the input voltage at said input port and to provide a buffered voltage that follows said input voltage. The switch circuit comprises complementary switches electrically connected between said input port and said output port and a voltage level translator electrically connected with said switches, said buffer stage and a control terminal that provides a control signal. The voltage level translator provides suitable gate voltages at the gate terminals of said switches, so that the operation of these latter can be controlled by said control signal.

Abstract: An exemplary apparatus and method for using intelligent gate driver units with distributed intelligence to control antiparallel power modules or parallel-connected electrical switching devices like IGBTs is disclosed. The intelligent gate drive units use the intelligence to balance the currents of the switching devices, even in dynamic switching events. The intelligent gate driver units can use master-slave or daisy chain control structures and instantaneous or time integral differences of the currents of parallel-connected switching devices as control parameters. Instead of balancing the currents, temperature can also be balanced with the intelligent gate driver units.

Abstract: A current mirror circuit is described. The current mirror circuit includes a first transistor and a second transistor. The gates of the first transistor and the second transistor are coupled at a bias voltage. The current mirror circuit also includes an auxiliary transistor that is biased into weak inversion by receiving the bias voltage at a gate of the auxiliary transistor after being reduced by an offset voltage. The sources of the first transistor, second transistor and auxiliary transistor are coupled together. A primary current from the drain of the second transistor is combined with an auxiliary current from the drain of the auxiliary transistor to produce an output current.

Abstract: An aspect of the present invention includes a circuit having a cascaded H-bridge, an upper voltage supply component, a lower voltage supply component and a pre-driver component. The cascoded H-bridge is arranged to provide a driving signal for driving a load. The upper voltage supply component can provide an upper supply voltage to the cascoded H-bridge. The lower voltage supply component can provide a lower supply voltage to the cascaded H-bridge. The pre-driver component can provide a pre-driving signal to the cascoded H-bridge, wherein pre-driver component has a first voltage source and a second voltage source. The first voltage source can provide an upper swing voltage and the second voltage source can provide a lower swing voltage. The pre-driver component can provide the pre-driving signal based on the upper swing voltage, the lower swing voltage and one of the upper supply voltage and the lower supply voltage.

Abstract: An output buffer has a first transistor and a voltage mitigation second transistor. The first transistor is configured to generate a voltage value corresponding to the power-supply voltage in response to an input signal. The second transistor is provided between an output line and the first transistor. A gate terminal of the second transistor is applied with a power-supply bias voltage which turns the second transistor on and makes a voltage between gate and source terminals of the second transistor constant in accordance with a power-supply voltage.

Abstract: An integrated circuit includes an output driver circuit having a plurality of output driver devices connected in a parallel arrangement and an output driver controller that is capable of individually controlling the conducting states of the output driver devices. In at least one embodiment, the controller is capable of achieving any of a plurality of different fall times (and/or rise times) in an output signal by appropriately controlling the conducting states of the output devices if a change in the state of the output signal is desired, in some implementations, the controller is capable of achieving different waveshapes during rising and/or failing edges of an output signal.

Abstract: An output switching circuit includes a switching circuit having a first transistor connected to a high-voltage power supply, a second transistor connected to a low-voltage power supply, and an output terminal at a connection node between the first and second transistors; a comparison unit that compares an input signal with a feedback signal obtained by feedback of an output signal of the output terminal via a low-pass filter to generate a comparison signal; and a drive pulse generating unit that generates first drive pulses for driving the first transistor and second drive pulses for driving the second transistor in accordance with the comparison signal.

Abstract: A driver circuit including front and rear amplifiers each powered by the primary and secondary power supplies, where the latter power supply is generated from the former power supply. The rear amplifier includes a cascade transistor whose base bias is provided from the bias source. The bias source provides the base bias to reduce the base current when the primary power supply is active but the secondary power supply is inactive, and to be equal to the primary power supply when two power supplies become active but the rear amplifier is inactive.

Abstract: A method includes obtaining a standard value for a characteristic of a power switch and obtaining a measured value of the characteristic, via a gate drive unit connected to a gate terminal of the power switch. The method also includes determining a health state of the power switch by comparing the measured value to the standard value of the characteristic.

Abstract: A gate driving circuit and a display apparatus having the gate driving circuit, in which the gate driving circuit includes a voltage adjusting part using a low clock signal to increase the reliability of the gate driving circuit, thereby extending the lifetime of the gate driving circuit.

Abstract: A stage circuit includes a first driver, a second driver, a first output unit and a second output unit. The first driver controls voltages of first and second nodes, according to a first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a first clock signal supplied to a second input terminal, and a second clock signal supplied to a third input terminal. The second driver controls a voltage of a third node, according to the first power source, a start signal or a carry signal of a previous stage supplied to a first input terminal, a carry signal of a next stage supplied to a fourth input terminal, and the voltage of the second node.

Abstract: A gate driver circuit that can supply a negative gate voltage to a high-side circuit without being additionally provided with an insulated power supply is realized. A driver circuit is configured such that a half-bridge circuit in which a first transistor and a second transistor are connected in series includes a capacitor that supplies a negative gate voltage to a high-side first transistor via a first control circuit, and a control circuit power supply that supplies a negative gate voltage to a low-side second transistor via a second control circuit, one end of the capacitor being connected to a negative voltage VEE on a negative terminal side of the control circuit power supply via a switching element, and the other end being connected to a voltage on an output terminal, wherein the switching element is controlled to be on upon a timing when the second transistor is turned on.

Abstract: A driver includes a first driver stage having a first T-coil structure. The first T-coil structure includes a first set of inductors each being operable to provide a first inductance. The first T-coil structure further includes a second set of inductors electrically coupled with the first set of inductors, wherein the second set of inductors each are operable to provide a second inductance.

Abstract: An output driver circuit provides an overcurrent protection function by a simple circuit configuration. The output driver circuit has a constant-current circuit, a constant-current mirror MOS transistor, and a selector circuit. The constant-current mirror MOS transistor and the output MOS transistor constitute a current mirror circuit. The gate of the output MOS transistor is controlled by a voltage based on a constant current generated by the constant-current mirror MOS transistor, thereby limiting the current flowing between the source and the drain of the output MOS transistor.

Abstract: An input buffer capable of interfacing higher-voltage logic signals to lower voltage internal circuitry includes a first stage configured to generate a first output signal in response to an input signal, the first stage configured to receive a first power supply voltage and including semiconductor circuit components configured to be variably biased responsive to a variable voltage. The input buffer also includes a second stage configured to receive the first output voltage and to responsively generate a second output signal, the second stage biased according to the first power supply voltage. The input buffer further includes a bias circuit configured to generate the variable voltage responsive to a state of the input signal.

Abstract: A decoupling circuit includes an inverter. The inverter includes i (i is an integer of 1 or more) PMOS transistors each having a first gate electrode, and j (j is an integer of 0 or more) PMOS transistors each having a second gate electrode. The inverter includes m (m is an integer of 1 or more) NMOS transistors each having a third gate electrode, and n (n is an integer of 0 or more) NMOS transistors each having a fourth gate electrode. The first to fourth gate electrodes are coupled to an input end of the inverter. A total area of the first and second gate electrodes is different from a total area of the third and fourth gate electrodes.

Abstract: A driver for a switch includes a primary side having a trigger input and a secondary side comprising an analog-to-digital converter (ADC). The primary side and the secondary side are separated by a galvanic isolation barrier and communicate via a communication circuit. The primary side is configured to receive a trigger signal at the trigger input and forward the trigger signal to the ADC of the secondary side of the driver via the communication circuit. The ADC is configured to start a measurement upon receiving the trigger signal.

Abstract: The preferred embodiments of the present invention use low voltage transistors to support high voltage switching circuits by connecting low voltage circuits in a stacking configuration. High voltage switching signals are divided into a plurality of small amplitude switching signals before sending into transformers, filters or other circuits. The resulting circuits can support high voltage applications while achieving cost and performance advantages of low voltage circuits.

Abstract: A voltage mode driver system includes a plurality of VMD cells, a plurality of auxiliary cells, a control logic and an output node. The plurality of VMD cells are configured to generate a first output. The plurality of VMD cells are configured to generate a calibrated effective resistance at different signal levels according to a calibration signal. The plurality of auxiliary cells are configured to generate a second output. The output node combines the first output and the second output into a driver output. The control logic is configured to control the plurality of auxiliary cells and the second output according to a selected level. The plurality of VMD cells may be configured to generate a calibrated effective resistance at different signal levels according to a calibration signal. A calibration component is configured to determine a voltage dependence effect and to generate a calibration signal according to the determined voltage dependence effect.

Abstract: Disclosed is a discharge path circuit of input terminal for a driver IC (Integrated Chip), the circuit providing a discharge path to the input terminal of the driver IC including a power input port connected to a first input and an operation mode selection port connected to a second input, the discharge path circuit including an LC (Inductance Capacitance) filter interconnected between the first input and the power input port to filter noise on a power source, and a resistance element interconnected between the first input and a ground terminal, wherein the resistance element provides a discharge path for discharging power charged by the input terminal of the driver IC.

Abstract: An impedance calibration circuit includes a first calibration voltage driver configured to operate in response to a first enable signal, compare a first calibration voltage signal with a first reference voltage signal, and drive the first calibration voltage signal, a first control code generator configured to operate in response to a second enable signal, compare the first calibration voltage signal with a first target voltage signal, and generate a first control code signal, and a first reference voltage generator configured to generate the first reference voltage signal in response to the first control code signal.

Abstract: A semiconductor device includes a normal code generation unit capable of generating a normal code, a test code output unit capable of storing a plurality of preliminary test codes to output a test code in response to a test control signal, and a reference voltage generation unit capable of generating a normal reference voltage in a normal operation mode and generating a test reference voltage in a test operation mode in response to the normal code and the test code.

Abstract: This application discusses, among other things, apparatus and methods for driving the bulk of a high-voltage transistor using transistors having gates with low-voltage ratings. In an example, a bulk driver can include an output configured to couple to bulk of a high-voltage transistor, a pick circuit configured to couple the output to an input voltage at an input terminal of the high-voltage transistor or an output voltage at the output terminal of the high-voltage transistor when the high-voltage transistor is in a high impedance state, and a bypass circuit configured to couple the output of the bulk driver to the output voltage when the high-voltage transistor is in a low impedance state.

Abstract: Disclosed herein is a device that includes an input receiver circuit activated by a strobe signal to generate an output signal by comparing a potential of an input signal with a reference potential, and a noise canceller cancelling noise superimposed on the reference potential due to a change in the strobe signal.

Abstract: A driver having low power consumption includes a first input terminal, a second input terminal, an output terminal, a power supply terminal, a ground terminal, a driving circuit, an adjusting circuit connected to the driving circuit and a biasing circuit which is connected to the driving circuit and the adjusting circuit. A method for accomplishing low power consumption of a driver is also provided. The method accomplishes an object of low power consumption by dynamically adjusting a driving current of a driver according to a difference between inputted differential signals.

Abstract: Methods and apparatuses are disclosed for driving a node to one or more elevated voltages. One example apparatus includes a first driver circuit configured to drive a node to a first voltage, and a second driver circuit configured to drive the node to a pumped voltage after the node reaches a voltage threshold. The apparatus also includes a controller circuit configured to disable the first driver circuit and enable the second driver circuit responsive to the node reaching the voltage threshold.

Abstract: In a scan lines driver that is used for driving scan lines of an organic light emitting diodes (OLED) display, a large voltage drop can develop between the gate or source of one of its transistors and the corresponding drain during a scan signal outputting period. This large voltage drop can excessively stress the one transistor. However, in accordance with the present disclosure, a voltage drop dissipating, second transistor is provided in series with the first transistor for absorbing part of the large voltage drop and thus reducing the stress that is applied to the first transistor.

Abstract: Provided is a semiconductor device exemplified by an inverter circuit and a shift register circuit, which is characterized by a reduced number of transistors. The semiconductor device includes a first transistor, a second transistor, and a capacitor. One of a source and a drain of the first transistor is electrically connected to a first wiring, and the other thereof is electrically connected to a second wiring. One of a source and a drain of the second transistor is electrically connected to the first wiring, a gate of the second transistor is electrically connected to a gate of the first transistor, and the other of the source and the drain of the second transistor is electrically connected to one electrode of the capacitor, while the other electrode of the capacitor is electrically connected to a third wiring. The first and second transistors have the same conductivity type.

Abstract: A system and method for reducing simultaneous switching output (SSO) noise. In one embodiment, power supply decoupling capacitances are distributed non-uniformly among a plurality of I/O circuits. Transitions between consecutive values on a data bus are either sent by the transmitter as requested at the input of the transmitter, or, in cases for which the noise of the requested transition is high, converted by an encoder to transitions having lower SSO noise. The converted transitions are decoded in a receiver, so that the data at the output of the receiver are the same as the data at the input to the transmitter.

Abstract: A driver circuit for receiving a data input and generating an output signal according to at least the data input is provided. The driver circuit includes a pair of differential output terminals, a current mode drive unit and a voltage mode drive unit. The pair of differential output terminals has a first output terminal and a second output terminal. The current mode drive unit is arranged for outputting a first reference current from one of the first and second output terminals and receiving the first reference current from the other of the first and the second output terminals according to the first data input. The voltage mode drive unit is arranged for coupling a first reference voltage to one of the first and the second output terminals and coupling a second reference voltage to the other of the first and the second output terminals according to the first data input.

Abstract: Methods and apparatus are provided that can be used to control a set of power switches operating as a power converter.

Abstract: Disclosed are a source driver provided in a display device that displays an image and a bias current adjusting method thereof, and a bias current deviating from a prescribed range is adjusted so that a source driver is driven by a bias current within the prescribed range.

Abstract: A common mode noise reduction circuit works with a transmission signal output circuit that has a first and a second output terminals and transmits differential signals from the first and second output terminals. The common mode noise reduction circuit includes: a first generating circuit to generate electric current to input to or receive electric current from the first output terminal; a second generating circuit to generate electric current to input to or output receive electric current from the second output terminal; and a control circuit to control the first and second generating circuits so that in synchronism with a drive control clock of the transmission signal output circuit, the first and second generating circuits generate current pulses to reduce common mode noise of the differential signals to be transmitted.

Abstract: A two-stage post driver circuit includes a controlling circuit, a pull-up unit and a pull-down unit. A first N-type transistor of the pull-down unit and a first P-type transistor of the pull-up unit are both connected to an output pad. The controlling circuit is used for controlling the first N-type transistor and the first P-type transistor. Consequently, when the pull-up unit or the pull-down unit is turned on, the voltage difference between the drain terminal and the source terminal of the first N-type transistor or the first P-type transistor is lower than a voltage stress.

Abstract: Driver circuits (1) for driving load circuits (2, 3) receive source signals from sources and provide feeding signals to the load circuits (2,3) and charging signals to capacitor circuits (21). These capacitor circuits (21) provide supporting signals to the load circuits (2, 3) in addition to the feeding signals. By providing the driver circuits (1) with control circuits (22) for controlling the supporting signals, the capacitor circuits (21) can become less bulky/costly and/or will limit the lifetime of the driver circuits (1) to a smaller extent. Further, these driver circuits (1) may get improved efficiencies. Said controlling may comprise controlling moments in time at which the supporting signals are offered to the load circuits (2, 3) or not, and/or may comprise controlling sizes of the supporting signals, and/or may be done in response to detection results from detectors (23) for detecting parameters of one or more signals. Said controlling may comprise switching via switches (24).

Abstract: Differential receivers are “stacked” and independently calibrated to different common-mode voltages. The different common-mode voltages may correspond to the common-mode voltages of stacked transmission circuits. Multiple stacks of samplers are connected to the same channels. The clocking of each stack of sampler circuits is phased (timed) such that the samplers in a given stack are not resolving at the same time. Samplers in a different stack and receiving a different common-mode voltage resolve at the same time.

Abstract: An output apparatus includes an output driving unit configured to drive a final output signal; an output compensating signal generation unit configured to generate a delayed output signal by delaying the output signal by a predetermined time, and generate an output compensating signal based on the delayed output signal and the output signal; and an output driving compensation unit configured to compensate for the final output signal to a level opposite to a level to which the final output signal is driven.

Abstract: The transistor suffers the variation caused in threshold voltage or mobility due to gathering of the factors of the variation in gate insulator film resulting from a difference in manufacture process or substrate used and of the variation in channel-region crystal state. The present invention provides an electric circuit having an arrangement such that both electrodes of a capacitance element can hold a gate-to-source voltage of a particular transistor. The invention provides an electric circuit having a function capable of setting a potential difference at between the both electrodes of the capacitance element by the use of a constant-current source.

Abstract: Circuits and methods to realize a power-efficient high frequency buffer. The amplitude of a buffered signal is detected and compared with the amplitude of the input signal. The comparison result can be fed back to the digitally-controlled buffer to keep the output gain constant. By using feedback control, the buffer can be kept at the most suitable biasing condition even if the load condition or signal frequency varies.

Abstract: There is provided an output stage comprising: a phase splitter for receiving an input signal and for generating first and second drive signals of opposite phase in dependence thereon; a DC offset signal generator for generating a DC offset signal; an adder for adding the DC offset signal to the first drive signal to provide a first modified drive signal; a subtractor for subtracting the DC offset signal from the second drive signal to provide a second modified drive signal; a first drive transistor associated with a first power supply voltage, for generating a first output signal in dependence on the first modified drive signal; a second drive transistor associated with a second power supply voltage, for generating a second output signal in dependence on the second modified drive signal; and a combiner for combining the first and second output signals to generate a phase combined output signal.

Abstract: A driving circuit includes a common well. The driving circuit further includes a first output buffer having a bulk connected to the common well, the first output buffer having a first terminal configured to receive a first signal, and having a second terminal connected to the common well. The driving circuit further includes a second output buffer having a bulk connected to the common well, the second output buffer having a first terminal configured to receive the first signal, wherein a second terminal of the second output buffer disconnected from the common well. The driving circuit further includes a first driver connected to the second terminal of the first output buffer and a second driver connected to the second terminal of the second output buffer.