Abstract: According to one embodiment, a apparatus for driving a capacitance-type actuator includes a first voltage source, a second voltage source, and a driver. The first voltage source outputs a first voltage to charge the capacitance-type actuator. The second voltage source outputs a second voltage to charge the actuator. The driver switches between first and second charges and first and second discharges. The first charge supplies the first voltage to the actuator. The second charge supplies the sum of the first voltage and the second voltage to the actuator. The first discharge emits a charge accumulated in the actuator and guides the charge to the second voltage source. The second discharge emits the charge accumulated in the actuator without guiding the charge to the second voltage source.

Abstract: An LVDS (Low Voltage Differential Signaling) driving circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, a second resistor, and a bias driver. The first transistor is coupled between a supply voltage and a first node. The second transistor is coupled between the supply voltage and a second node. The third transistor is coupled between the first node and a ground voltage. The fourth transistor is coupled between the second node and the ground voltage. The first resistor is coupled between the first node and a third node. The second resistor is coupled between the second node and the third node. The bias driver generates bias signals for controlling the first, second, third, and fourth transistors according to a data signal.

Abstract: Parallel transistor circuits with reduced effects from common source induction. The parallel transistors include physical gate connections that are located electrically close to one another. The parallel circuits are arranged such that the voltage at the common gate connection resulting from transient currents across common source inductance is substantially balanced. The circuits include switching circuits, converters, and RF amplifiers.

Abstract: Aspects of the invention can include a pulse generating means that outputs a set signal and reset signal for driving the high potential side switching element is such that, while either one of the set signal or reset signal is in an on-state as a main pulse signal for putting the high potential side switching element into a conductive state or non-conductive state, the other signal is turned on a certain time after the rise of the main pulse signal, thereby generating a condition in which the set signal and reset signal are both in an on-state.

Abstract: The semiconductor device includes first and second output terminals each coupled to one end side and another end side of an inductive or capacitive load, a first MOS transistor coupled between a first voltage and the first output terminal, a second MOS transistor coupled between a second voltage and the first output terminal, a third MOS transistor coupled between the first voltage and the second output terminal, a fourth MOS transistor coupled between the second voltage and the second output terminal, and a drive circuit driving the first to fourth MOS transistors for controlling the inductive or capacitive load, and further includes first and second bypass transistors for bypassing a forward current of a parasitic diode of a PN-junction formed in the MOS transistor in the dead-off period.

Abstract: A transmission channel transmits high-voltage pulses and receives echos of the high-voltage pulses. The transmission channel includes a current generator circuit, which generates current-integrator drive currents, a receiver, which amplifies transducer-echo signals, and control circuitry. The control circuitry generates one or more control signals to control generation of current-integrator drive currents by the current generator circuit during transducer-driving periods and reception of transducer-echo signals by the receiver during echo-reception periods. A current integrator integrates current-integrator drive currents generated by current generator circuit to generate transducer drive signals.

Abstract: The invention relates to an apparatus comprising a differential driver module configured to generate at least one differential signal having steep rise and fall times for at least partially reducing common-mode noise. The invention also relates to a method for causing the differential driver to generate the signal and a system comprising the differential driver and a conductor module for transmission of the generated differential signal. A computer program for performing the method and a computer-readable medium is also part of the invention.

Abstract: A driving device includes a driving circuit and a control circuit. The driving circuit has an input terminal and an output terminal and applies a driving voltage to a switching element through the output terminal. The control circuit outputs two types of control signals to the input terminal of the driving circuit. The driving circuit has a circuit group including multiple unit circuits which are turned ON by the same control signal. Each unit circuit includes one voltage source, one switch controlled to be turned ON and OFF by the control signals, and one resistor connected in series to the switch between the voltage source and the output terminal. Each voltage source outputs a different voltage, and each resistor has a different resistance. One end of each switch of all the unit circuits is connected to the output terminal.

Abstract: A novel semiconductor device and a driving method thereof are provided. In the semiconductor device, a (volatile) node which holds data that is rewritten by arithmetic processing as appropriate and a node in which the data is stored are electrically connected through a source and a drain of a transistor whose channel is formed in an oxide semiconductor layer. The off-state current value of the transistor is extremely low. Therefore, electric charge scarcely leaks through the transistor from the latter node, and thus data can be held in the latter node even in a period during which supply of power source voltage is stopped. In the semiconductor device, a means of setting the potential of the latter node to a predetermined potential is provided. Specifically, a means of supplying a potential corresponding to “1” or “0” that is data stored in the latter node from the former node is provided.

Abstract: A driver circuit includes detectors responsive to the operating region that a driven switch is operating in. The driver circuit is operative to drive the gate of the driven switch at a speed responsive to the output of the detectors.

Abstract: Electronic devices with a VCOM display panel are configured to provide a common voltage VCOM to a VCOM display panel backplane, referred to as a VCOM reference plane. The common voltage is supplied by a VCOM application circuit coupled to the VCOM reference plane. The VCOM application circuit includes a linear amplifier, such as a Class AB amplifier, coupled to a switched transient assist circuit configured to output the common voltage. The switched transient assist circuit stabilizes the amplifier in the presence of large transient output currents but with minimized power dissipation and heat rise in the amplifier.

Abstract: A power transmission device in a power transmission system including the power transmission device including a primary coil and a power reception device including a secondary coil, the primary coil being electromagnetically coupled to the secondary coil, to receive in the power reception device AC power transmitted from the power transmission device, comprises a waveform monitor circuit configured to detect an electric potential at one end of the primary coil and output a waveform monitor signal formed by restricting the detected electric potential to an electric potential which is equal to or higher than a ground electric potential; a waveform detection circuit configured to detect a waveform change in the waveform monitor signal input from the waveform monitor circuit; and a data detection circuit configured to detect data transmitted by load change by a load modulation unit in the power reception device based on a result of detection of the waveform change detected by the waveform detection circuit.

Abstract: A semiconductor circuit includes an operational amplifier, a voltage drop circuit, and a switch. The operational amplifier has an output terminal connected to an active element that produces a load drive current. A reference voltage is input to the non-inverting input of the operational amplifier. The voltage drop circuit drops a voltage outputted from the operational amplifier. The switch applies a voltage corresponding to a predetermined current flowing when the active element is on to the inverting input of the operational amplifier in a first interval in which the active element is on in response to a predetermined voltage from the operational amplifier. The switch allows the voltage dropped by the voltage drop circuit to be input to the inverting input in a second interval in which the active element is off, thereby shortening a time period until the load drive current starts to flow.

Abstract: A transistor drive circuit uses multi-stage slew rate control to drive one or more switching transistors. After a decision is made to change transistor state, a first drive current may be applied to an input terminal of the transistor for a predetermined time duration. After the predetermined time duration, a second drive current may be applied to the input terminal. When the transition between states is substantially complete, the current drive to the input terminal may be changed to a voltage drive. In some embodiments, the predetermined time duration may be based on the start time of a Miller plateau during the transition period.

Abstract: Aspects of rail-to-rail line drivers using differential cascode bootstrapping are described. In one embodiment, a differential line driver includes first and second differential driver output legs. The first output leg includes a first p-type cascode stack and a first n-type cascode stack, and the second output leg includes a second p-type cascode stack and a second n-type cascode stack. The differential line driver also includes a differential cascode bootstrap circuit arrangement coupled to an output of the differential line driver. More particularly, the differential cascode bootstrap circuit arrangement is coupled between the first and second differential output driver legs and the output of the differential line driver. According to aspects of the embodiments described herein, differential line drivers with overvoltage protection and rail-to-rail output swings may be achieved. Further, the differential line drivers may be generally smaller, with cascode stack transistors of reduced in size.

Abstract: A differential circuit system is provided. The differential circuit system includes: a different circuit set including a plurality of differential circuits, a voltage regulator, and a current drainage circuit set. The differential circuits are electrically connected between a first node and a second node, and each differential circuit generates a current flowing from the first node to the second node. A high voltage is provided to the first node and a low voltage is provided to the second node. The first node receives an external voltage. According to the first voltage, the voltage regulator generates the low voltage. The low voltage is provided to the second node. The current drainage circuit set generates a drainage current in between the second node and a ground voltage. A superposed current flowing to the voltage regulator is difference of the summation of currents minus the conducting current.

Abstract: A resistor renormalization method for a source driving circuit is provided, wherein the source driving circuit includes a plurality of resistors coupled in series, and the resistors respectively have a resistance and correspond to a number section value. The resistor renormalization method includes the steps of: (A) adding the resistances of the resistors to generate a total resistance; (B) providing a radix, wherein the radix is a natural number; (C) dividing the total resistance by the radix to generate a calculated section value; (D) dividing the resistances of the resistors by the radix to generate a plurality of remainders, respectively, and adding the remainders to generate an accumulated remainder; and (E) setting the number section value and the resistance of each resistor according to a relation between the calculated section value and the number section value and a relation between the remainder of each resistor and the radix.

Abstract: A method for calibrating signal swing and a trip reference voltage. The signal swing of a system can be calibrated in a symmetric or asymmetric technique through adjustment of a drive parameter such as a supply voltage for a transmitter or a drive termination. The trip reference voltage of the system can also be calibrated in a symmetric or asymmetric technique through sampling of a data pattern to determine an ideal level of the trip reference voltage.

Abstract: A high voltage switching circuit includes a low voltage driving circuit having first and second capacitors; and an isolated high voltage driving circuit. The isolated high voltage driving circuit has an isolated charge pump circuit and a transistor driving circuit. The first and second electrical nodes of the isolated charge pump circuit are electrically coupled to the transistor driving circuit, which is coupled to a resistive load. The transistor driving circuit increases an output voltage of the resistive load to a desired output voltage level over a time interval in response to first and second voltage signals being applied to the first and second electrical nodes, respectively, when the first and second capacitors are receiving first and second pulse width modulated voltage signals, respectively, over the time interval.

Abstract: A multiplex driving circuit receives m master signals and n slave signals, and includes m driving modules for generating m×n gate driving signals. Each driving module includes a voltage boost stage and n driving stages. The voltage boost stage is used for receiving a first master signal of the m master signals and converting the first master signal into a first high voltage signal, wherein a high logic level of the first master signal is increased to a highest voltage by the voltage boost stage. The n driving stages receives the n slave signals, respectively, and receives the first high voltage signal. In response to the highest voltage of the first high voltage signal, the n driving stages sequentially generates n gate driving signals according to the n slave signals.

Abstract: In an embodiment, an electronic includes a feedback-coupled circuit stage and a compensation circuit stage. The feedback-coupled stage is configured to drive a load, and the compensation stage is coupled to the feedback-coupled stage such that a combination of the compensation and feedback-coupled stages has a frequency response including a first root and an opposite second root that depend on the load. For example, an embodiment of such an electronic circuit may be a low-dropout (LDO) voltage regulator that lacks a large output capacitance for forming a dominant pole to stabilize the regulator. The regulator includes a feedback-coupled stage that generates and regulates an output voltage, and includes a compensation stage that is designed such that the frequency response of the regulator includes a zero that tracks a non-dominant output pole of the regulator so that the output pole does not adversely affect the stability of the regulator.

Abstract: Embodiments of the invention provide a drive circuit including: a constant current source that generates a constant current; a switching circuit that connects a gate of the insulated gate switching element to a power supply potential side via the constant current source when turning the insulated gate switching element ON and connects the gate of the insulated gate switching element to a reference potential side via a discharge circuit when turning the insulated gate switching element OFF; a gate voltage detection circuit that detects a gate voltage of the insulated gate switching element; and a current mode selection circuit that switches a mode of the constant current source from a normal current mode to a low current consumption mode when detecting, based on the gate voltage detected by the gate voltage detection circuit, that the insulated gate switching element is turned ON.

Abstract: Some embodiments of the present disclosure relate to a sense amplifier architecture that facilitates fast and accurate read operations. The sense amplifier architecture includes a folded cascode amplifier for its first sense amplifier stage, and a pre-charge circuit to establish a pre-charge condition for a senseline and a reference senseline of the sense amplifier. The pre-charge circuit and the folded cascode amplifier each include one or more cascode transistors of the same size and which receive the same bias voltage on a gate thereof. This architecture provides fast and accurate read operations in a relatively small footprint, thereby providing a good blend of cost and performance.

Abstract: A current-starved inverter circuit includes first and second current-mirror circuits, first and second transistors, a detector, and a current-booster. The first and second transistors receive a first source current and a first sink current from the first and second current-mirror circuits, respectively, and an input voltage signal, and generate an inverted input voltage signal (an output voltage signal). The detector generates a first detection signal when the output voltage signal exceeds a first threshold value and a second detection signal when the output voltage signal is less than a second threshold value. The current-booster, which is connected to the detector, receives the first and second detection signals and provides a second source current and a second sink current to the first and second transistors to pull-up and pull-down a voltage level of the output voltage signal, respectively.

Abstract: A voltage controlled switching element gate drive circuit makes it possible to suppress an occurrence of a malfunction, while suppressing surge voltage, surge current, and switching noise, when switching in a voltage controlled switching element. A gate drive circuit that supplies a gate voltage to the gate of a voltage controlled switching element, thus driving the voltage controlled switching element, includes a high potential side switching element and low potential side switching element connected in series, first variable resistors interposed between at least the high potential side switching element and a high potential power supply or the low potential side switching element and a low potential power supply, and a control circuit that adjusts the resistance values of the first variable resistors.

Abstract: A constant current circuit includes a first transistor, a second transistor having the gate and the source connected to the gate and the source of the first transistor, and having the drain connected to a load, a voltage adjustment circuit section that controls the drain voltage of the first transistor, a constant current generation circuit section that supplies a constant current to the first transistor, and a detection circuit section that determines whether at least one of the first transistor and the second transistor is unable to output a current proportional to the first constant current while at least one of the first transistor and the second transistor operates in the linear region, by performing a voltage comparison between a voltage at a connecting section between the voltage adjustment circuit section and the constant current generation circuit section and a predetermined reference voltage.

Abstract: A power supply circuit generates the internal power supply voltage intVCC from a first power supply capable of supplying a first power supply voltage V1 and a second power supply capable of supplying a second power supply voltage V2, which is lower than the first power supply voltage V1. A first transistor TR1 is provided between the first power supply and an output node, whereas a second transistor TR2 is provided between the second power supply and the output node. A first supply unit supplies the inverted value of an output voltage of the first power supply or the inverted value of a voltage corresponding to the output voltage of the first power supply, to the gate input of the first transistor TR1. A second supply unit supplies the output voltage of the first power supply or the voltage corresponding to the output voltage of the first power supply, to the gate input of the second transistor TR2.

Abstract: A method for designing a semiconductor integrated circuit includes: determining, by a designing device, first wirings over which signals are propagated and second wirings which are not used for propagation of the signals among a plurality of wirings of a semiconductor integrated circuit; and determining, by the designing device, from among the second wirings, third wirings to be used for storing electrical charges for electrical charge recycling of the first wirings for a most number of the first wirings in a range that satisfies a timing constraint based on operation rates of the signals propagated over the first wirings and delay times of the first wirings.

Abstract: A voltage transformer (10) comprises an inductor (11), a first and a second switch (15, 16), and a control unit (25). A first terminal (12) of the inductor is supplied an input voltage (VIN). The first switch (15) is disposed between a second terminal (13) of the inductor (11) and a reference potential terminal (17). The second switch (16) is disposed between the second terminal (13) of the inductor (11) and an output (19) of the voltage transformer (10). The control unit (25) is configured to set the first switch (15) in a first and a second phase (A, B) of a first operating mode of the voltage transformer (10) into a blocking operating state and to set the second switch (15) in the first phase (A) into a conducting operating state and in the second phase (B) into an operating state having different conductivity.

Abstract: A serial communication apparatus includes a slew rate control circuit, an output circuit, a detection circuit, and a switching circuit. The slew rate control circuit has a predetermined impedance, and supplies a constant current from an output according to an input signal. In the output circuit, first capacitance is charged and discharged by the constant current from the slew rate control circuit. The output circuit outputs a digital signal from an output terminal according to a drive voltage. The noise detection circuit detects noise propagated from the output terminal, and outputs a switching signal according to a detection result. The switching circuit switches an impedance of the slew rate control circuit to a value smaller than the predetermined impedance according to the switching signal.

Abstract: A gate drive circuit for driving an IGBT serving as a power semiconductor device includes a constant-current gate drive circuit that charges a gate capacity of the IGBT at a constant current, and a constant-voltage gate drive circuit that is connected in parallel to the constant-current gate drive circuit between input and output terminals thereof via a series circuit constituted by a MOSFET and a resistor, and charges the gate capacity of the IGBT at a constant voltage, wherein the gate drive circuit charges the gate capacity of the IGBT using both the constant-current gate drive circuit and the constant-voltage gate drive circuit at the time of driving the IGBT.

Abstract: The present document discloses a driver circuit for the high side switch of a half bridge at ultra-high voltage. The half bridge comprises the high side switch coupled to an input voltage Vin and to a midpoint of a low side switch. The driver circuit comprises a control signal generation unit generating a stream of control pulses and a control logic generating a gate voltage for the high side switch using a supply voltage Vcc based on the control pulses, a supply voltage capacitor generating the supply voltage Vcc, and a decoupling capacitor coupled on a first side to the control signal generation unit and on a second side to the control logic, to the midpoint of the half bridge via a first charging switch, and to the supply voltage capacitor via a second charging switch.

Abstract: A power device control circuit enters a gate driving signal into a gate terminal of a power device. The power device control circuit includes: a control signal input circuit that receives a power device control signal for control of the power device; a driving system control circuit connected to the control signal input circuit; a driving circuit with a plurality of driving systems, the driving circuit driving the power device in response to a driving circuit control signal received from the driving system control circuit; and a timer circuit that makes switching between the driving systems in response to the driving circuit control signal after elapse of a given period of time from receipt of a predetermined signal, specifically the power device control signal, thereby changing the driving power of the driving system control circuit to drive the power device.

Abstract: A cell balancing circuit includes a plurality of battery cells coupled in series, balancing switches, each balancing switch being coupled in parallel to a respective battery cell, balancing resistors, each balancing resistor being coupled in series to the respective battery cell, a balancing controller that individually controls the balancing switches such that the battery cells are discharged through the balancing resistors, and positive temperature coefficient (PTC) elements, each PTC element being positioned adjacent to a respective balancing resistor and electrically coupled to the respective balancing switch coupled in series to the respective balancing resistor.

Abstract: Embodiments of the present invention disclose a semiconductor structure and method for establishing a thermal profile across a semiconductor chip. In certain embodiments, the semiconductor structure comprises a through-silicon via formed in a first semiconductor chip having thermal control circuitry, wherein the through-silicon via is formed in a manner to be thermally coupled to the thermal control circuitry and a region of a second semiconductor chip, and wherein the through-silicon via conducts heat from the thermal control circuitry to the region. In other embodiments, the method comprises forming a through-silicon via in a first semiconductor chip having thermal control circuitry. The method also comprises forming the through-silicon via in a manner to be thermally coupled to the thermal control circuitry and a region of a second semiconductor chip, wherein the through-silicon via conducts heat from the thermal control circuitry to the region.

Abstract: A voltage level translator includes an inverter circuit configured to switch an output of the inverter circuit between a first voltage level and a second voltage level. The voltage level translator also includes a capacitor connected to the output of the inverter circuit. The voltage level translator also includes a load connected to the capacitor. The capacitance of the capacitor is approximately 10 times larger than a capacitance of the load. An output signal of the voltage level translator has at least one of a different voltage swing and a different voltage domain than an input signal to the inverter circuit.

Abstract: One or more resistors or resistances are integrated in a 7-bit DVR or PVCOM integrated circuit. A 7-bit DVR or PVCOM integrated circuit includes a 7-bit DAC. The integrated resistors or resistances (R1, R2, or RSET, or any combination) reduces the number of external components, reduces the number of pins, and increases the accuracy of the DVR or PVCOM circuit. The least significant bit (LSB) of the DAC depends only on ratios of internal resistors, which can be made very accurate and independent of temperature.

Abstract: When a counter-electromotive force generated by an inductive load is applied to the drain of a switch element, the gate of the switching element may pull the gate potential toward the direction opposite to its original potential due to capacitance coupling of the drain-gate capacitance, and this may cause a malfunction. To cope with this, a switch element that pulls the potential to the reverse direction is provided and controlled to turn on at timing at which the counter-electromotive force is applied.

Abstract: An integrated circuit with precision current source includes a first MOSFET, a second MOSFET, an op-amp and a resistor formed on a common semiconductor substrate. The first MOSFET is characterized by a first multiplier (xM1) and the second MOSFET is characterized by a second multiplier (xM2) where a ratio of xM2 to xM1 is greater than one. An inverting input of the op-amp is coupled to a drain of the first MOSFET and an output of the op-amp is coupled to a gate of the first MOSFET. A negative feedback circuit limits a rise in output current under low output voltage conditions.

Abstract: A current regulation system for generating a charging current curve for charging a rechargeable battery is provided, the system including a current regulation module coupled to a power converter to output a conversion current in a constant current mode and a constant voltage mode, a voltage-to-current regulation module coupled to the rechargeable battery to output a voltage conversion current in the constant voltage mode, a temperature-to-current regulation module and a resistance. The temperature-to-current regulation module outputs a temperature conversion current in the constant current mode and the constant voltage mode. The resistance is coupled to the current regulation module, the voltage-to-current regulation module and the temperature-to-current regulation module to regulate the voltage conversion current or the temperature conversion current, the conversion current is weakened by maintain a constant value so the charging current curve is regulated when the power of the rechargeable battery is full.

Abstract: A circuit for a large-signal electrical balance duplexer (EBD) may include a circulator that can be configured to couple an output node of a transmit (TX) path to an antenna. An EBD circuit may be coupled to the circulator, at a first port of the EBD circuit. The EBD circuit may be configured to isolate the circulator from one or more input nodes of a receive (RX) path. An attenuator may be coupled between the output node of the TX path and a second port of the EBD circuit. The attenuator may be configured to provide an attenuated signal to the EBD circuit.

Abstract: System and method for regulating a power conversion system. An example system controller for regulating a power conversion system includes a signal generator and a driving component. The signal generator is configured to receive a feedback signal associated with an output signal of a power conversion system and a current sensing signal associated with a primary current flowing through a primary winding of the power conversion system and generate a modulation signal based on at least information associated with the feedback signal and the current sensing signal. The driving component is configured to receive the modulation signal and output a drive signal to a switch based on at least information associated with the modulation signal.

Abstract: Embodiments of the invention are generally directed to elements to counter transmitter circuit performance limitations. An embodiment of an apparatus for driving data on a differential channel including a first output terminal and a second output terminal includes a differential driver circuit; and a first pre-driver and a second pre-driver, where each pre-driver has an output, wherein the first output terminal of the apparatus is coupled to the output of the first pre-driver, and the second output terminal of the apparatus is coupled to the output of the second pre-driver, where each pre-driver includes one or more capacitors, a first end of each capacitor being connected to the output of the pre-driver and a second end of each of the capacitors being connected to a sub-pre-driver circuit.

Abstract: An exemplary system includes a High-Definition Multimedia Interface (“HDMI”) analyzer and an HDMI router-switch having one or more input ports connected to one or more HDMI source devices and output ports connected to the HDMI analyzer and one or more HDMI sink devices. The HDMI router-switch is configured to establish and disestablish HDMI connections between the HDMI source devices and the HDMI analyzer and HDMI sink devices. The system further includes a control subsystem configured to control the HDMI analyzer, the HDMI router-switch, the HDMI source devices, and the HDMI sink devices, wherein the control subsystem is configured to direct one or more of the HDMI analyzer, the HDMI router-switch, the HDMI source devices, and the HDMI sink devices to perform one or more operations to execute one or more automated HDMI test routines. Corresponding methods and systems are also disclosed.

Abstract: A bidirectional switch device includes a main pass field effect transistor (FET) connected to an input node and an output node. A body region of the first main pass transistor is tied to a voltage substantially halfway between the voltage at the input node side of the first main pass transistor and the voltage at the output node side of the transistor when the first main pass transistor is in an ON state.

Abstract: Disclosed is a circuit arrangement for generating a drive signal for a transistor. In one embodiment, the circuit arrangement includes a control circuit that receives a switching signal, a driver circuit that outputs a drive signal, and at least one transmission channel. The control circuit transmits, depending on the switching signal for each switching operation of the transistor, switching information and switching parameter information via the transmission channel to the driver circuit. The driver circuit generates the drive signal depending on the switching information and depending on the switching parameter information.

Abstract: An output circuit includes: a first PMOS transistor and a second PMOS transistor connected in series between a high potential side power source and an output node; a first NMOS transistor and a second NMOS transistor connected in series between a low potential side power source and the output node; a first capacitive coupling part connected between a gate of the first PMOS transistor and gates of the second PMOS transistor and the second NMOS transistor; and a second capacitive coupling part connected between a gate of the first NMOS transistor and gates of the second NMOS transistor and the second PMOS transistor, a first bias voltage is applied to the gate terminal of the second PMOS transistor, and a second bias voltage is applied to the gate terminal of the second NMOS transistor.

Abstract: A power mixing circuit capable of maintaining a stable output voltage in a deep-power-down mode is provided. The power mixing circuit includes an input buffer, a power mixing control circuit, a power mixing driver and an output buffer. The input buffer is configured to operate using a first supply voltage, and to generate a first voltage signal in response to an input signal. The power mixing control circuit is configured to generate a power mixing control signal based on a power-up signal and a deep-power-down mode signal. The power mixing driver is configured to operate using an external supply voltage and a second supply voltage, to perform power mixing on the external supply voltage and the second supply voltage, and to generate a second voltage signal. The output buffer is configured to operate using the second supply voltage, and to generate an output signal.

Abstract: A wide bandwidth resonant clock distribution comprises a clock grid configured to distribute a clock signal to a plurality of components of an integrated circuit and a tunable sector buffer configured to receive the clock signal and provide an output to the clock grid. The tunable sector buffer is configured to set latency and slew rate of the clock signal based on an identified resonant or non-resonant mode.

Abstract: A differential line driver circuit comprising a plurality of driver stages is described. Each driver stage is operably coupled to at least one output of the line driver circuit and arranged to receive at least one control signal and to drive at least one output signal on the at least one output of the line driver circuit in accordance with the at least one control signal received thereby. The line driver circuit further comprises at least one delay component arranged to receive the at least one control signal, and to sequentially propagate the at least one control signal to the driver stages with time delays between the propagation of the at least one control signal to sequentially adjacent driver stages.