Abstract: A control portion and semiconductor switches included in a power supply system function as a current control device. The source of the semiconductor switch is connected to the source of the semiconductor switch. The two semiconductor switches connect the respective positive electrodes of a first power storage element and a second power storage element to each other. The control portion controls a current flowing between the drains of the two semiconductor switches by substantially simultaneously turning on or off the two semiconductor switches. The respective breakdown voltages between the drain and the source of the two semiconductor switches are different from each other.

Abstract: An output stage of an output buffer circuit includes a first drive transistor and a first cascode transistor (coupled in series between a first supply node and an output node) and a second drive transistor and a second cascode transistor (coupled in series between the output node and a second supply node). Gates of the first and second cascode transistors are biased with first and second bias voltages, respectively. The first bias voltage equals the first supply voltage at the first supply node when the first supply voltage is less than a threshold, and is fixed at a fixed voltage for any first supply voltage exceeding the threshold voltage. The second bias voltage equals a fixed voltage when the first supply voltage is less than a threshold voltage, and is offset from the first supply voltage by a fixed difference for any first supply voltage exceeding the threshold.

Abstract: A power switch device includes a switch which is configured to switch a load signal between an on state and an off state. A first terminal and a second terminal of the power switch device are configured to provide a supply voltage to the power switch device. The second terminal is further configured to provide a control signal to the power switch device. The control signal is generated by disconnecting the second terminal from an external voltage source. A storage circuit of the power switch device is configured to capacitively store a status of the supply voltage. A control circuit of the power switch device is configured to control operation of the power switch device depending on the stored status of the supply voltage.

Abstract: Data corrupted by a soft error is recovered. A storage device includes a first memory cell, a second memory cell, a sense circuit electrically connected to the first memory cell through a first sense line and to the second memory cell through a second sense line, a digital-analog converter circuit electrically connected to the first memory cell and the second memory cell through a bit line, and an analog-digital converter circuit. The digital-analog converter circuit has a function of applying voltages as first signals to the first memory cell and the second memory cell. Even when a soft error occurs in the first memory cell or the second memory cell, the storage device has a function of recovering data corrupted by the soft error because the sense circuit selects and outputs a higher one of the voltages applied to the first memory cell and the second memory cell.

Abstract: The transmission delay time of a receiver for receiving a differential signal is reduced. A first amplifier circuit is provided in an input stage of the receiver, and a second amplifier circuit is provided in an output stage of the receiver. The first amplifier circuit is a differential input, differential output amplifier circuit. The second amplifier circuit is a differential input, single-ended output amplifier circuit. A first power supply voltage and a second power supply voltage are input as a high-level power supply voltage and a low-level power supply voltage to the first amplifier circuit and the second amplifier circuit, respectively. The withstand voltage of transistors of a differential pair of the first amplifier circuit is higher than the withstand voltage of another transistor included in the first amplifier circuit and a transistor included in the second amplifier circuit.

Abstract: The present application relates to a gate drive unit circuit, comprising an input unit, an output unit, a pull-up node control unit, a pull-down node control unit and a pull-down unit. The input unit is used for transmitting a signal inputted by a first input signal terminal to a first node. The pull-up node control unit is used for transmitting a signal inputted by a first voltage terminal or a second voltage terminal to a pull-up node. The output unit is used for transmitting a signal inputted by a first control signal terminal to an output signal terminal. The pull-down node control unit is used for transmitting the input inputted by the first voltage terminal or the second voltage terminal to a pull-down node. The pull-down unit is used for transmitting a signal inputted by the second voltage terminal to the output signal terminal.

Abstract: A radio frequency (RF) front end device is disclosed. The device comprises a plurality of micro-electro-mechanical system (MEMS) transfer switches having a plurality of parallel switch inputs and parallel switch outputs. The device comprises a plurality of banks of a plurality of parallel signal conditioning devices and each bank comprising a plurality of parallel paths having an input side and an output side, at least two of the banks of the plurality of signal conditioning devices couple the input side to the plurality of parallel switch outputs of a preceding MEMS transfer switch and the output side to the plurality of parallel switch inputs of a succeeding MEMS transfer switch. The MEMS transfer switches are controlled to condition a wideband signal through a selected set of signal conditioning devices to improve selection sensitivity of at least one frequency in a wideband. A method and RF communications device are also disclosed.

Abstract: Disclosed herein are a high voltage switching circuit which includes one or more main switching devices connected to one or more current sources, and a control circuit unit configured to control a potential difference between terminals of each of the main switching devices within a predetermined range by receiving current from the one or more current sources.

Abstract: A system and method of over-voltage protection includes a switch coupled between a power source and a load, a detection circuit configured to detect an onset of an over-voltage event at the load; and a driver circuit coupled to the switch and the detection circuit. The driver circuit includes a boost sub-circuit that provides a low-resistance path for opening the switch in a boost mode, the boost mode being triggered by the onset of the over-voltage event and having a predetermined duration and a steady state sub-circuit that provides a high-resistance path for holding the switch open during steady state operation when the boost mode.

Abstract: A power switch driver for driving a control terminal of a power switch to drive a load, the power switch driver having a negative feedback circuit to control current delivered to the control terminal. The negative feedback circuit has a current output circuit having a current source and a current sink and serving for providing the current of the control terminal and configured to receive an output current control signal to control a magnitude of the current provided by the current output circuit, a terminal voltage input circuit for receiving a voltage from the control terminal and to output an indication of the voltage, an amplifier coupled to the terminal voltage input circuit for amplifying the terminal voltage indication to generate an amplifier output, and a reference voltage input circuit for receiving a reference voltage, having at least one resistor, and coupled to a charge supply input of the amplifier.

Abstract: The present disclosure discloses a circuit and a method for controlling gate current of a semiconductor switching device. The circuit comprises a current controlled variable inductor connected to a gate terminal of the semiconductor switching device and a feedback control circuit. The feedback control circuit comprises a differential module to compute an instantaneous rate of change of gate current with respect to time, a reference generator to generate a reference voltage and a control unit to regulate value of inductance of the variable inductor for controlling the gate current of the semiconductor switching device.

Abstract: An organic light emitting display device may include a display panel, a power supply, and a display driver, The display panel may comprise a plurality of scan lines, a plurality of data lines, and a plurality of pixels connected to the scan lines and to the data lines. The power supply may supply a first pixel voltage and a second pixel voltage to the pixels. The display driver may control the display panel. The display panel may display a first image in a first frame frequency during a first driving mode, and display a second image in a second frame frequency that is lower than the first frame frequency during a second driving mode, according to a control by the display driver.

Abstract: Switching circuitry includes first and second transistors in series between two terminals and including a common control node with a capacitance between the common control node and an intermediate point. A control circuit includes first and second circuits configured to charge and discharge the capacitance as a function of first and second control signals. The control circuit includes a third circuit having a plurality of diodes and a switch that operates when the voltage at the capacitance is greater than a threshold two diodes in cascade between the intermediate point and the common control node to enable current flow from the intermediate point to the common control node. When the voltage at the capacitance is smaller than the given threshold two diodes are connected in series between the common control node and the intermediate point to enable current flow from the common control node to the intermediate point.

Abstract: Disclosed herein is a power supply apparatus for a sub-module controller of a Modular Multilevel Converter (MMC), which supplies driving power to the sub-module controller of an MMC connected to a High Voltage Direct Current (HVDC) system. The power supply apparatus includes a bridge circuit unit including N (N?2, integer) energy storage units for storing a DC voltage in series-connected sub-modules in the MMC and multiple power semiconductor devices connected in parallel with the N energy storage units in a form of a bridge; and a DC/DC converter for converting a voltage output from output terminals formed between both ends of n (1?n<N) series-connected energy storage units, among the N energy storage units, into a low voltage and supplying the low voltage to the sub-module controller.

Abstract: A system for mitigating a solid state power controller (SSPC) open or closed state change caused by single event latchup (SEL) includes an ON circuit, an OFF circuit operatively connected in parallel to the ON circuit, a holding capacitor operatively connected in parallel with the ON circuit and the OFF circuit, and a power switching device operatively connected to the holding capacitor and the ON circuit. The system is configured to maintain, during and after the SEL, a drive state voltage to the power switching device that is stored in the holding capacitor prior to the SEL.

Abstract: A drive circuit having an output terminal includes a buffer circuit including a first transistor and a second transistor that are connected in parallel between a power supply and the output terminal. The first transistor and the second transistor are controlled such that after the first transistor and the second transistor are simultaneously turned on, the second transistor is turned off earlier than the first transistor.

Abstract: At least some embodiments are directed to a system that comprises a differential switch network comprising first and second output nodes, first and second transistors coupled to the network, and first and second resistors coupled to the first and second transistors. The DAC also comprises a voltage source coupled to the first resistor and a ground connection coupled to the second resistor. The DAC further includes a capacitor coupled to the first and second transistors and to the second resistor.

Abstract: The invention concerns an electrical system that comprises: —an electrical charge (42, 43); —a decoupling capacitor (41); —a DC voltage power supply system, comprising first and second terminals (321, 322), including: —a DC voltage source (2) comprising first and second poles; —a first branch including a first contactor (51); —a second branch including first and second switches (302, 303) and an inductor (305) connected in series in order to selectively connect the DC voltage source to the first terminal (321) of the power supply system; —a unidirectional conducting device (307, 308, 309) for conduction from the second terminal of the DC power supply system to a connection node (323) between the second switch (303) and said inductor (305); —a control circuit (304) comprising —a mode for supplying electrical load (42, 43); —a mode for charging the decoupling capacitor (41).

Abstract: A driver circuit (101) is connected to a control terminal of a semiconductor switching element (1). The driver circuit (101) includes an input circuit (3) connected to an input terminal (50), and an output control circuit (4) connected to the input circuit (3). A pulse signal output from the output control circuit (4) is input to a dead time adjustment circuit (13). The dead time adjustment circuit (13) includes a delay circuit which can delay the rising edge and the falling edge of the pulse signal output from the output control circuit (4) on the basis of signals from temperature analog output circuits (11) and (12). An output from the dead time adjustment circuit (13) is input to the drive circuit (5). The drive circuit (5) outputs a drive signal to an output terminal (51) of the driver circuit (101).

Abstract: In one embodiment, a Light Emitting Diode (LED) driving device for driving a plurality of LEDs has a switching matrix utilizing a plurality of one of a turn off thyristors or turn off triacs coupled to the plurality of LEDs. A controller is coupled to the switching matrix responsive to a voltage of a rectified AC halfwave, wherein combinations of the plurality of LEDs are altered to ensure a maximum operating voltage of the plurality of LEDs is not exceeded. A current limiting device is coupled to the combinations of the plurality of LED to regulate current.

Abstract: A low voltage differential signaling (LVDS) driver circuit, system, apparatus, and methodology are provided for controlling switching components in a primary current stage and a pre-emphasis current stage with an adaptive pre-emphasis gain tuning hardware control circuit arranged to provide control signals for periodically tuning a pre-emphasis gain setting for the secondary pre-emphasis current stage by selecting an optimum pre-emphasis gain setting from a plurality of pre-emphasis gain setting which minimizes an inter-symbol interference (ISI) jitter measure for the LVDS driver circuit.

Abstract: A driving circuit for driving a light emitting unit includes a gray scale generation circuit and a driving unit, and a gray scale generation circuit, includes a shift register unit and a data storage unit. The shift register unit receives a luminance-related data, and the shift register unit is a k-bit shift register unit. The data storage unit has parallel input ends and a serial output end. The data storage unit receives the luminance-related data via its parallel input ends and serially outputs bits of the luminance-related data to generate a serial signal. The data storage unit determines time points to output different bits of the serial signal to generate a gray-scale control signal according to a serial-out control signal. The driving unit is coupled to the gray scale generation circuit to adjust a light-emitting time of the light emitting unit according to the gray-scale control signal.

Abstract: A LED driving circuit comprises a high bit driving circuit, a low bit driving circuit and a driving output terminal. The high bit driving circuit coupled to a high bit signal of the grayscale signal determines a first current continuously driven during a grayscale period according to the value of the high bit signal. The first current is invariant during the grayscale period. The low bit driving circuit coupled to a low bit signal of the grayscale signal determines a second current driven in at least two time intervals during the grayscale period according to the value of the low bit signal. The driving output terminal coupled to the high bit driving circuit and the low bit driving circuit outputs the driving current added by the first current and the second current. Accordingly, the LED display can be improved with higher refresh rate and/or better uniformity in low grayscale.

Abstract: An integrated circuit includes an IO node, and an IO driver coupled thereto. The IO driver has a first driving circuit with a first PMOS transistor having a source coupled to a supply node and a gate coupled to receive a PMOS driving signal, and a first NMOS transistor having a source coupled to ground, a drain coupled to the drain of the first PMOS transistor, and a gate coupled to receive a NMOS driving signal. The IO driver also has a second driving circuit with a second PMOS transistor having a source coupled to the supply node and a gate coupled to receive a first delayed version of the PMOS driving signal, and a second NMOS transistor having a drain coupled to the drain of the second PMOS transistor, a source coupled to ground, and a gate coupled to receive a first delayed version of the NMOS driving signal.

Abstract: A driver circuit includes a high-side power transistor having a source-drain path coupled between a first node and a second node and a low-side power transistor having a source-drain path coupled between the second node and a third node. A high-side drive circuit, having an input configured to receive a drive signal, includes an output configured to drive a control terminal of said high-side power transistor. The high-side drive circuit is configured to operate as a capacitive driver. A low-side drive circuit, having an input configured to receive a complement drive signal, includes an output configured to drive a control terminal of said low-side power transistor. The low-side drive circuit is configured to operate as a level-shifting driver.

Abstract: A load driving device includes: a first turn-on drive circuit turning on a first power device as one of a plurality of gate-driven power devices; a second turn-on drive circuit turning on a second power device as another one of the plurality of gate-driven power devices different from the first power device; a current detection circuit detecting a current in at least the first power device; and a control circuit controlling the first turn-on drive circuit to turn on the first power device by applying a gate voltage with a first change rate, and subsequently controlling the second turn-on drive circuit to turn on the second power device by applying a gate voltage with a second change rate, which is larger than the first change rate, based on a condition in which the current detection circuit does not detect an overcurrent in the first power device.

Abstract: A parameter is compared to a lower threshold. The parameter is a gate-to-source voltage that is associated with a first transistor or a drain current that is associated with the first transistor. The first transistor is a field effect transistor, and the first transistor is a power device. If one or more of at least one supplemental transistor is coupled to the first transistor, and the parameter is less than the lower threshold, a plurality of switches is controlled to decouple at least one of the at least one supplemental transistor from the first transistor.

Abstract: The present invention relates to telecommunication techniques and integrated circuit (IC) devices. In a specific embodiment, the present invention provides a laser deriver apparatus that includes a main DAC section and a mini DAC section. The main DAC section processes input signal received from a pre-driver array and generates an intermediate output signal. The mini DAC section provides a compensation signal to reduce distortion of the intermediate output signal. The intermediate output signal is coupled to output terminals through a cascode section and/or a T-coil section. There are other embodiments as well.

Abstract: A semiconductor device includes a switching element including a control electrode, a first main electrode, and a second main electrode: a gate driver connected between the control electrode and the first main electrode, configured to transmit a gate drive signal for driving the control electrode; a Miller voltage detector detecting a Miller voltage between the control electrode and the first main electrode when the switching element turns off; a current value detector detecting a principal current flowing through the switching element; and a temperature calculator calculating a temperature of the switching element from the detected Miller voltage and principal current.

Abstract: The present application discloses a gate driver on array (GOA) unit, including: a buffering module, a pull-up module, a pull-down module, a retaining module, a charging module, and a discharging module, a pull-up node being coupled to the buffering module, the discharging module, the pull-up module, and the charging module, and a pull-down node being coupled to the discharging module and the retaining module. The buffering module, being coupled to an input signal terminal and a pull-up node and controlled by a voltage of the input signal terminal, is configured to output the voltage of the input signal terminal into the pull-up node. The pull-up module, being coupled to a first clock signal terminal, the pull-up node, and an output signal terminal and controlled by a voltage of the pull-up node, is configured to output a voltage of the first clock signal terminal into the output signal terminal.

Abstract: The present invention concerns a system comprising a multi-die power module composed of dies and a controller receiving input patterns for activating the dies of the multi-die power module. The controller comprises means for generating from the input patterns gate to source signals to apply to the dies and for each die, the gate to source voltage is shifted according to a given voltage value.

Abstract: According to one embodiment, a constant voltage circuit includes a first resistance including a first terminal coupled to a first voltage terminal, and a second terminal coupled to a first node; a first transistor including a first terminal coupled to the first voltage terminal, a second terminal coupled to a second node, and a control terminal coupled to the first node; a first diode coupled in series between the first node and a second voltage terminal; a Zener diode, and a second transistor coupled in series between the first node and the second voltage terminal; a second resistance, and a third transistor coupled in series between the first node and the second voltage terminal; and third and fourth resistances coupled in series between the second node and the second voltage terminal.

Abstract: An input circuit may include: an internal bias generation unit suitable for generating first and second bias voltages in response to a first enable signal; a buffer control unit suitable for comparing a reference voltage to the first and second bias voltages, and generating a plurality of buffer control signals based upon the comparison of the reference voltage with the first and second bias voltages; and a buffer unit including a plurality of buffers, wherein a buffer is driven to receive the reference voltage and an external input signal, and generates an internal signal, in response to an activated buffer control signal among the plurality of buffer control signals.

Abstract: A gate driving circuit includes: a plurality of stages configured to output a plurality of gate signals, wherein an Nth stage of the plurality of stages includes: an output pull-up unit including a control electrode connected to a first node, wherein the output pull-up unit is configured to increase an electric potential at the first node and is further configured to receive a clock signal and to output a gate signal of the Nth stage; a control node pull-up unit configured to charge the first node according to an (N?1)th control signal and an (N?2)th control signal; a control node pull-down unit configured to discharge a voltage of the first node as a first low voltage according to an (N+1)th control signal; and an output pull-down unit configured to discharge a gate signal of the Nth stage as the first low voltage according to the (N+1)th control signal.

Abstract: Systems and techniques for compensation to improve write signal controls for magnetic-medium-based storage devices, include an apparatus comprising: pre-compensation circuitry coupled with a controller to receive a data signal and a write-current control signal and to generate a write-current signal; the pre-compensation circuitry is configured to use different baseline write-current levels for the write-current signal after an overshoot write-current level used at polarity transitions of the write-current signal, and the pre-compensation circuitry is configured use a first baseline level of the different baseline write-current levels for a first type of magnet in the sequence of magnets and use a second baseline level of the different baseline write-current levels for a second type of magnet in the sequence of magnets, the first baseline level having a greater magnitude than the second baseline level, and the first type of magnet being shorter than the second type of magnet.

Abstract: A GOA circuit includes GOA circuit units. A holding module is substituted for a capacitor in each GOA circuit unit. A second transistor in the holding module is turned on when a scanning signal does not produce a pulse so that voltage imposed in a first control node is held by a first transistor and a third transistor. Because the transistors form a passage between the first control node and a first constant voltage, the voltage imposed on the first control node does not vary due to electricity leakage. Because a second capacitor is coupled with the first control node, the pulse of the scanning signal output by the GOA circuit unit reaches to an ideal high voltage level. The GOA circuit unit can resolve the problem of easy leakage of electricity. When the scanning signals are output by the GOA circuit unit, the stability is highly ensured.

Abstract: An output of a gate driver that drives a main switch is connected to the gate of the main switch, and a low-voltage side power supply terminal of the gate driver is connected to a source of the main switch via a current limiting resistor. Moreover, a suppression capacitor for suppressing rapid changes in current, having a prescribed capacitance, is connected between the drain of the main switch of a main circuit and the low-voltage side power supply terminal of the gate driver. This makes it possible to suppress the rapid change in current that occurs when the main switch switches OFF as well as to prevent extremely large currents from occurring in a low-voltage side power supply line of the driver circuit.

Abstract: Provided is a semiconductor device which can operate stably even in the case where a transistor thereof is a depletion transistor. The semiconductor device includes a first transistor for supplying a first potential to a first wiring, a second transistor for supplying a second potential to the first wiring, a third transistor for supplying a third potential at which the first transistor is turned on to a gate of the first transistor and stopping supplying the third potential, a fourth transistor for supplying the second potential to the gate of the first transistor, and a first circuit for generating a second signal obtained by offsetting a first signal. The second signal is input to a gate of the fourth transistor. The potential of a low level of the second signal is lower than the second potential.

Abstract: In order to reduce electric field concentration in a semiconductor device including a main transistor section and a sense transistor section, the semiconductor device is provided, the semiconductor device including a semiconductor substrate of a first conductivity type, a main transistor section in an active region on the semiconductor substrate, and a sense transistor section outside the active region on the semiconductor substrate, wherein the active region is provided with a main well region of a second conductivity type, and wherein the sense transistor section has a sense gate trench section formed extending from the outside of the active region to the main well region on the front surface of the semiconductor substrate.

Abstract: An electronic device with fingerprint recognition circuit powered by dedicated power source includes a functional circuit, a plurality of fingerprint sensing electrodes, and a fingerprint sensing control circuit. The functional circuit is powered by a first power source. The fingerprint sensing electrodes are provided for sensing a contact of a finger. The fingerprint sensing control circuit is powered by a second power source which is different from the first power source. The fingerprint sensing control circuit is connected to the fingerprint sensing electrodes for driving the fingerprint sensing electrodes to sense the fingerprint, wherein there is no common current loop between the first power source and the second power source during an operation of fingerprint sensing.

Abstract: Unique systems, methods, techniques and apparatuses of a gate driver are disclosed herein. One exemplary embodiment is a gate driver comprising a first and second DC rail, a first converter arm including a first and second semiconductor device, a second converter arm including a third and fourth semiconductor device, an inductor, and a controller. The controller is configured to open and close the primary switching device by operating the semiconductor devices so as to transmit power between the gate driver and a gate of a primary switching device. The controller is configured to transmit a gate signal to the primary switching device by closing the second semiconductor device, then opening the second semiconductor device and closing the fourth semiconductor device in response to the gate of the primary switching device receiving power with a voltage greater than or equal in magnitude to the voltage of the second DC rail.

Abstract: An inrush current control device for an IC chip having multiple functional units and M power switches comprises a programmable counter unit, a selector unit and an enable signal driving unit. The programmable counter unit counts a clock signal and sets a predetermined counting value. The selector unit is connected to the programmable counter unit and has N output ports for outputting N enable signals. The enable signal driving unit has N enable driving circuits correspondingly connected to the N output ports of the selector unit, and controlling on/off states of N groups of the M power switches. The programmable counter unit controls the selector unit to output the N enable signals to the N enable signal driving circuits at a predetermined time interval determined by the predetermined counting value to switch on the N power switches groups successively to reduce the transient inrush current.

Abstract: A power switching cell with normally on field-effect transistors comprises a current switch receiving the control input signal over an activation input and a power transistor for switching a high voltage VDD applied to its drain, to its source that is connected to the output port of the cell. The control of the gate of the power transistor whose source is floating, according to the input signal, is provided by a self-biasing circuit connected between its gate and source. The current switch is connected between the self-biasing circuit and a zero or negative reference voltage. The self-biasing circuit comprises a transistor whose source or drain is connected to the gate or source of the power transistor. The gate of this transistor is biased by a resistor connected between its gate and source, and between the current switch and the source. The transistors are HEMT transistors using GaN or AsGa technology.

Abstract: A load balancing circuit comprising a first power source, a first field effect transistor (FET) device having a drain terminal connected to the first power source and a source terminal connected to a first node, a first resistor connected to the first node and a second node, a load connected to the second node, a second FET device having a drain terminal connected to the first node and a source terminal connected to the second node, a third FET device having a collector terminal connected to a gate terminal of the first FET device and an emitter terminal connected to the second node, and a second resistor connected to a base terminal of the third FET device and the first node.

Abstract: In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.

Abstract: A motor incorporating a power converter including a printed board on which a semiconductor module (an inverter IC), which converts a voltage of an external power supply into a high-frequency voltage and supplies the high-frequency voltage to a stator, is mounted, wherein a high-voltage circuit ground, which is a power ground of a high-voltage main circuit system of the inverter IC, and a low-voltage circuit ground, which is a ground of a control circuit system, which is a low-voltage circuit, of the semiconductor module, are provided on the board, and the high-voltage circuit ground and the low-voltage circuit ground are connected at one point via a resistor.

Abstract: A differential communication circuit includes: a first switch in between a signal line and a power source, a second switch in between a signal line and a ground, a third switch in between the signal line and the ground, a fourth switch in between the signal line and the power source, first and second drivers respectively driving the first and second switches, and third and fourth drivers respectively driving the third and fourth switches OFF to ON at an ON to OFF timing of the first and second switches, for setting an ON period of the third and fourth switches to be shorter than a one-bit width in a communication signal and enabling a stable signal level determination while reducing power consumption of the differential communication circuit.

Abstract: An impedance calibration circuit includes a first reference resistor electrically coupled to a calibration pad, a second reference resistor which is coupled to the first reference resistor in parallel and a resistance value of the second reference resistor is varied according to an operation voltage mode, and a calibration circuit electrically coupled to the calibration pad and configured to generate a calibration code according to a resistance value formed by the first reference resistor and the second reference resistor and calibrate an impedance value in the calibration pad according to the calibration code.

Abstract: A power circuit includes a power transistor sinking a power current according to a voltage of a driving node and a driving circuit which includes a first bootstrap circuit, a second bootstrap circuit receiving a second internal signal to generate a first internal signal, a pre-driver receiving a third internal signal to generate the second internal signal, and a hysteresis circuit receiving a control signal to generate the third internal signal with a hysteresis. The first bootstrap circuit includes a high-side transistor providing a supply voltage to the driving node according to a high-side voltage, a low-side transistor electrically connecting the driving node to the ground according to the first internal signal, and a charge pump generating the high-side voltage exceeding the supply voltage according to the first internal signal and the second internal signal.

Abstract: An apparatus for driving a load using a low supply voltage includes a voltage-mode driver and a current source arrangement. The voltage-mode driver provides a desired termination impedance and a first portion of a desired output current to the load. The current source arrangement provides a second portion of the desired output current. The desired output current generates a predetermined voltage swing across the load, while the voltage-mode driver and the current source arrangement are powered by the low supply voltage.