Abstract: The invention provides a shift register unit, including a pull-up node, a pull-down node, a low-level signal terminal, a second clock signal terminal and a pull-down module, the second clock signal terminal supplies a high-level signal during an input sub-period and a pull-down sub-period, the pull-down module is connected to the pull-up node, the pull-down node, an output terminal of the shift register unit and the low-level signal terminal, the shift register unit further includes a discharging module, which is configured to make the pull-down node and the low-level signal terminal be connected in a conducting path during the input sub-period, and both the pull-up node and the output terminal of the shift register unit are connected with the low-level signal terminal in conducting paths during the input sub-period and the pull-down sub-period.

Abstract: The present invention relates to telecommunication techniques and integrated circuit (IC) devices. In a specific embodiment, the present invention provides a laser deriver apparatus that includes a main DAC section and a mini DAC section. The main DAC section processes input signal received from a pre-driver array and generates an intermediate output signal. The mini DAC section provides a compensation signal to reduce distortion of the intermediate output signal. The intermediate output signal is coupled to output terminals through a cascode section and/or a T-coil section. There are other embodiments as well.

Abstract: Disclosed herein is an apparatus that includes an output signal line, and first and second tristate buffer circuits each having an output node connected to the output signal line in common. The output signal line includes a first section having first and second connection points, a second section having third and fourth connection points, a third section connected between the first and third connection points, and a fourth section connected between second and fourth connection points. At least a part of the first section of the output signal line is located on the first tristate buffer circuit, and at least a part of the second section of the output signal line is located on the second tristate buffer circuit.

Abstract: An integrated circuit includes: a first differential buffer suitable for receiving a primary signal through a primary input terminal thereof, and receiving a secondary signal through a secondary input terminal thereof, wherein the secondary signal has a phase opposite to a phase of the primary signal; a second differential buffer suitable for receiving a first reference voltage through primary and secondary input terminals thereof; and an operational amplifier suitable for receiving a first common mode voltage of the primary and secondary output terminals of the first differential buffer and a second common mode voltage of the primary and secondary output terminals of the second differential buffer, to output the first reference voltage.

Abstract: A device for switching Gallium Nitride (GaN) devices includes a high side driver, low side driver, and high side charge circuitry. The high side driver is adapted to control a high side GaN device using a high side supply. The low side driver is adapted to control a low side GaN device using a low side supply. The high side charge circuitry is adapted to charge the high side supply with the low side supply when the low side driver activates the low side GaN device.

Abstract: A power supply system comprises an amplifier stage that includes at least one transistor, for example an LDMOS transistor. The transistor is connected to a supply voltage via a power connection, and is controlled by a control voltage at the control connection of the transistor. In some implementations, a first controller is provided for adjusting the control voltage of the transistor, and a second controller is provided for adjusting the supply voltage. In some implementations, one of the controllers is designed to feed a state signal to the other controller, and the other controller is designed to evaluate the state signal.

Abstract: A load balancing circuit comprising a first power source, a first field effect transistor (FET) device having a drain terminal connected to the first power source and a source terminal connected to a first node, a first resistor connected to the first node and a second node, a load connected to the second node, a second FET device having a drain terminal connected to the first node and a source terminal connected to the second node, a third FET device having a collector terminal connected to a gate terminal of the first FET device and an emitter terminal connected to the second node, and a second resistor connected to a base terminal of the third FET device and the first node.

Abstract: In a drive circuit, a control switch is electrically connected between a negative voltage source and a reference voltage generator. A drive controller switches a discharge switch and a control switch from an off state to an on state to thereby supply a first negative output voltage to a main control terminal of a target switch. The drive controller switches the discharge switch and the control switch from the on state to the off state to thereby change the first negative output voltage to be supplied to the main control terminal of the target switch to a second negative voltage based on the reference voltage generated by the reference voltage generator. The second negative voltage is more positive than the first negative voltage.

Abstract: A circuit includes a first transistor and a second transistor having respective control terminals coupled to receive first and second bias voltages. A first electronic switch is coupled in series with, and between current paths of the first and second transistors to provide an output current line between a circuit output node and ground. A second electronic switch is selectively activated to a conductive state in order to provide a charge transfer current path between a bias node and a charge transfer node in the output current line. A third electronic switch is selectively activated to a conductive state in order to provide a charge transfer current path between the charge transfer node and the control terminal of the second transistor.

Abstract: A method of controlling a slew rate of a MOSFET connected to a battery for supplying an electrical current to an electrical load is provided. A state transition of the MOSFET is provided and a drain-source voltage of the MOSFET is monitored. A variable current is provided through a gate of the MOSFET. A constant current is provided through the gate of the MOSFET, when the drain-source voltage of the MOSFET satisfies a predefined condition that is a function of a battery voltage.

Abstract: A switching control circuit includes a first current source, a second current source, a first switch disposed between the first current source and a gate of a switching element, and a second switch disposed between the second current source and the gate of the switching element. The first switch and the second switch are complementarily turned on and off according to a pulse signal. At least one of a value of current supplied to the gate of the switching element from the first current source when the first switch is turned on, and a value of current that flows out from the gate of the switching element to the second current source when the second switch is turned on, is changed periodically.

Abstract: A switching amplifier includes a power device and a processing device. The power device is configured for powering a load and is comprised of a plurality of switches. The processing device configured to calculate a switch junction temperature for a bonding wire in each switch based at least in part on a power loss of each switch; generate a first accumulated fatigue damage of the bonding wire in each switch based on the switch junction temperature; and generate an estimated remaining lifetime of the switching amplifier based on the first accumulated fatigue damages of the bonding wires in each switch.

Abstract: A class-D amplifier system includes one or more pulse width modulation (PWM) output paths at least one of which includes one or more digital closed-loop PWM modulators (DCL-PWMM) in which at least one of the DCL_PWMM includes a digital integrator that provides an output value and receives a feedback value. The output value has an output resolution and the feedback value has a feedback resolution that is coarser than the output resolution. The output value is the sum of an integer multiple of the feedback resolution and a residue. Control logic decreases/increases the residue of the digital integrator toward an integer multiple of the feedback resolution over a plurality of clock cycles in response to a request to transition the class-D amplifier and forces an output of the DCL_PWMM to have an approximate 50% duty cycle after decreasing/increasing the residue over the plurality of clock cycles.

Abstract: An amplifier includes an input stage, a folded cascode stage, and a class AB output stage. The folded cascode stage is coupled to the input stage. The class AB output stage is coupled to the folded cascode stage. The class AB output stage includes a high-side output transistor, a low-side output transistor, and a high-side feedback circuit that is coupled to the high-side output transistor. The high-side feedback circuit includes a high-side sense transistor and a high-side feedback transistor. The high-side sense transistor includes a control terminal that is coupled to a control terminal of the high-side output transistor. The high-side feedback transistor is coupled to an output of the high-side sense transistor and to the folded cascode stage. A first output of the folded cascode stage is coupled to the control terminal of the high-side sense transistor and to the control terminal of the high-side output transistor.

Abstract: A GaN digital circuit is disclosed. The circuit includes a first output node on a substrate, a pull up switch connected to a first output node and a power supply node having a second voltage, a capacitor having a first terminal configured to cause the voltage at the gate of the pull up switch to increase to substantially the sum of the second voltage and a third voltage in response to the voltage at the first output node increasing to the second voltage. The circuit also includes a first depletion mode charging switch configured to cause a voltage at the first terminal of the capacitor to become substantially equal to the third voltage while the voltage at the first output node is substantially equal to the first voltage and is configured to be substantially nonconductive while the voltage at the first output node is substantially equal to the second voltage.

Abstract: A memory interface may include a transmitter that generates multi-level signals made up of symbols that convey multiple bits of data. The transmitter may include a first data path for a first bit (e.g., a least significant bit (LSB)) in a symbol and a second data path for a second bit (e.g., the most significant bit (MSB)) in the symbol. Each path may include a de-emphasis or pre-emphasis buffer circuit that inverts and delays signals received at the de-emphasis or pre-emphasis buffer circuit. The delayed and inverted data signals may control de-emphasis or pre-emphasis drivers that are configured to apply de-emphasis or pre-emphasis to a multi-level signal.

Abstract: A signal output circuit includes a slope control circuit, a capacitor, a noise detector circuit and a fail-safe circuit. The slope control circuit charges and discharges the capacitor, the first terminal of which is connected to an output terminal, according to the control signal level, and drives transistors using the voltage of the second terminal of the capacitor, thereby controlling the slope of the output single. The noise detector circuit detects noise superimposed on the output terminal. When noise is detected, the fail-safe circuit performs a forced drive operation on the transistor to output the output signal at a level corresponding to the level of the control signal is output, regardless of the transistor being driven by the slope control circuit.

Abstract: An overvoltage protection device including an output stage, a first switch and a first load providing circuit is provided. The output stage has a first input terminal to receive a first signal, and generates an output signal at an output terminal of the output stage according to the first signal. A first terminal of the first switch is coupled to the first input terminal of the output stage, and a control terminal of the first switch receives a second signal. The first signal is the delayed second signal. The first load providing circuit is coupled to a second terminal of the first switch. The first load providing circuit provides an impedance to the first input terminal when the first switch is turned on.

Abstract: An amplifier may include a first transistor. The amplifier may also include a second transistor coupled to the first transistor in an output stage of the amplifier. The amplifier may also include a level shift resistor coupled between a gate of the first transistor and a gate of the second transistor. The amplifier may further include a feedback bias circuit coupled to the gate of the first transistor and the gate of the second transistor through the level shift resistor. The feedback bias circuit may be configured to sense a common mode voltage of the output stage of the amplifier, and to compare the common mode voltage with a reference voltage to control a resistor bias current conducted by the level shift resistor.

Abstract: A power conversion device converting and outputting a characteristic of input power, includes: a power conversion unit including a normally-on type first switching element made of a nitride-based semiconductor material and converting the characteristic of power by a switching operation performed by the first switching element; an operation control unit controlling a switching operation of the first switching element; and an intelligent power switch including: a second switching element provided on a power input side of the power conversion unit and turning on/off power input to the power conversion unit; and a protection control unit including a current detection unit detecting a current flowing in the second switching element and controlling on/off of the second switching element and turn off the second switching element in a case where a current detected by the current detection unit exceeds a threshold value.

Abstract: At least some embodiments are directed to a system that comprises a differential switch network comprising first and second output nodes, first and second transistors coupled to the network, and first and second resistors coupled to the first and second transistors. The DAC also comprises a voltage source coupled to the first resistor and a ground connection coupled to the second resistor. The DAC further includes a capacitor coupled to the first and second transistors and to the second resistor.

Abstract: An abnormality notification switch is switched on when a power storage module is abnormal but is switched off when the power storage module is normal. A first detection element outputs a signal indicating an abnormality of the power storage module when detecting that an electric current flows along an electric current line. A second detection element is inserted into an electric current line between a node and a second high-side reference potential that has a higher potential than a potential of a first high-side reference potential. The second detection element outputs a signal indicating an occurrence of a disconnection when detecting that no electric current flows along this electric current line. A retaining circuit retains a potential at the node higher than the first high-side reference potential and lower than the second high-side reference potential.

Abstract: In one embodiment, a (pre)driver circuit includes first and a second output terminal for driving an electronic switch that includes a control terminal and a current path through the switch. The arrangement can operate in one or more first driving configurations (e.g., for PMOS), with the first and second output terminals are coupled to the current path and the control electrode of the electronic switch, respectively, and one or more second driving configurations (e.g., for NMOS, both HS and LS), wherein the first and second output terminals of the driver circuit are coupled to the control electrode and the current path of the electronic switch, respectively.

Abstract: A lever shifter includes an output driver and a high-side gate driver. The high-side gate driver is configured to drive the high-side output transistor, and is coupled to an on pulse signal line that conducts an on pulse, and is coupled to an off pulse signal line that conducts an off pulse. The high-side gate driver includes a blocking circuit configured to enable generation of a drive signal to the high-side output transistor based on a voltage of a first of the on or off pulse signal line being greater than a first predetermined amount and a voltage of a second of the on or off signal line being less than a second predetermined amount.

Abstract: The present application provides a gate driver circuit comprising at least one cascaded gate driver circuit unit. The low-level-holding enabling terminal of the gate driver circuit unit is connected to an adaptive voltage generating module. The adaptive voltage generating module generates a self-compensating voltage according to its constant current source and transmits to the low-level-holding enabling terminal, so as to provide an effective voltage level to the low-level-holding enabling terminal. Because the threshold voltage shift caused by pulling-down transistors in the low-level-holding module is embodied at the low-level-holding enabling terminal, the adaptive voltage generating module generates a self-compensating voltage with its constant current source according to the threshold voltage to compensate the increase of the threshold voltage.

Abstract: A gate drive circuit for generating asymmetric drive voltages comprises a gate drive transformer comprising: a primary winding responsive to a pulse width module (PWM) input signal to generate a bipolar signal having a positive bias voltage and a negative bias voltage; and a secondary winding responsive to the bipolar signal to generate a PWM output signal. A first charge pump is connected to the secondary winding responsive to the PWM output signal to generate a level shifted PWM output signal. A second charge pump is connected to the secondary winding to generate a readjusted PWM output signal by decreasing at least a portion of the level shifted PWM output signal. A gate switching device is connected to the first charge pump and second charge pump. A level shifted PWM output signal establishes an ON condition and the readjusted PWM output signal establishes an OFF condition of the gate MOSFET.

Abstract: We disclose apparatus which may provide power amplification in millimeter-wave devices with reduced size and reduced power consumption, and methods of using such apparatus. One such apparatus comprises an input transformer; a first differential pair of injection transistors comprising a first transistor and a second transistor; a first back gate voltage source configured to provide a first back gate voltage to the first transistor; a second back gate voltage source configured to provide a second back gate voltage to the second transistor; a second differential pair of oscillator core transistors comprising a third transistor and a fourth transistor, wherein the third transistor and the fourth transistor are cross-coupled; a third back gate voltage source configured to provide a third back gate voltage to the third transistor; a fourth back gate voltage source configured to provide a fourth back gate voltage to the fourth transistor; and an output transformer.

Abstract: A transmitter may include a driver having a PMOS transistor and an NMOS transistor connected in series between a first power supply and a second power supply. The driver may be configured to output an output signal. The transmitter may further include a driver control circuit configured to control a gate voltage of the PMOS transistor and a gate voltage of the NMOS transistor based on a level of a data signal, an occurrence of a level transition of the data signal, and a direction of the level transition of the data signal.

Abstract: Apparatuses and methods for partial bit de-emphasis are provided. An example apparatus includes an output driver and control circuit. The output driver includes a pull-up circuit including one or more pull-up legs, and a pull-down circuit including one or more pull-down legs. The control circuit may be coupled to the output driver and configured to receive an input signal having a first logical value and a second logical value, and in response to determining the logical transition has occurred from the second logic value to the first logic value, cause the pull-up circuit and pull-down circuit respectively to enter a first state for a duration of a first portion of a bit period and to enter a second state for a duration of a second portion of the bit period preceding the first portion.

Abstract: A drive circuit includes a first level shift circuit, a second level shift circuit, a pre-driver, and a high-side transistor. The first level shift circuit outputs a first switch signal. The second level shift circuit outputs a second switch signal. The pre-driver includes a first switch portion configured to perform switching in accordance with the first switch signal and a second switch portion configured to output a gate signal in accordance with the second switch signal. The high-side transistor outputs a high-side output signal to an output terminal with a second power supply voltage which is fed in accordance with the gate signal.

Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

Abstract: An operational amplifier circuit is provided. The operational amplifier circuit includes a differential input stage circuit and a loading stage circuit. The differential input stage circuit includes an input circuit, a voltage maintaining circuit, and a current source. The input circuit includes a first input transistor and a second input transistor, for receiving a first and a second input signals, respectively. The voltage maintaining circuit includes a first branch circuit and a second branch circuit. The first branch circuit is coupled to the first input transistor for receiving the first input signal, and the second branch circuit is coupled to the second input transistor for receiving the second input signal. The current source is coupled to the first input transistor and the second input transistor. The loading stage circuit is coupled to the voltage maintaining circuit.

Abstract: Methods of operating an integrated circuit device, and integrated circuit devices configured to perform methods, including applying a particular voltage level to a first input of an input/output (I/O) buffer and to a second input of the I/O buffer, determining whether the I/O buffer is deemed to exhibit offset, and applying an adjustment to the I/O buffer offset while applying the particular voltage level to the first input of the I/O buffer and to the second input of the I/O buffer if the I/O buffer is deemed to exhibit offset.

Abstract: An instrumentation device having a pulse output function for preventing breakage of a switching element even if a wrong wire is connected. A calculation unit includes: a positive power supply terminal; a negative power supply terminal; a signal terminal; a control circuit; an NPN-type transistor; a feedback circuit; a PTC thermistor; and an N-channel type MOSFET. The NPN-type transistor has a collector terminal connected to the positive power supply terminal, an emitter terminal connected to the negative power supply terminal, and a base terminal connected to the control circuit. The PTC thermistor is a resettable protection element, and is connected in series to the signal terminal. The N-channel type MOSFET has a drain terminal connected to the signal terminal through the PTC thermistor, a source terminal connected to the negative power supply terminal on a downstream side of the feedback circuit, and a gate terminal connected to the control circuit.

Abstract: A power semiconductor module having switching elements includes: a collector main terminal and a collector auxiliary terminal connected to a collector potential of the switching element; a gate auxiliary terminal connected to a gate potential of the switching element; and an emitter main terminal and an emitter auxiliary terminal connected to an emitter potential of the switching element. A power converter includes a voltage dividing circuit board that generates a divided voltage obtained by dividing a voltage between the collector auxiliary terminal and the emitter auxiliary terminal and transmits to a gate driving circuit. The voltage dividing circuit board is electrically connected to the collector auxiliary terminal and the emitter auxiliary terminal. A gate driving circuit changes a driving speed of the switching element according to the divided voltage.

Abstract: The present disclosure relates to the technical field of semiconductors, and discloses a current source and a digital to analog convertor. The current source includes a current output circuit and an impedance gain circuit which is configured to increase output impedance of the current output circuit. The current output circuit includes a first PMOS transistor and a second PMOS transistor. The impedance gain circuit includes a first end, a second end, a third end which is connected to a supply voltage, and a fourth end which is connected to the ground. A source electrode of the first PMOS transistor is connected to the supply voltage, a drain electrode of the first PMOS transistor is connected to a source electrode of the second PMOS transistor and the first end of the impedance gain circuit, and a gate electrode of the first PMOS transistor is controlled by a first bias voltage.

Abstract: Systems and methods are provided for protecting a power conversion system. A system controller includes a two-level protection component and a driving component. The two-level protection component is configured to detect an output power of a power conversion system and generate a protection signal based on at least information associated with the output power. The driving component is configured to generate a drive signal based on at least information associated with the protection signal and output the drive signal to a switch associated with a primary current flowing through a primary winding of the power conversion system. The driving component is further configured to generate the drive signal corresponding to a first switching frequency to generate the output power equal to a first power threshold and generate the drive signal corresponding to a second switching frequency to generate the output power equal to a second power threshold.

Abstract: A semiconductor module including a semiconductor element, a controller, a cooler, and a temperature sensor are included. The controller is connected to the semiconductor module and controls switching operation of the semiconductor element. The temperature sensor measures a coolant temperature, which is a temperature of the coolant. The controller controls turn-off speed of the semiconductor element based on the coolant temperature. The controller increases the turn-off speed as the coolant temperature rises.

Abstract: Methods, systems, and apparatuses are described for improving the signal integrity of a differential pair of signals by mitigating a non-balanced channel deficiency. For example, signal integrity may be improved by independently shaping and/or independently controlling the slopes (e.g., the rising edge and/or falling edge) of each signal of a differential pair of signals to counteract the effects caused by non-balanced deficiencies to provide a balanced differential pair of signals (i.e., signals having symmetrical impedances, loads, etc.).

Abstract: An isolated insulated gate bipolar transistor (IGBT) gate driver is provided which integrates circuits, in-module, to support the measurements of threshold voltage, and collector-emitter saturation voltage of IGBTs. The measured gate threshold and collector-emitter saturation voltage can be used as precursors for state of health predictions for IGBTs. During the measurements, IGBTs are biased under specific conditions chosen to quickly elicit collector-emitter saturation and gate threshold information. Integrated analog-to-digital converter (ADC) circuits are used to convert measured analog signals to a digital format. The digitalized signals are transferred to a micro controller unit (MCU) for further processing through serial peripheral interface (SPI) circuits.

Abstract: A system and method may determine the operating parameters, such as voltages, of MOS transistors within a circuit design by testing or simulation, for example and may identify a MOS transistor operating with its drain voltage higher than its gate voltage in the circuit. The design system and method may substitute a smaller transistor, having a high-k dielectric layer, for the original transistor in the circuit design.

Abstract: In accordance with an embodiment, an electronic circuit includes a first transistor device, at least one second transistor device, and a drive circuit. The first transistor device is integrated in a first semiconductor body, and includes a first load pad at a first surface of the first semiconductor body and a control pad and a second load pad at a second surface of the first semiconductor body. The at least one second transistor device is integrated in a second semiconductor body, and includes a first load pad at a first surface of the second semiconductor body and a control pad and a second load pad at a second surface of the second semiconductor body. The first load pad of the first transistor device and the first load pad of the at least one second transistor device are mounted to an electrically conducting carrier.

Abstract: A configurable transceiver includes a first transmitter, an edge rate controller, a second transmitter, a subtractor, a bandwidth controller and a main controller. The first transmitter is configured to generate a first signal for transmission via a transmission link. The second transmitter is configured to generate a replica signal associated with the first signal. The edge rate controller is communicatively coupled to the first and/or second transmitter and is configured to control an edge rate parameter of the first and/or second signal. The subtractor is configured to subtract the replica signal from a signal received via the transmission link. The bandwidth controller is configured to control a bandwidth parameter of a difference signal received from the output of the subtractor. The main controller chooses edge rate and bandwidth control words per desired link rates. It can also automatically find the maximum possible link speed.

Abstract: In various embodiments, a master-slave clock generation circuit may include a first delay circuit, a second delay circuit, a first tristate inverter, and a second tristate inverter. The first delay circuit may delay a clock signal and output a slave clock signal and a delayed clock signal. The first tristate inverter may selectively invert the clock signal based on a scan enable signal. The second tristate inverter may selectively invert the delayed clock signal based on the scan enable signal. The second delay circuit may delay a signal received from the first tristate inverter, the second tristate inverter, or both, and output a master clock signal. As a result, the master-slave clock generation circuit may be configured to output a master clock signal and a slave clock signal having differing sets of relative timing characteristics depending on whether the scan enable signal is asserted.

Abstract: A GOA circuit includes GOA circuit units. Each GOA circuit has a holding module A first transistor and a second transistor in the holding module holds the voltage imposed on the first control node to be at high voltage level. Also, the transistors form a direct current passage between the first control node and a first fixed voltage at high voltage level so the voltage imposed on the first control node is not lowered due to electricity leakage. The GOA circuit unit can resolve the problem of easy leakage of electricity. When the scanning signals are output by the GOA circuit unit, the stability is highly ensured.

Abstract: The subject matter of this document can be embodied in a method that includes a voltage regulator having an input terminal and an output terminal. The voltage regulator includes a high-side transistor between the input terminal and an intermediate terminal, and a low-side transistor between the intermediate terminal and ground. The voltage regulator includes a low-side driver circuit including a capacitor and an inverter. The output of the inverter is connected to the gate of the low-side transistor. The voltage regulator also includes a controller that drives the high-side and low-side transistors to alternately couple the intermediate terminal to the input terminal and ground. The controller is configured to drive the low-side transistor by controlling the inverter. The voltage regulator further includes a switch coupled to the low-side driver circuit. The switch is configured to block charge leakage out of the capacitor during an off state of the low-side transistor.

Abstract: There is provided a drive circuit for turning on/off a power element which controls a main current flow between a first main electrode and a second main electrode in response to a drive signal applied to a control electrode. The drive circuit includes a first semiconductor switching element and a second semiconductor switching element which are connected in series and provided between the power supply terminal and the ground terminal, a third semiconductor switching element and a fourth semiconductor switching element which are connected in series with a semiconductor element, and a control circuit which controls turn-on/off of the power element by turning on/off the first to fourth semiconductor switching elements. The semiconductor element has a negative temperature characteristic.

Abstract: A bandstop filter includes a coupled line bandstop filter, a capacitor and a resistor. The coupled line bandstop filter includes a transmission line element and a shaped transmission line element. The shaped transmission line element includes a coupled line element disposed so as to electromagnetically couple with the transmission line element, and a second line element disposed so as not to be parallel with the transmission line element. The capacitor is electrically connected to the coupled line element. A portion of the received oscillating signal includes a bandstop frequency. Physical attributes of the coupled line bandstop filter, the capacitor and the resistor are such that the portion of the received oscillating signal including the bandstop frequency is attenuated.

Abstract: There is provided a drive circuit for turning on/off a power element which controls a main current flow between a first main electrode and a second main electrode in response to a drive signal applied to a control electrode. The drive circuit includes a a first semiconductor switching element and a second semiconductor switching element which are connected in series with a semiconductor element and provided between the power supply terminal and the ground terminal, third semiconductor switching element and a fourth semiconductor switching element which are connected in series, and a control circuit which controls turn-on/off of the power element by turning on/off the first to fourth semiconductor switching elements. The semiconductor element has a positive temperature characteristic.

Abstract: A semiconductor device includes: a semiconductor chip including a level shift circuit to output a high amplitude signal from an input of a logical signal, the level shift circuit including a series coupling circuit coupled to a second power supply, a control circuit coupled to the series coupling circuit for controlling the series coupling circuit based on the logical signal, and a first potential conversion circuit coupled between the series coupling circuit and the control circuit and coupled to a first power supply. The series coupling circuit includes a plurality of first MOS transistors coupled in series between the second power supply and a reference power supply, and a plurality of second MOS transistors coupled in series between the second power supply and the reference power supply in series with the plurality of first MOS transistors.