Abstract: The present invention relates to a technique capable of establishing communications between cores, which can provide a large degree of freedom of clock frequencies settable in each core, and thus providing deterministic operation, small communication latency, and high reliability. An object of the present invention is to provide a semiconductor device with high reliability, by analyzing factors affecting the performance of the semiconductor device, based on the communication histories within the semiconductor device, and reflecting the analysis back to the next generation semiconductor devices. The improved semiconductor device includes a core A for transmitting data in sync with the clock signal clkA, a core B for receiving data in sync with the clock signal clkB coincided with the rising or falling of the clock signal clkA in a constant period, and a controller for controlling communications between the core A and the core B.

Abstract: An external clock round-trips a round-trip delay block configured by a selector and a short delay array, and is made capable of corresponding to a wide frequency by generating a long delay time required for synchronization at the time of a low frequency operation. Further, when a plurality of phase comparators are disposed, in both cases where comparing phases all at once and comparing phases one after another, it is possible to complete the phase synchronization within a short time by making a delay amount variable.

Abstract: A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spectrum modulation to the clock signal. A programmable modulator is provided that generates digital values representing edge positions for edges of a clock signal based on at least one of a time-varying period value and a time-varying duty-cycle value. The programmable modulator may comprise a first circuit, called a period modulation circuit, that generates a time-varying digital period value, and a second circuit, called a duty-cycle modulation circuit, that generates a time-varying digital duty-cycle value. The time-varying period values and time-varying duty cycle values are processed to produce a digital edge position value that specifies an edge position for a clock signal.

Abstract: Input circuits connected to an external input terminal PAD via resistor elements are activated in response to the level transition of the clock signals supplied thereto for accepting input signals. In order to input signals applied to the external input terminal PAD clock signals having different phases are supplied to the respective input circuits. The cycle time of each one input circuit can be made longer by sequentially assigning the serial data supplied to the external input terminals in response to the clock signals having different clock signals. Since the input circuits are isolated from each other by means of the resistor elements, the influence of the kick back signal which occurs at first stage of each the input circuit upon the other input circuit can be made very small.

Abstract: In a synchronization circuit and a synchronization method, a first variable delay circuit generates a first pulse to be synchronized with a reference pulse, a second pulse which is leading in the phase to the first pulse, and a third pulse which is delayed in the phase from the first pulse. The reference pulse and the first pulse are compared by a first phase comparing circuit, and the reference pulse, second pulse and third pulse are compared by a second phase comparing circuit. A control voltage generating circuit forms a control voltage by giving priority to a comparison output of the second phase comparing circuit against a comparison output of the first phase comparing circuit. Delay time of the first variable delay circuit is controlled after the phases are matched by forming the control voltage with the comparison output of the first phase comparing circuit.

Abstract: A plurality of voltage controlled oscillators and a plurality of dividers are provided corresponding to a plurality of frequency bands, respectively, and a phase comparator, a charge pump, and a low pass filter are used in common for the plurality of frequency bands. A switch which selects any one of the plurality of voltage controlled oscillators, and a switch which selects any one of the plurality of dividers are provided. A controller which performs a gain control of a frequency synthesizer loop is further provided so that a gain characteristic of the frequency synthesizer loop comprised of a selected voltage controlled oscillator, selected divider, phase comparator, charge pump, and low pass filter becomes constant regardless of a selection change of the plurality of voltage controlled oscillators and the plurality of dividers.

Abstract: There is provided with a clock timing adjusting method for adjusting the difference of clock timings among a plurality of clock domains in a semiconductor integrated circuit which includes a clock generation portion capable of supplying a plurality of clocks with different phases, a plurality of clock domains for supplying clocks supplied from the clock generation portion to corresponding flip-flop groups, respectively, and a logic circuit portion having the flip-flop groups. In the clock timing adjusting method, a latency of each of the plurality of clock domains is extracted, then the phases of clocks supplied to the clock domains are determined among the plurality of clocks generated from the clock generation portion based on the extracted latencies, and the number of clock buffers is determined in order to adjust a latency difference of the plurality of clock domains which can not be adjusted by the determined clocks.

Abstract: A timing adjustment circuit and method thereof are disclosed. The timing adjustment circuit at least consists of a second timing adjustment unit, a multistage sample circuit, and a decision circuit for adjusting received timing of an output signal transmitted by a first chip and received by a second chip. The method takes advantage of the multistage sample circuit to receive a clock signal of receiving end so as to generate a plurality of sample clock signal. Later, according to the sample clock signals, sample output signals to generate a plurality of sampled signal. At last, make comparison of the sampled signals by the decision circuit in accordance with the output signals to generate a second adjustment signal being transmitted to the second timing adjustment unit for adjusting phase of a base clock to generate an adjusted receiving-end clock signal. Thus the receiving timing of the second chip to receive the output signal is adjusted.

Abstract: A clock tree distribution network for a field programmable gate array comprises an interface with a root signal chosen from at least one of an external clock signal, an internal clock signal, a plurality of phase lock loop cell output signals and programmable elements. The FPGA includes a logic array with programmable elements coupling the logic array to a programmable routing architecture and the interface. A routed clock network selects a signal from a clock signal from the interface, a local signal from the logic array through the routing architecture, Vcc or ground, and routes the selected signal to the logic array through the clock tree distribution network. A hardwired clock network selects a signal from a clock signal from the interface or a local signal from the routing architecture, and routes the selected signal to a plurality of flip-flops in the logic array through the clock tree distribution network.

Abstract: In one embodiment, a storage circuit comprises a first passgate having an input coupled to receive a signal representing a data input to the storage circuit and further having an output connected to a storage node in the storage circuit. The storage circuit also comprises a scan latch having an input connected to a scan data input to the storage circuit and further coupled to receive a scan enable input. The scan latch is configured to store the scan data input responsive to an assertion of the scan enable input, and also comprises a second passgate connected to the storage node and having an input coupled to receive the stored scan data. Each of the first passgate and the second passgate are coupled to receive respective pairs of control signals to control opening and closing of the passgates, wherein the scan enable signal controls which of the respective pairs of control signals are pulsed.

Abstract: Methods and apparatus provide a transceiver, such as a serializer/deserializer device (SerDes), with enhanced built-in self test (BIST). A built-in self test circuit is provided that decouples a clock signal used for receiving data from a clock signal used in transmitting data. This permits data tracking circuitry of a receiver to be efficiently tested with a relatively simple loop back test.

Abstract: A dual-edge-triggered clock-gated logic circuit includes; a delay clock generator operating to generate first, second, third and fourth delay clock signals in response to a clock signal, and a pulse generator operating to generate a pulse signal in response to the clock signal, the first, third, and fourth delay clock signals, and the control signal. The pulse generator operates to generate the pulse signal at the rising and falling edges of the clock signal.

Abstract: A method is presented for enabling application-level software to normalize processor clock values within a multiprocessor data processing system. A first processor number associated with a first processor is obtained such that the first processor executes one or more instructions for obtaining the first processor number. Subsequent to obtaining the first processor number, a processor clock value is obtained such that the processor clock value is associated with a processor that executes one or more instructions for obtaining the processor clock value. Subsequent to obtaining the processor clock value, a second processor number associated with a second processor is obtained such that the second processor executes one or more instructions for obtaining the second processor number. If the first processor number and the second processor number are equal, then the first processor number is used to retrieve a compensation value for a normalization operation on the processor clock value.

Abstract: A system, method, and article of manufacture for synchronizing first and second time-of-day clocks on first and second computers, respectively, are provided. The first and second computers have first and second network interface cards with third and fourth clocks, respectively, thereon. The system utilizes time stamp values generated by the third and fourth clocks to synchronize the first and second time-of-day clocks.

Abstract: A clock generator for generating an output clock signal synchronized with an input clock signal having first and second adjustable delay lines. The first adjustable delay lines is adjusted following initialization of the clock generator to expedite obtaining a lock condition following the initialization. The second adjustable delay line is adjusted after synchronization is achieved with the first adjustable delay line, or when the first adjustable delay line reaches a maximum adjustable delay. The first adjustable delay line is reset when a lock condition is initially obtained, and the second adjustable delay line is adjusted to compensate for the resetting of the first adjustable delay line.

Abstract: A phase adjustment unit adjusts the phases of a plurality of external clocks successively shifted in phase, thereby generating a plurality of internal clocks having an equal phase difference between every adjacent transition edges thereof. The internal clocks are synthesized to generate a composite clock having equal pulse intervals. Thus, even when the semiconductor integrated circuit is supplied with external clocks of lower frequencies, it is possible to operate the semiconductor integrated circuit at high speed. For example, the internal circuit can be operated and tested at high speed by using a low-cost LSI tester having a low clock frequency. This can reduce the testing cost of the semiconductor integrated circuit, allowing a reduction in chip cost.

Abstract: A clock generating circuit generates a high frequency clock having a constant duty and the same period as that of an external clock. A clock generating circuit generates a clock signal (hereinafter “the clock”) used for outputting a data signal to a data pin. The clock generating circuit includes at least a dividing portion and a clock generating portion. A dividing portion divides an internal clock signal (hereinafter “the internal clock”) generated based on an external clock signal (hereinafter “the external clock”) and outputs a plurality of divided clock signals (hereinafter “the divided clocks”). The clock generating portion performs a predetermined logical operations combining the divided clocks to generate the clock having a constant duty and the same period as the external clock.

Abstract: Clock rate matching circuitry is provided to buffer data between two clock domains that may have slightly different frequencies. To facilitate supporting a wide range of different communication protocols, the clock rate matching circuitry includes dedicated control circuitry and is also associated with other circuitry that is capable of acting as control circuitry that can be used as an alternative to at least part of the dedicated control circuitry. For example, the dedicated control circuitry may be set up to support one or several industry-standard protocols. The other circuitry (which may be, for example, programmable logic circuitry) is available to support any of a wide range of other protocols, whether industry-standard or custom.

Abstract: An off-chip driver circuit including a plurality of delay circuits, at least two of which have different delay times, in which the delay circuits receive a data signal and generate delayed data signals, respectively. The circuit also includes a plurality of off-chip drivers for respectively receiving the delayed data signals from the respective delay circuits and generating respective output signals in response to respective control signals, wherein the total number of the off-chip drivers to be activated at the same time is changed by the respective control signals which are generated in response to a desired drivability, and the activated off-chip drivers sequentially generate the output signals in response to the delay times, thereby increasing a total drivability of the off-chip driver circuit.

Abstract: A microcontroller integrated circuit with a clock controller and a processor automatically switches the source of the clock signal that clocks the processor from a failed fast external precision oscillator to a slow internal backup oscillator, then enables a fast internal precision oscillator, and finally switches to the fast internal precision oscillator. A failure detection circuit within the clock controller detects a failure of the external precision oscillator and sends an associated interrupt signal to the processor. The clock controller decouples the external oscillator from the processor and couples the backup oscillator to the processor. The microcontroller integrated circuit then enables the fast internal precision oscillator, decouples the backup oscillator, and couples the fast internal precision oscillator to the processor.

Abstract: A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization while maintaining the same output data latency. In one embodiment, this circuit is used on a bus-system to re-time data from receive-domain, clocks to transmit-domain clocks. In such a system the phase relationships between these two clocks is set by the device bus location and thus is not precisely known. By supporting arbitrary phase resynchronization, this disclosure allows for theoretically infinite bus-length and thus no limitation on device count, as well as arbitrary placement of devices along the bus. This ultimately allows support of multiple latency-domains for very long buses.

Abstract: A 40-Gb/s clock and data recovery (CDR) circuit incorporates a quarter-rate phase detector and a multi-phase voltage controlled oscillator to re-time and de-multiplex a 40-Gb/s input data signal into four 10-Gb/s output data signals. The circuit is fabricated in 0.18 ?m CMOS technology.

Abstract: In one embodiment, a method for balancing clock signals in a clock tree includes, at a register, receiving a divided input clock signal and a non-divided input clock signal and generating a first output clock signal based on the received divided input clock signal and the received non-divided input clock signal, the first output signal being associated with a first delay. The method further includes, at a delay line, receiving the non-divided input signal, delaying the non-divided input signal for a time substantially equivalent to the first delay, and generating a second output clock signal associated with a second delay substantially equal to the first delay.

Abstract: Methods, systems and computer program products are provided for synchronizing clocks in a computer network. A first node clock is synchronized to a second node clock by establishing an initial value of a virtual second node clock at the first node. The initial value may be established based on the first node clock and a timing record received from the second node. A frequency bias adjustment factor is determined for the virtual second node clock based on a plurality of clock requests from the first node and a plurality of corresponding responses from the second node spaced apart in time. The responses from the second node include the timing record based on the second node clock. A time of the virtual second node clock is provided based on the frequency bias adjustment factor responsive to requests for the virtual second node clock at a time between requests.

Abstract: Method and apparatus for data recapture from a source synchronous interface. A data signal is obtained via the source synchronous interface. A timing signal is obtained via the source synchronous interface, where the data signal and the timing signal are provided in association with one another. The timing signal is frequency divided by frequency divider to provide an enable signal. Data of the data signal is captured responsive to the timing signal and the enable signal, where the data captured is in a time domain of the timing signal. A data valid signal is generated from the enable signal and an internal clock signal, where the data valid signal is internally timed without having to determine a system level delay. The data is recaptured responsive to the internal clock signal and the data valid signal, where the recaptured data is in a time domain of the internal clock signal.

Abstract: A method and a system for configurably generating enabling pulse clocks are disclosed herein. In various embodiments, enabling pulse clocks are configurably generated for a selected one of a first and a second signaling mode, employing a configurable enabling pulse clock generator configurable to so generate the enabling pulse clocks.

Abstract: The present invention provides a method and apparatus for synchronizing signal transfers between two clock domains, where the clock domains have a gear ratio relationship. A gear ratio means that the clocks are related by a ratio, such that each clock has a different integer number of clock cycles in a common period. Also, in addition to a gear ratio relationship, the clocks may have a synchronized edge at the end of the common period. For each clock, the cycles in the common period are “colored”, i.e., identified by a number (1st, 2nd, etc.). By using the coloring technique, the appropriate clock edge to perform a data or control signal transfer can be identified. The edges are preferably chosen to minimize the latency of the transfer.

Abstract: In a semiconductor device of the present invention, a clock is not changed instantaneously but it is changed over maximum N+1/M clocks (N: integer not less than 2) by shifting delay cells in a step by step manner to make the phase state of a previous reference signal and the phase state of a present reference signal coincide with each other, whereby the clock is synchronized with the reference signal with accuracy, and the duty of the output clock is kept constant. With this semiconductor device, it is possible to prevent the duty of the clock from being discontinuous when a signal whose reference signal does not coincide with the clock is inputted and reset is made to a rising edge of this reference signal.

Abstract: A method and apparatus for a integrated circuit having flexible-ratio frequency domain cross-overs. In one embodiment, an integrated circuit has at least three cooperating frequency domains with variable operating frequencies. The integrated circuit includes cross-over logic to allow integral fraction ratio frequency domain cross-overs between more than one pair of frequency domains.

Abstract: The present invention provides an event edge synchronization system and a method of operating the same. In one embodiment, the event edge synchronization system includes: (1) a first clock zone device configured to generate an event signal based upon a first clock rate, (2) a second clock zone device configured to operate at a second clock rate, which is asynchronous with the first clock rate and (3) a synchronous notification subsystem configured to receive the event signal, synchronize the event signal to the second clock rate based upon an edge transition of the event signal and the second clock rate, and generate a synchronous notification signal therefrom.

Abstract: The clock recovery circuit includes a first oscillator and an edge detector. The first oscillator generates a plurality of clocks having different phases and a predetermined frequency. The edge detector detects two clocks, among the plurality of clocks, between edges of which an input data signal has made a transition. The first oscillator includes a plurality of delay cells connected in a ring, and outputs of the plurality of delay cells are output as the plurality of clocks. Each of the plurality of delay cells selectively delays a first-delay added input data signal or the signal output from the preceding delay cell, and outputs the selected delayed signal. The edge detector controls one delay cell among the plurality of delay cells corresponding to the result of the detection, to delay and output the first-delay added input data signal.

Abstract: A status indication detection apparatus comprises an input storage stage, an intermediate storage stage and an output storage stage. Status indications are input into the input register of the input stage and are shifted to the intermediate and to the output stage. The input and intermediate storage stages operate with a first reference clock in a first clock domain whilst the output storage stage operates with a different second reference clock in the second clock domain. In accordance with the invention a reading out of the intermediate register of the intermediate stage is only possible during the generation of a hold signal which keeps a current status indication in the intermediate storage stage and blocks a transfer of a new status indication from the input stage.

Abstract: A clock generation system for generating a first-, a second-, and a third-reference frequency clocks having respective frequencies having predetermined ratios to the reference frequency of a reference clock, using PL circuits in such a way that the clocks have sufficient S/N ratios in spite of the S/N ratio limitation by the noise floor. A first reference frequency clock is supplied to a first PLL circuit to generate an intermediate-frequency clock having an intermediate frequency having a predetermined ratio to the reference clock. The intermediate-frequency clock is supplied to a second and a third PLL circuits to generate a second and a third reference frequency clocks having frequencies respectively having a second and a third ratios to the intermediate frequency, respectively.

Abstract: Disclosed herein are circuits in which a plurality of clock signals are generated by corresponding clock generators from one or more common clock references. The clock generators accept control values that specify the phases of the individual clocks. The actual phase of each clock signal potentially varies during operation, and the phases of the various clock signal are generally independent of each other. To detect or measure phase relationships, the disclosed circuits evaluate or compare the control values using arithmetic logic.

Abstract: Clock signal control circuitry including a selector for selecting between a first clock signal and an inverse of the first clock signal and a phase detector for determining a phase relationship between the first clock signal and the second clock signal and in response causing the selector to select between the first clock signal and the inverse of the first clock signal.

Abstract: A method for adjusting the relative phases of two signals includes receiving first and second signals, which may, for example, be derived from a differential clock signal. A duty cycle error between the first signal and the second signal is detected by comparing a phase component of the first signal with a phase component of the second signal. This duty cycle error can then be corrected by delaying the second signal by an amount based upon a result derived from the comparing.

Abstract: According to an aspect of the invention, there is provided a phase synchronous circuit generating an output signal synchronized with an input signal. The phase synchronous circuit comprises an output circuit putting out an output signal according to an input clock signal, a selection circuit selecting a clock signal applied to the output circuit from multiphase clock signals such that the output circuit puts out an output signal synchronized with the input signal. The internal delay in a phase synchronous circuit using a multiphase clock signal can be efficiently compensated and an output signal synchronized with the reference signal can be generated.

Abstract: A method and circuit configuration for synchronous resetting of an multiple clock domain circuit such as an Application Specific Integrated Circuit (ASIC) combine an asynchronous reset signal with a functional signal using a clocked reset tree of synchronous logic elements.

Abstract: A clock synchronization circuit for synchronizing a first clock signal and a second clock signal for data transfer from a first function block, which is clocked by the first clock signal, to a second function block which is clocked by the second clock signal, where the clock synchronization circuit has a sampling unit for sampling the second clock signal using the first clock signal in order to generate samples and edge detection values of the sampled second clock signal, a logic circuit for outputting the generated edge detection values as a reconstructed clock signal and generating an Edge-too-Early signal and an Edge-too-Late signal; and a signal delay circuit, which delays the reconstructed second clock signal on the bases of the Edge-too-Early signal or the Edge-too-Late signal.

Abstract: The present invention demonstrates a method and circuit where a plurality of phase clocks from a “frequency lock only” PLL are used to sample an input clock CLKIN. This results in a series of signals from which the phase clock most in synchronization with CLKIN can be determined and presented to the output CLKOUT. If used for data sampling, a phase clock that lags the phase clock most in synchronization may be selected to appear at CLKOUT. This guarantees that sampled data are static during sampling. This system is less complex and consumes minimal power over systems using variable delay circuits.

Abstract: In an oversampling clock recovery circuit comprising first through fourth phase comparators (PD1 to PD4) and a majority circuit (10), DOWN signal output terminals (DN2(out), DN3(out)) of the second and the third phase comparators are connected to UP signal input terminals (UP3(in), UP4(in)) of the majority circuit and UP signal output terminals (UP3(out), UP4(out)) of the third and the fourth phase comparators are connected to DONW signal input terminals (DN2(in), DN3(in)) of the majority circuit.

Abstract: A synchronization interface transfers multi-bit digital data or signal between multiple clocked logic domains while maintaining data or signal integrity. When deployed in a processor-based system, in one embodiment, a plurality of data units may be received at a source location in a first clocked domain. To control writing of the plurality of data units from the source location to a target location in a second clocked domain, an enable signal may be detected. This enable signal may be synchronized with respect to the second clocked domain. Finally, in response to the synchronized enable signal, the plurality of data units may be transferred from the first clocked domain to the target location in the second clocked domain. The synchronization interface may comprise a data path to capture the multi-bit digital data or signal based on a control logic implementing a mechanism (e.g.

Abstract: There is disclosed a data recovery (DR) circuit including an over sampling (OS) circuit, a transition detection (TD) circuit and a sample selection/data alignment (SSDA) circuit. A multiphase clock generating circuit delivering n phases is coupled to each of these circuits. The OS circuit over samples the received digital data stream and produces n sampled signals at each clock period. The TD circuit is configured to detect a data transition (if any) and to generate n select signals, only one of which is active and represents a determined delay with respect to the transition position, indicating thereby which over sampled signal is the best to be retained. The SSDA circuit is configured to generate the recovered (retimed) data signal that is aligned with a predefined phase of the multiphase clock signal. The data recovery circuit is well adapted to high speed serial data communications between integrated circuits/systems on digital networks.

Abstract: A circuit, system, and method are provided for generating edge-aligned, complementary output signals from complementary input signals. The output and input signals can, according to one example, be clock signals. The circuit, system, and method can use the rising edges of the complementary pair of input signals to trigger transitions on the complementary pair of output signals. More specifically, the rising edge of a true input clock signal will trigger the rising edge of the true output clock signal and the falling edge of the inverted output clock signal. A rising edge of the inverted input clock signal will trigger the falling edge of the true output clock signal, and the rising edge of the inverted output clock signal. Moreover, the circuit, system, and method ensures that at any time only one transition occurs on the active inputs of a final logic stage of the clock generation circuit.

Abstract: A clock resynchronizer includes a write circuit and a read circuit. The write circuit stores input data in accordance with a first clock associated with the input data. The read circuit outputs data to be output out of the data stored in the write circuit, in accordance with a second clock. The read circuit also outputs a signal acquisition permitting signal indicating that the data to be output is valid. The read circuit outputs no signal acquisition permitting signal when the data to be output is not output.

Abstract: The present invention provides an apparatus for signaling that a predetermined time value has elapsed, having a device for acquiring and storing the amplitude value of a clock signal at an acquisition instant in the temporal profile of the clock signal. A device is provided for continuously comparing the acquired and stored amplitude value of the clock signal with an instantaneous amplitude value of the clock signal and for outputting a comparison signal which has a first logic state if the instantaneous amplitude value of the clock signal is less than the stored amplitude value and has a second logic state if the instantaneous amplitude value of the clock signal is greater than the stored amplitude value.

Abstract: The invention refers to a clock distortion detection method, and a clock distortion detector including a first input for receiving a first clock signal, a second input for receiving a second clock signal, and at least one mirror delay element.

Abstract: An information processing apparatus is constructed by a system PLL, a first unit, a second unit, and a system board on which they are mounted. A delay setting circuit in which a variation and delay elements (a gate delay and a line delay) which are equivalent to those of a clock tree circuit for a gate have been set at the designing stage is provided on a signal line of a system clock in the first unit to the second unit. A delay setting circuit in which a variation and delay elements which are equivalent to those of the clock tree circuit for the gate have been set at the designing stage is provided on a signal line of a clock gate signal to the second unit.

Abstract: A double data rate memory controller is provided with a plurality of data and strobe pads, means for receiving data and strobe signals via said pads at 1× double data rate memory speed, and means for receiving data and strobe signals via said pads at M× double data rate memory speed (M?2).

Abstract: A technique of processing an input signal having an input signal phase is disclosed. The technique includes determining a number of transitions of the input signal within a period having a start and an end. The technique includes determining a relative beginning phase of the input signal at the start of the period, which includes generating a first reference signal having a first reference signal frequency and a first reference signal phase synchronized with the start of the period, and detecting a first time interval required for the input signal phase to have a first specified relationship to the first reference signal phase. The technique includes similarly determining a relative ending phase of the input signal at the end of the period. The technique includes determining an input signal temporal characteristic from the number of transitions and the relative beginning phase and the relative ending phase.