Abstract: Power switching systems often benefit from controlling the instant at which the power devices change state so as to minimize dissipation in these devices. Such systems often require fairly tight tolerances on reactive components and a relatively narrow frequency operating range to be certain these switching times occur as intended. This invention defines a system that can adapt the required switching instant over very wide changes in the reactive components.

Abstract: An apparatus for transferring data in a non-spread domain to a spread domain. The apparatus comprises a first-in-first-out (FIFO) memory; a write pointer generator adapted to generate a write pointer for writing data into the FIFO memory in response to a non-spread clock signal; a spread-clock generator adapted to generate a spread clock signal based on the non-spread clock signal; a read pointer generator adapted to generate a read pointer for reading data from the FIFO memory in response to the spread clock signal; and a controller adapted to control the spread-clock generator in response to the read and write pointers indicating predetermined potential data overflow or underflow of the FIFO memory.

Abstract: A digital phase-locked loop (DPLL), a supporting digital frequency integrator, and a method are provided for deriving a digital phase error signal in a DPLL. A digital frequency integrator periodically accepts a digital tdcOUT message from a Time-to-Digital Converter (TDC) representing a measured ratio of a reference clock (Tref) period to a synthesizer clock (Tdco) period. Also accepted is a digital message selecting a first ratio (Nf). In response, a digital phase error (pherr) message is periodically supplied that is proportional to an error in phase between the reference clock and the (synthesizer clock*Nf).

Abstract: A phase lock loop (PLL) circuit having a phase frequency detector (PFD), a coarse tune low-pass filter module, a voltage control oscillation (VCO) module and a feedback loop is provided. The PFD compares phases and frequencies of an input signal and a feedback signal. The coarse tune low-pass filter module is coupled to the PFD and used for low-pass filtering a control signal with a gradually narrowed bandwidth to generate a filtered signal. The control signal indicates the comparison result of the input signal and the feedback signal. The VCO module has a first VCO gain and a second VCO gain, and generates an output signal according to the control signal and the filtered signal. The feedback loop provides the feedback signal to the PFD according to the output signal.

Abstract: A fractional-N frequency synthesizer having a cancellation system for phase discontinuity due to loop gain changes may include a phase detector, a current-changeable charge-pump, a loop filter for providing a tuning signal, a voltage-controlled oscillator (VCO) controlled by the tuning signal for providing a VCO output signal, a divider for providing a divided VCO signal, a modulator for generating a modulating signal for fractional-N functionality, wherein the phase detector has a first input for receiving a reference signal oscillating at a reference frequency; a second input for receiving the divided signal; and the phase detector and charge-pump is configured to compare a phase of the first input and a phase of the second input, and generate a charge-pump current on and off, featuring that the cancellation system is implemented inside the modulator having an additional input defined by the changeable charge-pump current values.

Abstract: A lock detector for a phase lock loop (PLL) includes: first and second pulse width extenders, performing pulse width extension on first and second pulses for generating third and fourth pulses, respectively; first and second delay circuits, delaying the third and the fourth pulses into first and second sampling clocks, respectively; and a cross-sampling circuit, sampling the third pulse based on the second sampling clock and sampling the fourth pulse based on the first sampling clock to indicate whether the PLL is locked.

Abstract: A clock generator is disclosed that includes a lock detector. The lock detector is configured to generate a lock signal based on control signals of a phase lock loop circuit that generates an output clock of a desired frequency that is phase locked to a reference clock. The lock detector generates a mismatch signal based on a comparison between the phases of the reference clock and the output clock to generate a compare result. The lock detector delays the compare result by a time period Td and AND the delayed compare result with the compare result to generate the mismatch signal. The lock detector includes a lock-counter that counts a number of reference clock cycles when the mismatch signal remains at 0. The lock signal indicates that a lock-state is achieved when the number of counted reference clock cycles equals a set-value.

Abstract: A phase locked loop circuit is provided. The PLL circuit receives an input clock signal and generates an output clock signal according to internal clock signals with phase shifting which are generated according to the input clock signal. The PLL circuit includes a selector, a dividing unit, a converter, a low pass filer (LPF), and a modulator. The selector selects one of the internal clock signals to serve as a selection clock signal according to an enable signal. The first dividing unit performs dividing operations to the selection clock signal to generate the output clock signal and a feedback clock signal. The converter detects phase difference between the feedback clock signal and a reference clock signal to generate a detection signal. The LPF performs a filtering operation to the detection signal to generate a filtering signal. The modulator modulates the filtering signal to generate the enable signal.

Abstract: A time correction circuit includes: a time-measurement device that measures a time period; a receiver device that receives electromagnetic wave based on a first baseband signal, the first baseband signal including time information concerning time and being encoded by a pulse width modulation method, and outputs a second baseband signal based on the electromagnetic wave received; and an asynchronous circuit that corrects the time based on the second baseband signal, wherein the asynchronous circuit executes a specified process to retrieve the time information from the second baseband signal based on the time period measured, at least one of when the second baseband signal changes from high level to low level and when the second baseband signal changes from low level to high level, and assumes a standby state after executing the specified process.

Abstract: A delay locked loop (DLL) circuit includes an analog DLL core and a digital DLL core. The analog DLL core receives an input clock signal of a first operating frequency. The digital DLL core receives an input clock signal of a second operating frequency equal to or lower than the first frequency. The analog and digital DLL cores operate selectively. The DLL core also includes a selection circuit configured to select one of the first and second DLL cores. The selection circuit may operate in response to a detection signal from a frequency detector which detects the frequency of the input clock signal. The selection circuit may also operate in response to a column address strobe writing latency signal that indicates frequency information of the input clock signal.

Abstract: The present invention relates to a PLL that utilizes a phase interpolation by a reference clock. The PLL includes a phase-interpolated controller for generating a phase-interpolation control signal; a phase/frequency detector for detecting a phase difference between a second reference clock and a feedback clock and outputting a phase error signal to represent the phase difference; a loop filter for filtering the phase error signal to generate a first control signal; a phase-interpolated oscillator for generating an output clock under a control by the phase-interpolation control signal and the first control signal; and a divide-by-N circuit for dividing down the output clock by a factor of N to generate the feedback clock, where N is an integer.

Abstract: A method to operate a digital phase locked loop (DPLL) in which the DPLL includes a phase-frequency detector that compares the frequency of a reference signal with a feedback signal to generate an error signal. The error signal is used to generate first and second control words. Binary current control word bits and thermometric current control word bits are generated using the first and second control words, respectively. A binary controller switches a first set of binary current sources prior to a frequency lock being achieved using the binary current control word bits and the thermometric current control word bits are held at a predetermined value. After achieving the frequency lock, the binary current sources are fixed and then a thermometric controller switches a second set of thermometric current sources using the thermometric current control word bits.

Abstract: A phase lock loop (PLL) featuring automatic stabilization is provided, in which a first charge pump is coupled to a driving control signal to generate a first current, a filter with a zero-point path and the first charge pump are coupled at a first node, and a current adjustment circuit adjusts a current on the first node according to a voltage difference in the zero-point path.

Abstract: A frequency divider includes a least significant (LS) stage, multiple cascaded divider stages, and an output stage. The LS stage receives an input signal, a program bit and a first mode signal, and generates a first frequency-divided signal and an output mode signal. Each of the plurality of divider stages divides the frequency of an output of an immediately previous stage by a value specified by a corresponding program bit and a corresponding mode signal. A first divider stage in the plurality of divider stages is coupled to receive the first frequency-divided signal and to generate the first mode signal. The output stage receives the output mode signal and a control signal, and generates an output signal by dividing a frequency of the output mode signal by two if the control signal is at one logic level. The output stage forwards the output mode signal without division otherwise.

Abstract: A rapidly adjustable local oscillation (LO) module for use in a radio transmitter or a radio receiver includes an oscillation generating module and a high frequency switching module. The oscillation generating module is operably coupled to generate a plurality of local oscillations. The high frequency switching module is operably coupled to, for a first one of a plurality of transmission paths, provide one of the plurality of local oscillations when a first transmission path selection indication is in a first state and provide another one of the plurality of local oscillations when the first transmission path selection indication is in a second state and, for a second one of the plurality of transmission paths, provide the one of the plurality of local oscillations when a second transmission path selection indication is in a first state and provide the another one of the plurality of local oscillations when the second transmission path selection indication is in a second state.

Abstract: According to one embodiment, a PLL circuit generates a first signal of 1/m times from a reference clock and a second signal of 1/n times from an output of an oscillator, obtains a quantized phase difference corresponding to a shift amount between the both signals, integrates the phase difference, predicts a control value for the oscillator based on the integrated value, converts the predicted control value into an analog value. Sequential integration is performed for the phase difference until the polarity of the phase difference is reversed from negative to positive and then from positive to negative again, or until the polarity is reversed from positive to negative and then from negative to positive again, a predictive weight value is generated by multiplying the integrated value by a predictive coefficient value of optional ratio, and the control value is obtained by adding the predictive weight value to the integrated value.

Abstract: A loop filter having a first node on which to receive an input signal to the loop filter, a second node on which to provide an output signal of the loop filter, and a cascade arrangement of at least a first circuit that generates a zero, a second circuit that generates a first pole, and a third circuit that generates a second pole to form a passive loop filter of at least 3rd order. The cascade arrangement includes a first signal path coupling the first node to the second node, such that the first circuit is coupled to the first node through the second circuit and the third circuit. Further, the loop filter includes at least one transistor circuit, and a second signal path coupled in parallel to the first signal path at the first node and coupled to the second node through the transistor circuit.

Abstract: A method and apparatus for tuning a phase of a data clock signal having a different frequency than a main clock signal. The method of tuning includes coarse tuning by receiving the data clock signal, dividing the data clock signal to generate a frequency-divided clock signal having a same frequency as the main clock signal, repeatedly shifting the frequency-divided clock signal to generate multiphase frequency-divided clock signals at a predetermined phase interval, comparing a phase of each of the multiphase frequency-divided clock signals with a phase of the main clock signal, and determining a phase shift amount based on a comparison result, and fine tuning by comparing a phase of a multiphase frequency-divided clock signal corresponding to the phase shift amount with the phase of the main clock signal and adjusting the phase of the data clock signal by a predetermined phase step based on the comparison result.

Abstract: A phase locked loop includes a phase lock unit configured to compare a phase of a reference clock with a phase of a feedback clock and to generate an internal clock based on the comparison; a delay lock unit configured to compare the reference clock with the internal clock, and to generate the feedback clock which is delayed in response to a control voltage based on the comparison; and a start voltage enable unit configured to receive an enable signal and to apply a start voltage as the control voltage in response to the enable signal.

Abstract: A circuit including a first circuit configured to receive an input signal and first, third and fifth phase clocks of a clock, and generate a first early signal indicating the clock is earlier than the input signal and a first late signal indicating the clock is later than the input signal. The circuit further includes a second circuit configured to receive an input signal and second, a fourth and sixth phase clocks of the clock, and generate a second early signal indicating the clock is earlier than the input signal and a second late signal indicating the clock is later than the input signal. The circuit further includes a third circuit configured to generate a first increase signal. The circuit further includes a fourth circuit configured to generate a first decrease signal.

Abstract: A method of controlling a power control circuit includes enabling a power cutoff signal when a delay locking operation of a Delay Locked Loop (DLL) circuit is completed, disabling the power cutoff signal for a predetermined time, and detecting a phase difference between a reference clock and a feedback clock to re-determine, on the basis of the detection result, whether or not to enable the power cutoff signal.

Abstract: A phase lock loop frequency synthesizer includes a phase rotator in the feedback path of the PLL. The PLL includes a phase detector, a low pass filter, a charge pump, a voltage controlled oscillator (“VCO”), and a feedback path connecting output of the VCO to the phase detector. The feedback path includes a phase rotator connected to the output of the VCO and to an input of a frequency divider. Coarse frequency control is implemented by adjusting the input reference frequency to the phase detector or by adjusting the divider ratio of the frequency divider. Fine frequency control is achieved by increasing or decreasing the rotation speed of the phase rotator. The phase rotator constantly rotates phase of the VCO output, thereby causing a frequency shift at the output of the phase rotator.

Abstract: One embodiment relates to an integrated circuit including a first strip of phase-locked loop (PLL) circuits on a first side of the integrated circuit, and a second strip of PLL circuits on a second side of the integrated circuit which is opposite from the first side. The PLL circuits in the first and second strips may be configured by programming the integrated circuit. Another embodiment relates to an integrated circuit including a plurality of phase-locked loop (PLL) circuits and a plurality of physical media attachment (PMA) triplet modules adjacent to the plurality of PLL circuits. Each PMA triplet module includes first, second and third channels. The first and third channels are arranged for use as receiving channels, and the second channel is arranged to be configurable as either a receiving channel or a clock multiplication unit. Other embodiments and features are also disclosed.

Abstract: A phase-locked loop includes: a voltage-controlled oscillator (VCO) system receiving one or more control signals and in response thereto generating a PLL output signal; a plurality of phase detectors for comparing a reference signal having a reference frequency to a PLL feedback signal having a PLL feedback frequency derived from the PLL output signal, and in response thereto to output a comparison signal; and a plurality of signal processing paths each connected to an output of a corresponding one of the phase detectors for outputting a phase detection output signal. The signal processing paths have different frequency responses from each other. In operation only one of the phase detectors is activated, and a switching arrangement selectively switches between outputs of the signal processing paths to select the phase detection output signal from the activated phase detector to generate the control signal(s) for the VCO system.

Abstract: A phase selector including a plurality of buffers, a multiplexer, a first inverter, and a selecting circuit is provided. Each of the buffers provides a clock signal, and the clock signals have different phases. The multiplexer selectively outputs one of the clock signals as a switch signal according to a first control signal, wherein the first control signal is first portion of bits of a selecting signal. The input terminal of the first inverter receives a second control signal, wherein the second control signal is second portion of bits of the selecting signal, and the output terminal of the first inverter outputs an inverted signal. The selecting circuit transmits the second control signal of the selecting signal or the inverted signal to the output terminal of the phase selector according to the logic state of the switch signal.

Abstract: A communication system includes a phase-locked loop that maintains synchronization of a reception signal. The phase-locked loop includes a loop filter that has a circuit configuration m for an m-th order phase-locked loop including a circuit configuration n for an n-th order phase-locked loop (m>n), and a switching section that switches circuit configurations, which are activated in the loop filter, between the circuit configuration n and the circuit configuration m.

Abstract: A digital phase lock loop circuit, where under certain conditions the phase error is derived from phase comparison between a reference clock edge and the next oscillator clock edge rather than a feedback clock edge. This technique can be used to significantly reduce digital phase lock loop circuit power by disabling feedback divider and sync FF once initial frequency lock is established, provided phase jitter of digital phase lock loop circuit is low enough so that there is no cycle slip. This technique can also be used to multiply the effective reference clock frequency of digital phase lock loop circuits to increases the loop bandwidth, thus reducing the phase noise. Both the applications of this technique can be combined in some circuits.

Abstract: A frequency synthesizer comprises a VCO group; a phase comparator; and a loop filter. Each VCO includes a varactor and a capacitor bank including a plurality of weighted capacitance elements, and a plurality of switches turned ON and OFF based on a control signal. Also provided a temperature compensation including a varactor correction potential generation circuit, a correction potential generation circuit for parasitic capacitance of the capacitor bank, a variable gain amplifier in which weighting processing, based on a control signal of the capacitor bank, is performed on an output potential of the correction potential generation circuit, and an adder circuit that adds the output voltage of the correction potential generation circuit of the varactor and output voltage of the variable gain amplifier, and the varactor of the VCO is controlled by output (correction potential) of the adder circuit.

Abstract: A method and a circuit are described for recovery of video clocks for a DisplayPort receiver. The disclosure includes two clock dividers, a direct digital synthesis (DDS), a fixed multiplier Phase-Locked Loop (PLL) on a DisplayPort video system. A DisplayPort receiver link clock is divided to a lower frequency as the input of the DDS which can lower the performance requirement on a DDS circuit. The output from a time stamp value indirectly controls a direct digital synthesis device, which then drives a PLL to generate the recovery clock signal. The technique is suitable for implementation on an integrated circuit and Field Programmable Gate array system.

Abstract: A delay locked loop operates over a wide range of frequencies and has high accuracy, small silicon area usage, low power consumption and a short lock time. The DLL combines an analog domain and a digital domain. The digital domain is responsible for initial lock and operational point stability and is frozen after the lock is reached. The analog domain is responsible for normal operation after lock is reached and provides high accuracy using smaller silicon area and low power.

Abstract: A digital loop filter includes a fine control circuit and a coarse control circuit. The fine control circuit adjusts a phase of a feedback clock signal by a first phase adjustment in response to a first phase error signal that indicates a sign of a phase error between a reference clock signal and the feedback clock signal. The coarse control circuit adjusts the phase of the feedback clock signal by a second phase adjustment in response to a second phase error signal. The second phase adjustment is larger than the first phase adjustment. The second phase error signal indicates a magnitude of a phase error between the reference clock signal and the feedback clock signal.

Abstract: There is provided a PLL circuit including a first loop filter and a second loop filter, which includes a current signal generation circuit that includes a first output driver that generates a first current signal to be output to the first loop filter and a second output driver that generates a second current signal to be output to the second loop filter, and a control circuit that selects which of the first output driver and the second output driver is to be activated.

Abstract: An oscillation frequency control circuit controls a second oscillation circuit, which generates and outputs a second clock signal of a second frequency according to a received control signal, to control the second frequency. The oscillation frequency control circuit includes a frequency difference detection circuit unit configured to detect a difference between a predetermined first frequency of a first clock signal generated by an external first oscillation circuit and the second frequency, and generate and output an output signal indicating a detection result, and a frequency control circuit unit configured to control, according to the output signal of the frequency difference detection circuit unit, the second oscillation circuit to control the second frequency of the second clock signal to make an absolute value of the difference between the first frequency and the second frequency greater than a predetermined value.

Abstract: A method is for detecting locking of a phase-locked loop that generates an output signal and includes a phase comparator receiving, as an input, a reference signal and a second signal based upon the output signal. A time window having a duration of at least two periods of a third signal based upon the output signal, and located about a payload edge of the second signal, is generated. A first comparison of the reference signal and the second signal at a first payload edge of the third signal within the time window and on a first side of the payload edge of the second signal is performed. A second comparison of the reference signal and the second signal at a second payload edge of the third signal within the time window and on a second side of the payload edge of the second signal is then performed. Locking of the phase-locked loop based upon the reference signal and the second signal being equal during the first and second comparisons is detected.

Abstract: A clock circuit includes a frequency or phase comparator for receiving a reference clock signal, an LC VCO coupled to the comparator, a feedback divider coupled between the LC VCO and the comparator, a clock distribution chain coupled to the feedback divider and the first VCO, and a DLL or injection-locked ring-VCO coupled to the clock distribution chain for providing a plurality of phased output clock signals.

Abstract: A compensating DFLL (CDFLL) is disclosed that utilizes temperature readings at regular intervals in combination with production characterization data of a reference oscillator to compensate for frequency drift and nominal frequency error. In some implementations, the CDFLL selects a calibration value that is not optimal for frequency accuracy to minimize accumulated frequency error over time. More particularly, during a calibration run, mismatch between an ideal frequency and an actual frequency is measured, and the measurement is used as a starting point for a next calibration run, such that the accumulated frequency error is averaged almost to zero over time.

Abstract: A locked loop may have an adjustable hysteresis and/or a tracking speed that can be programmed by a user of an electronic device containing the locked loop or controlled by an integrated circuit device containing the locked loop during operation of the device. The looked loop may include a phase detector having a variable hysteresis, which may be coupled to receive a reference clock signal and an output clock signal from a phase adjustment circuit through respective frequency dividers that can vary the rate at which the phase detector compares the phase of the output clock signal to the phase of the reference clock signal, thus varying the tracking speed of the loop. The hysteresis and tracking speed of the locked loop may be programmed using a variety of means, such as by a temperature sensor for the electronic device, a mode register, a memory device command decoder, etc.

Abstract: A digital time base generator and method for providing a first clock signal and a second clock signal in which a base clock signal having a base frequency is generated to provide two clock signals of slightly different frequencies with defined time or phase delay. Here, the base frequency is divided by a first integer to produce a first auxiliary signal, the frequency of the first auxiliary signal is multiplied by a factor to obtain the first clock signal, the base frequency is further divided by a second integer to produce a second auxiliary signal, and the frequency of the second auxiliary signal is multiplied by the factor to obtain the second clock signal.

Abstract: A first current source supplies a first charge amount responsive to a first pulse signal from the phase frequency detector and a second current source supplies a second charge amount according to a fixed value and a variable value. The variable value corresponds to a phase difference between a first feedback clock signal and a hypothesized feedback clock signal with reduced quantization noise. The first and second charge amounts are of opposite polarity. A single set of first and second current sources perform the functions of charge pump and noise reduction DAC.

Abstract: A method for the recovery of a clock signal from a data signal is provided where the edges of the signals are each represented as a chronologically-ordered sequence of timing points. In one procedural stage, a plurality of timing points of the data signal are processed in parallel as follows: resolving the timing points of the data signal by a nominal clock pulse; estimating the bit-period deviations for the adjusted timing points; and injecting the nominal clock pulse to the estimated bit-period deviations.

Abstract: Provided is a signal generating apparatus that generates an output signal having a designated phase, comprising a phase difference detecting section that outputs a control signal corresponding to a phase difference between a reference signal having a prescribed period and the output signal; an oscillating section that generates a periodic signal having a frequency corresponding to the control signal; and a phase shifting section that outputs the output signal to have a phase that is shifted from the phase of the periodic signal by a designated phase amount.

Abstract: A communication terminal includes first and second transmitters, which are coupled to produce respective first and second Radio Frequency (RF) signals that are phase-shifted with respect to one another by a beamforming phase offset, and to transmit the RF signals toward a remote communication terminal. The terminal includes a reception subsystem including first and second receivers and a phase correction unit. The first and second receivers are respectively coupled to receive third and fourth RF signals from the remote communication terminal. The phase correction unit is coupled to produce, responsively to the third and fourth RF signals, a phase correction for correcting an error component in the beamforming phase offset.

Abstract: An apparatus including a multiplexer configured to provide an output clock selected from a source clock, a destination clock, and a transition clock is provided. The apparatus further includes a phase difference calculation module configured to calculate a phase difference between the source clock and the destination clock and a clock generation module configured to generate a plurality of clocks. The apparatus further includes a clock selection module configured to select one of the plurality of clocks as the transition clock and a control circuit configured to provide: (1) a signal to the clock selection module for selecting one of the plurality of clocks as the transition clock based on the phase difference between the source clock and the destination clock and (2) a signal to the multiplexer to provide as the output clock one of the source clock, the destination clock, or the transition clock.

Abstract: The present invention relates to a gigitaol phaselocked loop DPLL (300, 400) having a phase-to-digital P2D (60) with an enhanced bang-bang phase detector BBPD. Such a P2D (60) comprises a BBPD (62), an additional digital circuit (200) including a sign detector (210), a counter (220) and a mapping function (230), and a summer block (64). During the locking process, the BBPD (62) may-output a repeating value, namely a string of data bits of same polarity value either “+1” or “?1”. The polarity sign is detected by the sign detector (210), and the data string length is determined by the counter (220) that is reset to zero whenever the BBPD output changes sign. The mapping function (230) is configured for mapping the data string length in input to the phase correction level in output Its output is added to that of the BBPD (62) through the summer block (64), such that the phase correction level is increased to enhance the locking process whenever a data string is detected.

Abstract: A variable delay circuit applies a variable delay that corresponds to an analog signal to a reference clock so as to generate a delayed clock. A phase detection unit detects the phase difference between the delayed clock and the reference clock, and generates a phase difference signal having a level that corresponds to the phase difference. A counter performs a counting up operation or a counting down operation according to the level of the phase difference signal. A digital/analog converter converts the count value of the counter into an analog signal, and supplies the count value thus converted to the variable delay circuit.

Abstract: A phase lock loop includes a quantization circuit that generators an out of phase noise cancellation signal from an error in a delta-sigma modulator and applies the noise cancellation signal to the charge pump. The quantization circuit includes a digital-to-analog differentiator. The digital-to-analog differentiator may be, for example, a single-bit first-order digital-to-analog differentiator, a single-bit second-order digital-to-analog differentiator, or a full M-bit binary-weighted digital to analog differentiator.

Abstract: There is provided a frequency synthesizer. The frequency synthesizer includes a frequency oscillator adjusting an output frequency according to a control bit; a programmable divider having a preset minimum division ratio, the programming divider dividing the output frequency of the frequency oscillator at a variable division ratio; a counter unit receiving an output signal of the programmable divider and a reference frequency to generate a count value by counting rising edges of the output signal of the programmable divider during one cycle of the reference frequency, and outputting a first hit signal when the count value is 1, and outputting a second hit signal when the count value is 2; and a phase detection unit outputting a control bit obtained by subtracting a fractional error of the output signal of the programmable divider from a fractional error at a locked phase obtained from the count value and the reference frequency.

Abstract: A PLL circuit includes: the number-of-accumulated clocks detecting portion detecting the number of accumulated clocks of an oscillation circuit as a digital value; a periodicity detecting portion detecting periodicity of a digital value of a fractional portion of the number of accumulated clocks of the oscillation circuit with a first reference clock as a reference; a corrected value calculating portion calculating a corrected value; and an adding portion adding the corrected value to the fractional portion of the number of accumulated clocks with the first reference clock from the starting points of the periods of the periodicity.

Abstract: A differential transmitter and an auto-adjustment method of data strobe thereof are provided. The differential transmitter includes a phase-detecting unit, a switching unit, a rising edge strobe unit, and a falling edge strobe unit. The phase-detecting unit detects a phase relation between a clock signal and a data signal to outputs a detection result. The rising edge strobe unit latches the data signal at a rising edge of the clock signal, and converts a latching result to a first differential output signal. The falling-edge-strobe unit latches the data signal at a falling edge of the clock signal, and converts a latching result to a second differential output signal. The switching unit determines whether to switch the clock signal and data signal to the rising edge strobe unit or to the falling edge strobe unit according to the detection result.

Abstract: Adjusting a phase locked loop (PLL) clock source to reduce wireless communication (e.g., radio frequency (RF)) interference within a device. The PLL may be included in a high speed serial interface, e.g., coupled to a display, and may be initially driven by a first clock. Later, when a second clock is available and aligned with the first clock, the PLL may be driven by the second clock. The second clock may be configured to change its frequency over time such that the PLL does not lose lock and also does not interfere (or reduces interference) with wireless communication of the device. For example, the second clock may be programmable or may dynamically vary its operating frequency, thereby reducing its interference with the wireless communication of the device.