Abstract: The present invention provides an apparatus and method for a frequency adaptive level shifter circuit. The frequency adaptive level shifter circuit includes a first inverter, a second inverter coupled to the output of the first inverter, a capacitor coupled to the output of the second inverter, and a resistor coupled to the output of the capacitor. The frequency adaptive level shifter circuit further includes a transistor coupled to the output of the resistor, wherein the transistor has a gate connected to a reference voltage, a third inverter coupled to the output of the capacitor, and a fourth inverter coupled to the output of the third inverter and the transistor and outputting the signal.

Abstract: A frequency locking method, for locking an output signal outputted from a frequency locking circuit to a target frequency, comprising: (a) detecting an output frequency of the output signal, wherein the output signal is generated according to an oscillating frequency of a controllable oscillator; (b) computing a frequency difference between the output frequency and the target frequency; (c) utilizing a controllable factor adjusting device to provide and to adjust a normalization factor according to the frequency difference, to anticipate a gain of the controllable oscillator and to provide a control signal related with the normalization factor and the frequency difference, wherein the output frequency is related with a product of the normalization factor and the gain of the controllable oscillator; and (d) controlling the controllable oscillator according to the control signal, such that the output frequency approaches to the target frequency.

Abstract: A delay lock loop comprising: a first delay loop, for delaying an input signal to generate a first output signal; a second delay loop, for frequency-dividing and delaying the input signal to generate a second output signal, wherein a frequency of the first output signal is higher than which of the second output signal; a phase detector, selectively detecting phases of the input signal, and one of the first delayed output signal and the second delayed output signal, to generate a phase detecting result; and a delay control circuit, for generating a first and a second delay control signal according to the phase detecting result, wherein the first and the second delay control signals are respectively transmitted to the first delay loop and the second delay loop, to control delay amounts of the first delay loop and the second delay loop.

Abstract: A modulation device includes a signal input for receiving a data stream to be modulated and a first and a second signal output. At least one first complex component is derived from the data stream in a coding device. A first and a second high-frequency signal are output via the signal outputs. The first and second high-frequency signals are derived from the at least one first complex component and are distinguished by the fact that the second high-frequency signal has a phase shift of substantially 90° with respect to the first high-frequency signal.

Abstract: A delay locked loop semiconductor apparatus that models a delay of an internal clock path is presented. The semiconductor apparatus includes: a DLL and a detection code output block. The DLL includes a delay model unit in which a delay value of an internal clock path is modeled and is configured to output a DLL clock signal of which the phase is controlled by reflecting the delay value of the internal clock path into an applied input clock signal. The detection code output block is configured to output a phase difference detection code having a code value corresponding to a phase difference between a first phase correction clock signal generated by reflecting a model delay value of the delay model unit into the DLL clock signal and a second phase correction clock signal generated by reflecting an actual delay value of the internal clock path into the DLL clock signal.

Abstract: A phase-locked loop (PLL) frequency synthesizer includes a phase detector, a low pass filter coupled to the phase detector, an amplifier coupled to the low pass filter, a voltage controlled oscillator (VCO) coupled to the amplifier, a power splitter coupled to the VCO, and a switch configured to select between a first branch and a second branch through which to couple the power splitter to the phase detector. The first branch includes a frequency divider while the second branch includes a mixer. The PLL frequency synthesizer also includes a frequency accuracy indicator that compares a frequency in the first branch with a frequency generated in the second branch, and confirms that the PLL frequency synthesizer is locked to a desired frequency upon receiving a phase lock signal, if the frequency generated in the first branch is the same as the frequency generated in the second branch.

Abstract: A phase-locked loop circuit comprising: an oscillator (20) configured to generate an output signal; an input (25) for receiving a reference clock signal; a delay cell (26) configured to delay the reference clock signal to generate a delayed reference clock signal; a phase comparator (27) configured to generate a quantized signal indicative of the phase difference between the output signal and the delayed reference clock signal, an integrator (28) configured to integrate the quantized signal to form an integrated signal; a first feedback path (22) configured to control the phase and/or frequency of the oscillator in dependence on the integrated signal; and a second feedback path (23) configured to adjust the delay applied by the delay cell (26) in dependence on the integrated signal.

Abstract: A low bandwidth phase lock loop (PLL) arranged in a dual-loop configuration is disclosed. The first loop is a standard loop configuration using a crystal oscillator as a reference clock. The loop parameters for this first PLL can be optimized to work over a wide range of output frequencies, and with a minimum amount of jitter. The first loop outputs a reference signal, which is a VCO output. The second loop comprises a bang-bang detector configured to drive a digital loop filter, which then drives a phase interpolator. The phase interpolator manipulates the output phase. Since phase and frequency are related, where frequency is the derivative of phase, small frequency offsets can be made using a phase control signal, generated within the second loop based on the relation between the reference signal and the clock input signal. The second loop sets the jitter transfer bandwidth of the system.

Abstract: A phase locked loop (PLL) includes a voltage controlled oscillator (VCO) configured to supply an output signal. A phase frequency detector (PFD) is configured to receive a reference frequency signal and to provide a first control signal. A first charge pump is configured to receive the first control signal and to provide a first voltage signal in order to control the VCO. A second charge pump is configured to receive the first control signal and to provide a second voltage signal. A comparator is configured to receive a reference voltage signal, to compare the reference voltage signal and the second voltage signal, and to provide a second control signal. The PFD is configured to adjust at least one side slope of the first control signal based on the second control signal.

Abstract: A phase-locked-loop (PLL) circuit is provided. The PLL circuit includes a phase/frequency detector, a digital filter, a digital low pass filter (LPF), a digitally controlled oscillator (DCO), and a frequency divider. The digital LPF performs a low-pass-filtering on least significant bits of first digital data in a digital mode and generates filtered second digital data. The DCO performs a digital-to-analog conversion on the second digital data and most significant bits of the first digital data to generate a first signal, generates an oscillation control signal based on the first signal, and generates an output clock signal oscillating in response to the oscillation control signal.

Abstract: Provided are a phase locked loop (PLL) circuit, a lock detector employable with a PLL circuit, a system including such a PLL circuit and/or lock detector, and a method of detecting a lock/unlock state of a PLL circuit. The PLL circuit may include a clock generating circuit configured to generate an output clock signal having a predetermined frequency in synchronization with a reference clock signal. The lock detector may be configured to determine that the PLL circuit is in a lock state when a phase difference between the reference clock signal and the output clock signal is equal to or less than a first reference value, determine that the PLL circuit is in an unlock state when the phase difference between the reference clock signal and the output clock signal is greater than a second reference value, and generate a lock detection signal.

Abstract: A phase locked loop circuit according to the present invention includes a selector that selects an input clock, a 1/m frequency divider that divides a frequency of the input clock, a 1/n frequency divider that divides a frequency of a feedback clock, a phase difference detector, a first voltage controlled oscillator that includes a first voltage holding circuit, a second voltage controlled oscillator that includes a second voltage holding circuit, and a selection circuit that outputs any output of the first and second voltage controlled oscillators as an output clock and outputs any output of the first and second voltage controlled oscillators as a feedback clock. The input clock is switched when the voltage controlled oscillator in a holding mode generates the output clock and the voltage controlled oscillator in a normal mode generates the feedback clock.

Abstract: An on-chip phase-locked loop circuit has reduced power consumption in a semiconductor integrated circuit. The phase locked loop circuit is equipped with a phase frequency comparator, a loop attenuator, a charge pump, a loop filter, a voltage controlled oscillator and a divider. The attenuator includes a sampling circuit and a counter. A sampling pulse and first and second output signals both outputted from the phase frequency comparator are supplied to the sampling circuit. The sampling circuit outputs a sampling output signal. When the counter completes a countup of a predetermined number of sampling pulses outputted from the sampling circuit, the counter outputs a countup completion output signal. The charge pump outputs a charging current or a discharging current to the loop filter in response to the countup completion output signal.

Abstract: Various embodiments of the present invention relate to systems, devices and method of frequency synthesis that generate in-phase and quadrature-phase clock signals at a programmable frequency. The generated frequency, which can range from a fraction to multiples of the input reference frequency, is generated by dividers following a phase-locked loop, thus avoiding the use of a low input reference frequency as well as frequency doubling.

Abstract: A differential charge pump circuit including a common mode bias unit, a first single-ended charge pump unit, and a second single-ended charge pump unit is provided. The common mode bias unit provides a differential signal to a low pass filter. The first single-ended charge pump unit provides a first current to the common mode bias unit or sinks the first current from the common mode bias unit via the first terminal based on an up signal and a down signal. The second single-ended charge pump unit provides a second current to the common mode bias unit or sinks the second current from the common mode bias unit via the second terminal based on the up signal and the down signal. The first and the second single-ended charge pump units respectively charge or discharge the first and the second terminals of the common mode bias unit.

Abstract: A delay locked loop includes a delay unit delaying an input clock to generate an output clock, a replica delay unit delaying the output clock to generate a feedback clock, a phase comparing unit outputting a phase signal having a first or second value according to whether the phase of the feedback clock leads the phase of the input clock, a filtering unit generates a filtering signal in response to the phase signal and updates the filtering signal when a difference of count numbers of the phase signal having the first value and the second value is substantially equal to a filtering depth, a locking unit generates a locking signal in response to the filtering signal, and a control unit adjusts a delay value in response to the filtering signal and maintains the delay value when the locking signal is activated.

Abstract: A method may include performing a logical exclusive OR and a logical inverse exclusive or on an input reference signal and an output signal to generate an XOR signal and an XNOR signal, respectively. The method may also include generating a switch control signal indicative of whether a first phase of the input reference signal leads or lags a second phase of the output signal. The method may additionally include: (i) transmitting the XOR signal to an output of a switch if the first phase leads the second phase; and (ii) transmitting the XNOR signal to the output of the switch if the first phase lags the second phase. The method may further include generating a phase detector output signal indicative of a phase difference between the second phase based on a signal present on the output of the switch.

Abstract: The present disclosure provides a phase comparator including, a first latch, a second latch, a first detection circuit, a second detection circuit, and a charge-pump circuit having the function of a changeover switch.

Abstract: A method and apparatus for generating a clock that can be switched in phase within a reduced interval of dead time are disclosed.

Abstract: A start-up circuit for a PLL includes a phase-frequency detector (PFD), one or more logic gates, a flip-flop and a false detection circuit. The false detection circuit includes a set of series connected flip-flops. The PFD receives a reference signal and a feedback signal. The PFD compares the frequency of a reference signal with that of a feedback signal. If the frequency of the reference signal is greater than the frequency of the feedback signal then a start-up signal is generated and transmitted to the PLL. The PLL increases the frequency of the feedback signal until it is greater than the frequency of the reference signal. The generation of the start-up signal is halted when the frequency of the feedback signal is greater than the frequency of the reference signal.

Abstract: In described embodiments, a clock alignment system with a digital bang-bang phase detector (BBPD) employs digitally implemented hysteresis. A first BBPD is employed for a phase control loop that compares the phases from two different clock domain sources, where one clock domain source is used as a reference clock for the phase control loop. A second BBPD with delayed reference clock is employed to resolve ambiguous phase relations seen by the first BBPD. An initial state of a BBPD vector, defined as a vector of current values of the first BBPD and the second BBPD, is examined. Based on the initial and subsequent states of the BBPD vector, the non-reference clock is permitted to naturally move to a lock state through action of the phase control loop, or forced to have its phase rotate clockwise or counterclockwise to reach the lock state.

Abstract: A system and method is provided for phase interpolator based transmission clock control. The system includes a transmitter having a phase interpolator coupled to a master timing generator and a transmission module. The phase interpolator is also coupled to a receiver interpolator control module and/or an external interpolator control module. When the system is operating in repeat mode, the transmitter phase interpolator receives a control signal from a receiver interpolator control module. The transmitter phase interpolator uses the signal to synchronize the transmission clock to the sampling clock. When the system is operating in test mode, a user defines a transmission data profile in an external interpolator control module. The external interpolator control module generates a control signal based on the profile. The transmitter phase interpolator uses the signal to generate a transmission clock that is used by the transmission module to generate a data stream having the desired profile.

Abstract: Frequency synthesizer with immunity from oscillator pulling. The frequency synthesizer for generating an output frequency includes an oscillator that is capable of generating a first frequency. The frequency synthesizer also includes an output divider coupled to the oscillator. The output divider is configurable to allow the oscillator to generate a second frequency to prevent degradation in phase noise due to an interference to the first frequency of the oscillator, and to generate the output frequency from the second frequency.

Abstract: There is provided a jitter suppression circuit and a jitter suppression method in which both shortening of a pull-in time and high jitter suppression characteristics is satisfied. In a jitter suppression circuit using a digital phase locked loop, both shortening of a pull-in time and high jitter suppression effect can be satisfied by determining whether the loop is in a synchronous state or not using a phase difference between an input clock and an output clock, and changing characteristics of a loop filter by the determination result.

Abstract: A method for performing a clock and data recovery includes providing data and a clock; determining early/late values of the data to generate a first-order phase code using the data and the clock; and accumulating first-order phase codes retrieved from different finite state machine (FSM) cycles to generate a second-order phase code. A plurality of candidate total phase codes is generated from the second-order phase code. A multiplexing is performed to the plurality of candidate total phase codes to output one of the plurality of candidate total phase codes as a total phase code. The multiplexing is controlled by the first-order phase code. A brake machine may be implemented to prevent over-compensation of phases.

Abstract: The disclosed invention provides a structure and method for improving performance of a phase locked loop by suppressing low-frequency noise produced by a phase detector. This is achieved by up-conversion of the in-band frequency components in the phase difference between reference signal and feedback signal to a higher frequency range where noise performance of a phase detector is improved. The up-converted phase difference is provided to a phase detector that is configured to determine an error signal based upon this phase difference. The error signal is output to a down-converter configured to down-convert the error signal (e.g., back to the original frequency range), thereby intrinsically up-converting the error signal's low-frequency noise (produced by the phase detector), prior to being provided to a filter configured to filter the up-converted noise, thereby resulting in an improved PLL noise performance.

Abstract: A digital phase-locked loop having a phase frequency detector (PFD), a 3-state phase frequency detection converter (3-state PFD converter), a loop filter and a digital voltage-controlled oscillator is provided. The PFD receives an input frequency and a reference frequency and outputs a first signal and a second signal based on the phase difference between the input frequency and the reference frequency. The 3-state PFD converter outputs a 3-state signal according to the first and second signals, wherein the 3-state signal is presented in 1, 0 and ?1. The loop filter outputs at least one control bit based on only the 3-state signal. The DCO adjusts the outputted oscillation frequency according to the control bit.

Abstract: A receiver that receives a train of a plurality of symbols representing digital data, includes: an isolated pulse detector that detects whether the digital data includes an isolated pulse in the symbol train, respectively; a phase detector that detects a timing at which the level of the symbols changes; a symbol value converter that converts the symbols into logical values on the basis of the timing detected by the phase detector; and a data selector that selects a logical value of the isolated pulse instead of the logical value converted by the symbol value converter when the isolated pulse detector detects the digital data containing the isolated pulse.

Abstract: A phase-locked loop comprising; an oscillator configured to output an oscillating signal in dependence on the control signal at an input of the oscillator; a phase detector and loop filter configured to output a low frequency compensation signal in dependence on the output of the oscillator and a reference signal; a correlator configured to frequency correlate an interferer signal and the low frequency compensation signal, and in dependence on that correlation generate a correlation signal; and an adaptive filter configured to adapt the interferer signal in dependence on the correlation signal to output a high frequency compensation signal; and a summation unit configured to combine the low frequency compensation signal and the high frequency compensation signal to form a control signal to drive the input of the oscillator.

Abstract: A signal recovery circuit capable of expanding the receive margin is provided. The signal recovery circuit comprises for example a clock generator unit CLK_GEN for generating the clock signals CLKa, CLKb, and CLKc, a window width control unit WW_CTL, and a clock data discriminator unit CD_JGE for generating a phase detector signal (EARLY, LATE) when for example a data signal Di pulse edge enters between the CLKa and CLKb, or between the CLKb and CLKc, and the clock generator unit. Along with exerting control based on these phase detection signals to maintain the mutual phase differential of the overall phase of CLKa, CLKb, CLKc so as to prevent intrusion of the above described Di edge, the CLK_GEN also regulates the phase differential between CLKa and CLKb, and the phase differential between CLKb and CLKc based on a signal (Sww) from the WW_CTL.

Abstract: A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal 30 according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock 15.

Abstract: A clock generation circuit includes a first divider, a loop unit that has a second divider and generates an output clock which is in phase synchronization with a reference clock of the first divider and has a frequency that is F times the reference clock, a clock switching unit that selects one input clock among a plurality of input clocks and supplies the selected input clock to the first divider, and a timing control unit. The timing control unit switches the clock selection command in accordance with switching of clock selection information, switches at least one of a setting of the number R of the input clocks and a setting of the number F of the output clocks, and starts both of a count operation by using the first divider and a count operation by using the second divider after switching of the setting.

Abstract: A 4× over-sampling data recovery system consists of a charge pump PLL, a 4× over-sampler, a data regenerator and a digital PLL. The charge pump PLL receives a clock signal and generates a plurality of multiplicative clock signals in response to the clock signal. The 4× over-sampler samples a serial data to generate a M-bit signal according to the plurality of multiplicative clock signals, wherein each bit in the serial data is sampled for four times. The data regenerator sequentially receives and combines two M-bit signals to generate a (M+N)-bit signal. The digital PLL divides the (M+N)-bit signal into (N+1) groups of M-bit data and selects a designated M-bit data from the (N+1) groups of M-bit data to generate a P-bit recovery data.

Abstract: System and method for improving a digital PLL's performance by making fine grained adjustments to the loop gain. A preferred embodiment comprises a plurality of loop gain adjustors (such as loop gain adjustors 605, 606, 607, and 608) that can incrementally adjust the loop gain. The incrementally adjusted loop gains are sequentially brought on-line so that the loop gain of the digital PLL is slowly decreased. By slowly decreasing the loop gain, the digital PLL is less perturbed by smaller noise transients that would take time to settle. Hence, the digital PLL can quickly acquire a signal and then decrease its loop gain and hence its bandwidth when it only needs to track a signal. The reduced bandwidth also reduces the overall noise in the digital PLL that is due to the reference noise contribution.

Abstract: Phase-locked loop circuitry to generate an output signal, the phase-locked loop circuitry comprising oscillator circuitry, switched resistor loop filter, coupled to the input of the oscillator circuitry (which, in one embodiment, includes a voltage-controlled oscillator), including a switched resistor network including at least one resistor and at least one capacitor, wherein an effective resistance of the switched resistor network is responsive to and increases as a function of one or more pulsing properties of a control signal (wherein pulse width and frequency (or period) are pulsing properties of the control signal), phase detector circuitry, having an output which is coupled to the switched resistor loop filter, to generate the control signal (which may be periodic or non-periodic). The phase-locked loop circuitry may also include frequency detection circuitry to provide a lock condition of the phase-locked loop circuitry.

Abstract: An apparatus having a plurality of power supply domains and a plurality of logic components. Each of the plurality of logic components residing within a different one of the plurality of power supply domains. Each of the plurality of logic components is configured to operate with a corresponding clock signal within a respective one of the plurality of power supply domains.

Abstract: A clock data recovery circuit that supplies stable reference clocks to the object respectively by shortening the time of bit synchronization with each received burst data signal regardless of jittering components included in the received burst data signal, includes an interpolator that generates a reference clock having the same frequency as that of a received burst data signal and two types of determination clocks having a phase that is different from that of the reference clock respectively; and a phase adjustment control circuit that can change the phase of the reference clock in units of M/2?. After beginning receiving of a burst data signal, the clock data recovery circuit sets a large phase change value at the first phase adjustment timing and reduces the change value in the second and subsequent phase adjustment timings, thereby realizing quick bit synchronization with the received burst data signal to generate a reference clock.

Abstract: A phase locked loop (PLL) which has a desired frequency characteristic even though a manufacturing process of a semiconductor integrated circuit has fluctuations. The semiconductor integrated circuit includes the PLL and a control unit. The PLL has a phase frequency detector, a loop filter, a voltage controlled oscillator (VCO) and a divider. The VCO comprises a voltage-current converter (VIC) and a ring oscillator. In response to a control voltage, the VIC generates a control current for setting each operating current of the ring oscillator. The control unit switches the PLL to a calibration operating period of its open loop and a normal operating period of its closed loop.

Abstract: A system and method for low-cost performance and compliance testing of local oscillators and transmitters for wireless RF applications. A preferred embodiment comprises observing a digital signal from within an RF circuit, manipulating the signal with digital signal processing techniques, and determining if the RF circuit passes a test based upon results from the manipulating. Since the signal is clocked at a much lower frequency than an RF output of the RF circuit and the manipulation is performed digitally, testing can be performed at different stages of the production cycle and expensive test equipment can be eliminated.

Abstract: The present invention relates to a double data rate interface and method for use between a processor and random access memory, comprising a delay line including means for creating a delay in a data strobe signal from the random access memory, the delay line being arranged such that the delay in the data strobe signal is equal to the sum of set-up time and data bus rise time. The interface of includes the delay line comprising the delay locked loop which in turn comprises a ring oscillator. The ring oscillator includes a buffer and a Vernier delay.

Abstract: An apparatus configured for built in self test (BIST) jitter measurement is described. The apparatus includes a time-to-voltage converter. The time-to-voltage converter generates a voltage signal proportional to timing jitter present in a clock/data signal input. The apparatus also includes feedback circuitry for the time-to-voltage converter. The feedback circuitry provides a ramp slope for the time-to-voltage converter. The apparatus further includes a calibration controller. The calibration controller provides control signals to the time-to-voltage converter for process-independent calibration. The apparatus also includes a sample-and-hold (S/H) circuit. The S/H circuit provides a set bias voltage to the time-to-voltage converter once calibration is complete.

Abstract: A clock and data recovery device receives a serial data stream and produces recovered clock and data signals. The clock and data recovery device operates over a range of frequencies and without use an external reference clock. A first loop supplies a first clock signal to a second loop. The second loop modifies the first clock signal to produce the recovered clock signal and uses the recover clock signal to produce the recovered data signal. The first loop changes the frequency of the first clock signal based on frequency comparison and data transition density metrics.

Abstract: An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.

Abstract: A phase locked loop (PLL) circuit including a phase comparator for comparing a phase of a reference signal with a phase of a feedback signal, an oscillator for outputting an output signal at a frequency in accordance with an output of the phase comparator, a feedback loop for returning the output signal of the oscillator and supplying the output signal as the feedback signal, and a delay circuit for delaying the phase of the output signal output from the oscillator to a load circuit, wherein the delay circuit is provided outside the feedback loop.

Abstract: A frequency synthesis circuit is disclosed. The circuit includes a phase-locked loop and multi-phase oscillator such as a rotary traveling wave oscillator (RTWO). The oscillator provides a plurality of phases that are applied to a selection circuit. The selection circuit, in response to the output of a delta-sigma modulator, selects one of the phases of the multi-phase oscillator to minimize phase shift noise when the divider ratio in the loop changes, thereby eliminating a source of noise that contaminates the synthesized frequency. This permits the use of the frequency synthesis in applications requiring a high degree of spectral purity.

Abstract: A digital circuit with adaptive resistance to single event upset. A novel transient filter is placed within the feedback loop of each latch in the digital circuit to reject pulses having a width less than T, where T is the longest anticipated duration of transients. The transient filter includes a first logic element having a controllable inertial delay and a second logic element coupled to an output of the first logic element. A first controller provides a control voltage VcR to each first logic element to control a rise time of the first logic element to be equal to T. A second controller provides a control voltage VcF to each first logic element to control a fall time of the first logic element to be equal to T.

Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.

Abstract: A phase-locked loop (PLL) circuit including a voltage-controlled oscillator (VCO) with a variable gain is provided. A phase frequency detector (PFD) detects a phase difference between a reference signal and a PLL feedback signal. A charge pump and a loop filter sequentially process an output signal of the PFD. A VCO has different gains according to a mode transition. A control voltage applied to the VCO is selected from an output signal of the loop filter and an additional control signal according to the mode transition.

Abstract: A semiconductor integrated circuit includes: digitally controlled oscillators; a phase-data output unit; an integration processing unit; a filter unit; a multiplier (a first multiplier) that outputs, as an oscillator tuning word, a value obtained by multiplying an output signal subjected to time division from the filter unit with a predetermined coefficient; and an output selector (a tuning-word separating unit) that allocates the oscillator tuning word to the digitally controlled oscillators in synchronization with a reference frequency.

Abstract: An apparatus for clock/voltage scaling includes a device power manager arranged to supply a scalable frequency clock to an interface; a delay-locked loop, supplied by a constant fixed frequency clock and a constant voltage, arranged to generate a unique code depending on process, voltage, and/or temperature; and controlled delay line elements coupled to the delay-locked loop, arranged to generate an appropriate delayed data strobe based on the unique code. A method for a digital phase lock loop high speed bypass mode includes providing a first digital phase lock loop in a first high speed clock domain; providing a second digital phase lock loop in a second clock domain; controlling an output of a first glitchless multiplexer according to preselected settings using a device power manager synchronized locally; and controlling an output of a second glitchless multiplexer using a control logic element of the second digital phase lock loop.