Abstract: A Phase-Locked Loop (PLL) includes a Phase-to-Digital Converter (PDC), a programmable digital loop filter, a Digitally-Controlled Oscillator (DCO), and a loop divider. Within the PDC, phase information is converted into a stream of digital values by a charge pump and an Analog-to-Digital Converter (ADC). The stream of digital values is supplied to the digital loop filter which in turn supplies digital tuning words to the DCO. A number of types of ADCs can be used for the ADC including a continuous-time delta-sigma oversampling Digital ADC and a Successive Approximation ADC. The voltage signal on the charge pump output is a small amplitude midrange voltage signal. The small voltage amplitude of the signal leads to numerous advantages including improved charge pump linearity, reduced charge pump noise, and lower supply voltage operation of the overall PLL.

Abstract: The invention provides a clock and data recovery (CDR) circuit, including: a phase locked loop (PLL) circuit, providing a reference voltage; a first delay device, delaying an input data according to a control signal so as to generate a first delay signal; an edge detector, generating an edge signal according to the first delay signal and the input data; a second delay device, delaying the edge signal so as to generate a second delay signal; a first gated voltage-controlled oscillator, generating an output recovery clock according to the second delay signal and the reference voltage; a phase detector, detecting a phase difference between the first delay signal and the output recovery clock so as to generate a phase signal and a output recovery data; and an amplifier, amplifying the phase signal by a factor so as to generate the control signal.

Abstract: A phase-locked loop with two negative feedback loops including: a phase frequency detector which includes phase difference between the input clock and the feedback clock in a frequency-phase-locked loop and outputting up or down signals based on the phase difference; a charge pump outputting the current proportional to the up and down signals outputted from the phase frequency detector; a loop filter outputting the voltage by filtering the current outputted from the charge pump; a voltage controlled oscillator outputting the frequency based on the voltage outputted from the loop filter; a divider dividing the frequency outputted from the voltage controlled oscillator and feedbacking to the phase frequency detector; a frequency-voltage converter generating the voltage corresponding to the frequency outputted from the voltage controlled oscillator, and suppressing noise of the voltage controlled oscillator by feedbacking the generated voltage to the voltage controlled oscillator.

Abstract: This invention provides a clock and data recovery system, which comprises a plurality of gm cells, control device, resistor and capacitor. The gm cells respectively have an input end and an output end. The control devices are connected to these output ends. According to a time value, the control device controls a part of the plurality of gm cells to form a first gm cell, and the control device controls another part of the plurality of gm cells to form a second gm cell. The resistor is connected between the first gm cell and the second gm cell. The capacitor is connected to the second gm cell. Wherein, the control device controls the ratio of the first gm cell and the second gm cell in accordance with a time-division multiplexed manner.

Abstract: A delay locked loop in accordance with some embodiments of the inventive concept may include a delay signal generation part generating a first delay signal having a first phase and a second delay signal having a second phase by delaying a reference signal on the basis of a delay control signal; a phase synthesizing part generating at least one third signal having a third phase using the first delay signal and the second delay signal; and a phase detection part generating a control code by comparing the reference signal with each of the first delay signal, the second delay signal and the third signal.

Abstract: A semiconductor integrated circuit includes: a delay locked loop (DLL) configured to generate a DLL clock signal by delaying a source clock signal by a first delay time for obtaining a lock, wherein an update period of the DLL is controlled in response to an update period control signal after locking is completed; and an update period controller configured to generate the update period control signal based on a second delay time occurring in a loop path of the DLL in response to the source clock signal and a plurality of control signals provided from the DLL.

Abstract: A delay-locked loop (DLL) circuit is disclosed that can generate an output oscillation signal having a frequency that is an integer multiple of an input oscillation signal. The DLL includes a phase detector, a charge pump, and a voltage-controlled oscillator (VCO). The phase detector generates UP and DN control signals in response to a phase difference between a reference signal and a feedback signal. The charge pump generates a control voltage in response to the UP and DN control signals. The VCO adjusts the frequency of the output oscillation signal in response to the control voltage, generates the reference signal in response to the input oscillation signal, and generates the feedback signal in response to the output oscillation signal.

Abstract: A phased-locked loop (PLL) circuit which comprises a phase-frequency detector (PFD) configured to receive a reference signal, a voltage-controlled oscillator (VCO) configured to produce a VCO signal, and a divider configured to divide the VCO signal thereby producing a feedback signal based on the feedback signal not being locked to the reference signal. Based on the feedback signal not being locked to the reference signal, the PFD is configured to compare an edge of the reference signal with an edge of the feedback signal to produce an error signal. Based on the feedback signal being locked to the reference signal, the PFD is configured to compare the edge of the reference signal to an edge of the VCO signal to produce an error signal and the divider is configured to be disabled.

Abstract: A PLL circuit includes a digital PLL circuit and an analog PLL circuit, wherein the digital PLL circuit includes a first digital phase detector configured to detect a first phase difference between a reference clock signal and a first feedback clock signal, and a phase accumulator configured to generate, as the first feedback clock signal, a digital oscillating signal having oscillating frequency that changes in response to the detected first phase difference, and wherein the analog PLL circuit includes a second digital phase detector configured to detect a second phase difference between the digital oscillating signal generated by the phase accumulator and a second feedback clock signal, and a voltage controlled oscillator configured to receive a voltage value changing in response to the detected second phase difference and to generate the second feedback clock signal that oscillates at frequency responsive to the voltage value.

Abstract: A phase locked loop (PLL) circuit is provided with selectable feedback paths. In one example, a method of operating a device includes passing a clock signal provided by a PLL circuit of the device through an internal feedback path of the PLL circuit to provide a first input signal to the PLL circuit while at least one external circuit of an external feedback path of the device is disabled during a low power operation mode of the device. The method also includes detecting a lock between the first input signal and a reference signal during the low power operation mode. The lock indicates that the clock signal is operating at a frequency used during a normal operation mode of the device. The method also includes passing the clock signal through the external feedback path to provide a second input signal to the PLL circuit.

Abstract: A delay lock loop includes a phase frequency detector, a loop filter, and a voltage controlled delay circuit. The phase frequency detector is used for outputting an upper switch signal or a lower switch signal according to a reference clock and a feedback clock. The loop filter includes a first capacitor, a second capacitor, and a first switch. The first capacitor is charged or discharged and the first switch is turned off during a phase tracking period. The first capacitor and the second capacitor are charged or discharged and the first switch is turned on during a phase locking period. The voltage controlled delay circuit is used for outputting the feedback clock according to the reference clock and a control voltage outputted by the loop filter.

Abstract: Spread spectrum generators and methods are disclosed. In one implementation, a spread spectrum clock generator includes a phase locked loop generating an output clock according to a first clock and a second clock; a delay line coupled between the first clock and the phase locked loop; a modulation unit providing a modulation signal to control the delay line thereby modulating phase of the first clock, such that frequency of the output clock generated by the phase locked loop varies periodically; a scaling unit scaling the modulation signal from the modulation unit according to a scaling ratio, and outputting to the delay line; and a calibration unit generating an output signal for controlling the scaling ratio.

Abstract: A method of performing modulation of a data signal at a phase-locked loop (PLL) includes generating, at an upper frequency port of the PLL, a digital loop signal based at least in part on the data signal. The method further includes differentiating the digital loop signal to generate a digital input signal and converting the digital input signal to an analog current signal. A first feedback signal is generated based on the analog current signal. The method further includes generating, at a lower frequency port of the PLL, a second feedback signal based on the first feedback signal and further based on the data signal. According to further embodiments, apparatuses and a computer-readable medium are disclosed.

Abstract: Disclosed herein is a signal transmission system including: a first signal processing section configured to perform signal processing on a basis of a reference signal; a high-frequency reference signal generating section configured to generate and transmit a high-frequency reference signal having a higher frequency than the reference signal such that the high-frequency reference signal is synchronized with the reference signal; a low-frequency reference signal generating section configured to receive the high-frequency reference signal from the high-frequency reference signal generating section, and generate a low-frequency reference signal having a lower frequency than the high-frequency reference signal such that the low-frequency reference signal is synchronized with the received high-frequency reference signal; and a second signal processing section configured to perform signal processing on a basis of the low-frequency reference signal generated by the low-frequency reference signal generating section.

Abstract: A communication terminal includes first and second transmitters, which are coupled to produce respective first and second Radio Frequency (RF) signals that are phase-shifted with respect to one another by a beamforming phase offset, and to transmit the RF signals toward a remote communication terminal. The terminal includes a reception subsystem including first and second receivers and a phase correction unit. The first and second receivers are respectively coupled to receive third and fourth RF signals from the remote communication terminal. The phase correction unit is coupled to produce, responsively to the third and fourth RF signals, a phase correction for correcting an error component in the beamforming phase offset.

Abstract: Disclosed herein is a device that includes a coarse adjusting circuit generating first and second clock signals having different phases from each other, and a fine adjusting circuit generating a third clock signal having a phase between a phase of the first clock signal and a phase of the second clock signal. The fine adjusting circuit includes a plurality of first transistors receiving the first clock signal and a plurality of second transistors receiving the second clock signal. The fine adjusting circuit controls the phase of the third clock signal by synthesizing the first clock signal output from selected zero or more of the first transistors based on adjustment codes and the second clock signal output from selected zero or more of the second transistors based on the adjustment codes. The adjustment codes are not a binary system.

Abstract: A lock signal indicating that a target signal is in phase with a reference signal includes detecting the reference signal at the rising and falling edges of the target signal. The target signal is detected on the rising and falling edges of the reference signal. An out of phase condition between the target and reference signals is used to place a timing means in a reset state. When the timing means is allowed to time out, a signal is asserted which indicates that the target signal is deemed to be locked to the reference signal.

Abstract: An adjusting circuit of duty cycle includes an edge detecting circuit, a flip-flop connected to the edge detecting circuit, a feedback control circuit connected to the flip-flop and a charge pump circuit connected to the feedback control circuit. The edge detecting circuit detects an edge of an inputted clock signal. The flip-flop sets an outputting terminal thereof at a first level according to a clock signal outputted by the edge detecting circuit. The charge pump circuit controls a duration of the first level outputted the outputting terminal of the flip-flop by charging and discharging a capacitor. The flip-flop sets the outputting terminal thereof at a second level contrary to the first level according to a clock signal outputted by the feedback control circuit. An adjusting method of duty cycle is also disclosed. The adjusting circuit of duty cycle has a simple structure, a stable performance and a fast speed.

Abstract: A data equalizing circuit includes an equalizer configured to control a gain of data according to a value of a control code and output a controller gain; and a detection unit configured to divide n cycles of the data into N periods, count data transition frequencies for n/N periods while changing the value of the control code, calculate dispersion values of data transition frequencies for 1/N periods of the data from the data transition frequencies for the n/N periods, and finally output the value of the control code corresponding to a largest dispersion value, wherein n is equal to or greater than 2 and is set such that boundaries of the respective n/N periods of the data have different positions in the 1 UI data.

Abstract: Methods and apparatus are provided for pseudo asynchronous testing of receive paths in serializer/deserializer (SerDes) devices. A SerDes device is tested by applying a source of serial data to a receive path of the SerDes device during a test mode. The receive path substantially aligns to incoming data using a bit clock. A phase is adjusted during the test mode of the bit clock relative to the source of serial data to evaluate the SerDes device. The source of serial data may be, for example, a reference clock used by a phase locked loop to generate the bit clock. The phase of the bit clock can be directly controlled during the test mode, for example, by a test phase control signal, such as a plurality of interpolation codes that are applied to an interpolator that alters a phase of the bit clock.

Abstract: An apparatus includes a first oscillator configured to generate a reference signal and a second oscillator configured to generate an output signal having a controllable frequency. The apparatus also includes a frequency difference detector configured to generate a difference signal having a frequency based on a frequency difference between the reference signal and the output signal. The apparatus further includes a discriminator configured to modify the frequency of the output signal based on the difference signal. The frequency difference detector can be configured to generate the difference signal having multiple pulses. The discriminator can be configured to count a number of pulses in the difference signal during a specified time period and to modify the frequency of the output signal based on the counted number of pulses. The specified time period can be adjustable.

Abstract: A loop filter of a phase-locked loop (PLL) that uses a current-controlled oscillator (CCO) includes a capacitor, a voltage-to-current (V-to-I) converter, and a charge pump. The input node of the loop filter receives a first current from an external charge pump. The combination of the capacitor and the V-to-I converter generates a first component of the output current of the loop filter based on the first current. The charge pump of the loop filter generates a second component of the output current. The loop filter is implemented without the need for a zero-frequency-determining resistor, the resistor instead being realized by the product of the first current, the second component of the output current and the transconductance of the V-to-I converter. Phase noise reduction in the PLL, as well as implementation of the loop filter with a smaller area, are thus made possible.

Abstract: An ILFD controller sets a control parameter on the basis of a frequency of a frequency-divided signal and a frequency of a reference signal measured by a clock counter. A VCO controller selects an oscillation band that defines an oscillation frequency of a VCO and also selects an oscillation band of the VCO on the basis of the frequency of the reference signal and a frequency of a frequency-divided signal that is a result obtained by frequency-dividing an output signal, which is delivered from the VCO in response to the selected oscillation band, by means of an ILFD and a frequency divider.

Abstract: Designs of devices having digital phase locked loop (DPLL) circuits that include multiple digital feedback loops to generate high frequency clock signals by a digitally controlled oscillator (DCO). A time-to-digital converter (TDC) module is provided in such a DPLL circuit to receive an input reference clock signal and a first feedback clock signal from a first digital feedback loop and produces a digital TDC output indicative of a first phase error caused by a difference in time between the input reference clock signal and the first feedback clock signal. A second digital feedback loop is provided to generate a second digital feedback signal indicative of a second phase error caused by a difference in frequency between a desired clock signal and a generated clock signal generated by the DCO. The first and second digital feedback loops are coupled to the DCO to generate the high frequency clock signals.

Abstract: A frequency synthesis system with self-calibrated loop stability and bandwidth, which outputs an output signal based on an input signal and includes a detector, a charge pump, a filter, a controllable oscillator and a programmable frequency divider. The detector produces a detection signal based on a logic level difference between the input signal and a feedback signal. The charge pump is connected to the detector in order to produce a control signal based on the detection signal. The filter is connected to the charge pump in order to produce a tuning signal based on the control signal. The controllable oscillator is connected to the filter in order to produce the output signal based on the tuning signal. The programmable frequency divider is connected to the controllable oscillator in order to produce the feedback signal based on the output signal. The filter is a discrete time loop filter.

Abstract: Described embodiments provide a method of calibrating, by a calibration engine, a phase-locked loop (PLL) having one or more adjustable oscillators. The method includes entering a calibration mode of the PLL. The PLL is set to an initial state, thereby selecting one of the adjustable oscillators for calibration, an initial threshold window, and an initial tuning band of the selected adjustable oscillator. If the control signal of the selected adjustable oscillator is not within the initial threshold window, the calibration engine iteratively adjusts at least one of: (i) the selected tuning band of the selected adjustable oscillator, (ii) the selected adjustable oscillator, and (iii) the selected threshold window until the control signal of the selected adjustable oscillator is within the adjusted threshold window. If the control signal is within the threshold window, the one or more calibration settings of the PLL are stored and used to set the PLL operation.

Abstract: A circuit device includes a clock generator outputting a clock signal having a first frequency; plural phase controllers inputting the clock signal having the first frequency, and outputting clock signals having the first frequency and having phases advanced or delayed with respect to a phase of the clock signal; a selector inputting the plural clock signals having the first frequency output from the plural phase controllers, sequentially selecting pulses of the plural clock signals, and outputting a clock signal having a second frequency; a pattern generator generating a test pattern based on the clock signal having the second frequency; and a circuit inputting the clock signal having the second frequency and the test pattern generated by the pattern generator, operate based on the clock signal having the second frequency, and outputting operation results.

Abstract: Locked loops, delay lines, delay circuits, and methods for delaying signals are disclosed. An example delay circuit includes a delay line including a plurality of delay stages, each delay stage having an input and further having a single inverting delay device, and also includes a two-phase exit tree coupled to the delay line and configured to provide first and second output clock signals responsive to clock signals from inputs of the delay stages of the plurality of delay stages. Another example delay circuit includes a delay line configured to provide a plurality of delayed clock signals, each of the delayed clock signals having a delay relative to a previous delayed clock signal equal to a delay of a single inverting delay device. The example delay circuit also includes a two-phase exit tree configured to provide first and second output clock signals responsive to the delayed clock signals.

Abstract: A fractional spur compensation technique is implemented in a fractional-N PLL using multiple phase comparison frequencies Fpd, one of which is selected for any channel frequency Fch in a target frequency band to obtain a selected offset frequency Fos between the channel frequency Fch and its primary fractional spur throughout the target frequency band. Other features of an exemplary implementation of the fractional spur compensation technique include (a) maintaining the phase comparison frequency at less than a predetermined maximum value, (b) using a programmable reference frequency multiplier with selectable multiplication factors and/or a programmable reference frequency divider with selectable divide ratios to generate multiple phase comparison frequencies derived from a predetermined reference frequency Fref, and (c) using a programmable charge pump to select different charge pump currents for respective phase comparison frequencies to reduce loop gain variation.

Abstract: A frequency synthesizer circuit is disclosed. The frequency synthesizer circuit includes a comparator circuit coupled to a reference clock and a phase-corrected output signal. The frequency synthesizer circuit also includes a loop filter coupled to the comparator circuit. The frequency synthesizer circuit also includes an oscillator coupled to the loop filter. The frequency synthesizer circuit also includes a fractional divider coupled to an output of the oscillator. The frequency synthesizer circuit also includes phase correction circuitry that corrects a phase of an output of the fractional divider to produce the phase-corrected output signal.

Abstract: The disclosed is a reference frequency generating device (11), which includes a GPS receiver (21), a PLL circuit (31), a detector (28), a memory unit (29), and a controller (22). The PLL circuit (31) controls the digitally controlled oscillator (26) based on a synchronizing control signal acquired based on a reference signal from the GPS receiver (21). The memory unit (29) stores a correspondence relation between a control value of the synchronizing control signal, and a voltage value and a temperature at that time. When the reference signal is not acquired, the controller 22 determines a holdover control signal based on the correspondence relation, and the voltage and temperature detected by the detector 28, and controls the digitally controlled oscillator (26).

Abstract: A method and system for compensating for offsets when measuring parameters of a phase-locked loop (PLL). In one embodiment, a proportional path in the PLL is temporarily shut off, a measurement is made of a real time-to-zero crossing in the PLL to measure a defined parameter of the PLL, the proportional path is switched on, and the defined loop parameter is adjusted based on this measurement. In one embodiment, the real time-to-zero crossing is measured after introducing a phase step into the PLL between a reference signal and an output signal of the PLL. In an embodiment, two phase steps, having opposite polarities, are successively introduced into the PLL, and the time-to-crossing measurements resulting from these two phase steps may be averaged, and this average is used to determine a loop parameter.

Abstract: A digital delay line includes a plurality of delay cells therein. The delay line is configured to delay a periodic signal received at a first input thereof by passing the periodic signal through a selected number of the plurality of delay cells, in response to a discontinuous thermometer code that encodes the selected number. A code converter is provided, which includes a group bit decoder, a shared bit decoder and a code output cell array, which are collectively configured to generate the discontinuous thermometer code in response to a binary control code.

Abstract: A signal processing apparatus of the present invention includes an input unit configured to receive a reference signal supplied from an external device, a phase detection unit configured to detect a phase difference between the reference signal received from the input unit and a clock signal, a generation unit configured to generate the clock signal with a frequency corresponding to an output of the phase detection unit, and a control unit configured to detect an error between a frequency of the reference signal received from the input unit and the frequency of the clock signal based on an output of the phase detection unit and to output information, which indicates the status of a frequency change in the reference signal, to a display device based on the detected error.

Abstract: Systems and methods are provided for improving frequency resolution in a phase locked loop having an oscillator and a phase detector. A method comprises receiving a reference signal and generating an output signal having a phase relationship with the reference signal and receiving the output signal at a fractional divider connected between the oscillator and the phase detector in a feedback loop, wherein the fractional divider includes a plurality of configurable parameters. The method also comprises adjusting a value of the modulus parameter to increase frequency resolution.

Abstract: A temperature compensation circuit includes: a sensing circuit arranged to sense a temperature to generate a sensing signal; an operational circuit arranged to sample the sensing signal to generate a sample signal during a first phase, and arranged to generate an output signal according to the sensing signal and the sample signal during a second phase; and a capacitive circuit arranged to provide a capacitance adjusted by the output signal.

Abstract: A device for generating a clock signal, including a phase-locked loop including: a controlled oscillator to deliver a clock signal; plural phase comparators to compare a phase of the clock signal delivered by the controlled oscillator with plural clock signal phases applied at an input of the phase-locked loop; a mechanism for weighted summation of output signals of the plural phase comparators such that one or more of the weighting coefficients applied to one of the output signals has an absolute value that overrides the absolute values of the other weighting coefficients applied to the other output signals; and a mechanism filtering the weighted sum of the output signals of the plural phase comparators, to deliver at an output a control signal to the controlled oscillator.

Abstract: A phase-locked loop (PLL) including an active filter, a voltage-controlled oscillator (VCO), two phase detectors, a charge pump and a digital-to-analog converter (DAC) is provided. The VCO generates an oscillation signal according to a control signal provided at an output of the active filter. The first phase detector generates a phase difference signal according to a reference signal and a feedback signal associating with the oscillation signal. The charge pump provides a charging current to a first input of the active filter according to the phase difference. The second phase detector generates a digital reference signal according to the phase difference between the reference signal and the feedback signal. The DAC converts the digital reference signal to an analog reference voltage and provides the analog reference voltage to the second input of the active filter.

Abstract: A delay-locked loop circuit includes a voltage-controlled delay line configured to generate a plurality of delayed clock signals based on an input clock signal, a lock signal and a voltage control signal, the plurality of delayed clock signals being sequentially delayed from one another to produce an earliest delayed clock signal to a latest delayed clock signal, the voltage-controlled delay line including an anti-jitter delay circuit and a plurality of delay circuits, the anti-jitter delay circuit configured to output the earliest delayed clock signal, and the plurality of delay circuits coupled in series and configured to output a remainder of the plurality of delayed clock signals, a phase frequency detection circuit configured to generate an up signal and a down signal based on the earliest delayed clock signal and the latest delayed clock signal, a filter configured to generate the voltage control signal in response to the up signal and the down signal, and a lock detection circuit configured to generate

Abstract: A delay lock loop includes a phase frequency detector, a loop filter, and a voltage controlled delay circuit. The phase frequency detector is used for outputting an upper switch signal or a lower switch signal according to a reference clock and a feedback clock. The loop filter includes a first capacitor, a second capacitor, and a first switch. The first capacitor is charged or discharged and the first switch is turned off during a phase tracking period. The first capacitor and the second capacitor are charged or discharged and the first switch is turned on during a phase locking period. The voltage controlled delay circuit is used for outputting the feedback clock according to the reference clock and a control voltage outputted by the loop filter.

Abstract: One embodiment of the present invention provides a phase-locked loop (PLL) for synthesizing a fractional frequency. The PLL can include a 1/N frequency divider, a voltage-controlled oscillator (VCO), a programmable phase mixer, and a phase detector. The programmable phase mixer can be coupled between an output of the VCO and an input of the frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock signal of frequency f1 by varying a phase of the output clock signal. The frequency divider is configured to receive the first clock signal from the programmable phase mixer and generate a second clock signal of frequency f2=f1/N. The phase detector can receive a reference clock signal and the second clock signal as inputs, and the phase detector's output can be used to generate the control voltage for the VCO.

Abstract: A digital linear transmitter for digital to analog conversion of a radio frequency signal. The transmitter includes a delta sigma (??) digital to analog converter (DAC) and a weighted signal digital to analog converter in the transmit path of a wireless device to reduce reliance on relatively large analog components. The ?? DAC converts the lowest significant bits of the oversampled signal while the weighted signal digital to analog converter converts the highest significant bits of the oversampled signal. The transmitter core includes components for providing an oversampled modulated digital signal which is then subjected to first order filtering of the oversampled signal prior to generating a corresponding analog signal. The apparatus and method reduces analog components and increases digital components in transmitter core architecture of wireless RF devices.

Abstract: The present disclosure is directed to a fractional-N digital phase locked loop (DPLL) that replaces the conventionally used time-to-digital converter (TDC) based phase detector with a bang-bang phase detector (BBPD). Compared to the TDC based phase detector, the BBPD has an often superior resolution for the same or similar amount of power and/or area consumption. Therefore, replacing the TDC based phase detector with a BBPD can reduce, or even eliminate, the common problem of spurs being added to the output signal generated by the DPLL because of the limited resolution of the TDC based phase detector. This can allow the DPLL to be used for the most demanding applications, such as in generating local oscillator signals for down-converting and demodulating weak signals received by a communication device, such as a cellular phone.

Abstract: Signal value storage circuitry 2 includes transparent storage circuitry 4, transition detector circuitry 6 and error detecting circuitry 8. The transition detector circuitry serves to generate a detection pulse when a signal transition is detected at a signal node NS within the transparent storage circuitry. The error detecting circuitry generates an error indicating signal when this detection pulse overlaps in time with the non-transparent phase of a pulse clock signal controlling the signal valve storage circuitry for at least an overlap period TOV.

Abstract: There is provided an integrated circuit in which a reference-signal source generates a reference signal having a basic frequency, a phase locked loop includes a voltage-controlled oscillator, a first frequency divider to generate a first frequency-divided signal based on the signal by N, a phase detector, a charge pump and a loop filter, the second frequency generates a second frequency-divided signal based on the signal generated by the voltage-controlled oscillator by M, wherein a minimum absolute value of a difference between the basic frequency multiplied by “K” and a frequency of the second frequency-divided signal is equal to or less than a low cutoff frequency of a bandpass filter or equal to or higher than a high cutoff frequency of the bandpass filter, the bandpass filter being represented by a transfer function from an input of the voltage-controlled oscillator to an output of the phase locked loop.

Abstract: According to an aspect of the present invention, one of multiple clock signals of different relative phases is selected based on a desired delay magnitude, and the digital values received on an input signal are then synchronized to an edge (“first edge”) of the selected clock signal to provide the digital values with the desired delay magnitude. In an embodiment, the selected clock signal can be delayed by a fine value (less than the minimum phase difference of the multiple clock signals) to provide a wide span of desired delays. An aspect of the invention provides for a synchronization circuit with reduced latency and which is substantially invariant to process, voltage and temperature (PVT) changes.

Abstract: A PLL includes a PFD configured to: receive a reference clock and a feedback clock, output a first signal, which includes first phase information for a rising edge of the reference clock, and output a second signal, which includes second phase information for a rising edge of the feedback clock. The PLL includes a logic gate coupled to the PFD configured to logically combine the first and second signals to produce a pulse signal having a rising edge, which includes the first phase information, and having a falling edge, which includes the second phase information. The PLL includes a TDC coupled the logic gate configured to generate a digital timing signal, which includes timing information for a phase difference of the first and second phase information. The PLL includes a controlled oscillator coupled to the TDC configured to vary a frequency of the feedback clock from the digital timing signal.

Abstract: Embodiments of the present invention may provide a clock and timing generation scheme for a video signal processor (e.g., a scaler), which enables fast switching between different input video standards without disturbing the output clock or timing. The scheme also may minimize the number of video frames that are dropped or repeated at the output. This may be achieved by locking the video's output timing to the input timing and also by utilizing a frame buffer to remove instantaneous discontinuities caused when an input is changed.

Abstract: A digital PLL may be combined with an analog PLL so that the output of the digital PLL is at a frequency high enough to maintain stability in the analog PLL when an initial reference clock signal is too low to maintain stability in the analog PLL. The digital PLL may include a scaling circuit, such as a frequency divider in the feedback path of the PLL, to generate the higher frequency output signal from the lower frequency reference input signal. The digital PLL may also use an on-chip free run ring oscillator as the clock for the digital PLL engine.

Abstract: Disclosed is a phase-frequency comparator stabilizing a loop band width by a simple circuit, there is provided a phase-frequency comparator which is a phase-frequency comparator of inputting a reference clock and a feedback clock and outputting an up signal to a frequency synthesizer and a down signal to the frequency synthesizer, which is provided with a first phase-frequency comparing circuit, a second phase comparing circuit, and a delay circuit portion inputting the reference clock and the feedback clock and providing a predetermined relative delay to an input of the first phase-frequency comparing circuit and an input of the second phase comparing circuit, in which frequency comparison is carried out by the first phase-frequency comparing circuit, and phase comparison is carried out by the first phase-frequency comparing circuit and the second phase comparing circuit controlling a latch.