Abstract: A control circuit configured to control a switching power supply including a ramp generator configured to generate a triangular waveform. A comparator is configured to generate a series of pulse width modulated (PWM) pulses at a first frequency and to regulate the switching power supply. The ramp generator includes a capacitor, a charging current source configured to provide a charging current to charge the capacitor, and a discharging current source configured to provide a discharging current to discharge the capacitor. The ramp generator also includes a closed loop current balancing current source configured to balance the currents from the charging and discharging current sources to establish a substantially zero direct current (DC) bias across the capacitor. The controller also includes a multi-phase configuration to provide a stackable multi-channel architecture.

Abstract: The pulse width adjusting circuit includes a pulse delaying circuit for inputting an inputted pulse signal a and for outputting a plurality of different delayed pulse signals b1, b2, . . . , a transmission gate for inputting an inputted pulse signal a and controlling the passage of the inputted pulse signal a in response to the application of two delayed pulse signals from among the plurality of different delayed pulse signals b1, b2, . . . , and a pulse width setting circuit connected to the transmission gate for setting the pulse width of an outputted pulse signal c generated on the basis of the inputted pulse signal a passing through the transmission gate.

Abstract: The present invention discloses a PWM signal generation circuit and a PWM signal generation method. The PWM signal generation circuit includes: a reference signal generation circuit for generating a reference signal according to an input voltage; a variable ramp signal generation circuit for generating a variable ramp signal; and a comparator circuit for comparing the reference signal with the variable ramp signal to generate a PWM signal. A rising slope and/or a falling slope of the variable ramp signal is variable.

Abstract: A motherboard includes a central processing unit (CPU), a drive, and a voltage-state display system to display a voltage mode of the CPU. The voltage-state display system includes a power management chip, a first transistor, a second transistor, a first light emitting diode (LED), and a second LED. A first phase output terminal of the power management chip is connected to the first LED through the first transistor. A second phase output terminal of the power management chip is connected to the second LED through the second transistor. The LEDs indicate the voltage mode of the CPU.

Abstract: Tunable injection locked (IL) dividers having enhanced locking range, good phase noise performance, and low power consumption are disclosed. In an exemplary design, an apparatus (e.g., a wireless device) includes an oscillator and at least one IL divider. The oscillator provides an oscillator signal at a first frequency. The at least one IL divider receives the oscillator signal and provides an output signal at a second frequency, which is related to the first frequency by an overall divider ratio for the IL divider(s). Each IL divider may be calibrated based on a target frequency of that IL divider. Each IL divider may be calibrated (e.g., by tuning at least one adjustable capacitor) to obtain an oscillation frequency within a predetermined tolerance of the target frequency of that IL divider. The oscillator may be calibrated based on a target oscillation frequency of the oscillator.

Abstract: The present invention is a device for coating surfaces of metallic work pieces with an electrically conductive material by employing short duration high current packets of pulses in which the work piece forms the cathode and the consumable coating material forms the anode, which are connected to a generator for generating pulses by charging and discharging a bank of capacitors using a MOSFET.

Abstract: A duty cycle correction circuit comprises a duty cycle detector, a filter, a comparator, a SAR DAC, an equalization device, a pass gate circuit, and a duty cycle corrector. The duty cycle detector generates control signals in response to internal clock signals. The equalization device equalizes voltage levels of the control signals, and the pass gate circuit applies the control signals to the duty cycle corrector. The filter obtains average voltages of the control signals. The comparator compares output signals from the filter to generate a comparison result. The SAR DAC performs a SAR algorithm to generate analog output signals based on the comparison result. The duty cycle corrector receives external clock signals, the analog output signals, and output signals from the pass gate circuit to generate the internal clock signals with a corrected duty cycle.

Abstract: A pulse width modulation signal with a less distortion component that is not influenced by a common-mode noise or an offset voltage is generated. Pulse signal generation circuits 6, 7 generate pulse signals S1, S2 whose pulse widths are discharge times t1, t2 of integrators 3, 4, respectively, a PWM signal generation circuit 8 detects discharge end timings of the integrators 3, 4 based on the pulse signals S1, S2, and a pulse whose pulse width is a time between discharge end timing of one of the integrators 4 and discharge end timing of the other one of the integrators 3 is generated so as to be output as a PWM signal Spwm.

Abstract: A duty cycle error accumulation circuit includes first to nth delay units and a feedback unit. The first to nth delay units receive a clock signal, a first input signal and a second input signal, respectively, to generate a first output signal and a second output signal by delaying one signal selected from first and second input signals based on a logic level of the clock signal. The feedback unit supplies second input signal to a kth delay unit based on second output signal of a (k+1)th delay unit. The first output signal of the kth delay unit is supplied to the (k+1)th delay unit as first input signal, and the clock signal is supplied to the first delay unit as first input signal and to the nth delay unit as second input signal. The duty cycle error accumulation circuit effectively corrects a duty cycle of a clock signal.

Abstract: An apparatus and method for controlling a device using pulse signals. In the apparatus and method, a two-stage control is used to generate pulse signals, which can be a PWM signal, a pulse signal including a PWM signal with a sleeping time, or a PDM signal. The two-stage control includes a second stage control, which generates pulse signals according to parameter values generated periodically by a first stage according to a target value and feedback sensing values. The two-stage control can be used in decreasing perturbation in a closed-loop control and accurate open-loop control.

Abstract: An improved programmable duty cycle generator and method of operation. In one aspect, the generated output signal duty cycle is not measured, but rather is generated based on a predetermined value. Saw tooth generator/Integrator schemes are used to create the saw type waveforms of the incoming frequency which in conjunction with DAC is used to create the desired duty cycle. The improved programmable duty cycle signal generator for placement in key pinch points of a critical path where precise duty cycle definition is needed.

Abstract: A clock system includes a local clock buffer adapted to receive a variable global clock signal. The local clock buffer produces a first local clock signal from the variable global clock signal. The clock system includes a pulse width logic control circuit in operable communication with the local clock buffer. The pulse width logic control circuit may be adapted to limit the first local clock signal pulse width to be less than the variable global clock signal pulse width during a slow mode. The pulse width logic control circuit may be adapted to expand the first local clock signal pulse width to be greater than the variable global clock signal pulse width during a fast mode. The limited and expanded first local clock signals may signal a local evaluation circuit to address a memory line.

Abstract: In one embodiment, an apparatus may include a clock generator to generate a first clock signal. The apparatus may also include a serializer to generate serial data based on a transmit clock signal and parallel input data. The apparatus may also include a signal generator to generate at least two differential signals based on the first clock signal and the serial data.

Abstract: Systems and methods are disclosed including a duty cycle module having two timer circuits to measure pulse widths of a clock signal. Two comparators are used to generate control signals depending upon comparisons of the pulse width measurements. In response to the control signals, either the clock signal or an inverted clock signal may be programmably delayed such that combination of the clock signal and the inverted clock signal results in a corrected clock signal. Systems and methods are also disclosed for verifying operation of a duty cycle module.

Abstract: A receiver includes an antenna interface, a frequency translation bandpass filter (FTBPF), a sample and hold module, and a down conversion module. The antenna interface is operable to receive a received wireless signal from an antenna structure and to isolate the received wireless signal from another wireless signal. The FTBPF is operable to filter the received wireless signal to produce an inbound wireless signal. The sample and hold module is operable to sample and hold the inbound wireless signal in accordance with an S&H clock signal to produce a frequency domain sample pulse train. The down conversion module is operable to convert the frequency domain sample pulse train into an inbound baseband signal.

Abstract: Groups of phase shifted Pulse Width Modulation signals are generated that maintain their duty-cycle and phase relationships as a function of the period of the PWM signal frequency. The multiphase PWM signals are generated in a ratio-metric fashion so as to greatly simplify and reduce the computational workload for a processor used in a PWM system. The groups of phase shifted PWM signals may also be synchronized with and automatically scaled to match external synchronization signals.

Abstract: A method adjusts a pulse width of a signal. The method provides a fixed voltage input trigger pulse (34), of a certain pulse width, to a pulse width generator circuit (10) and provides an output pulse (52) from the pulse width generator circuit such that a pulse width of the output pulse is longer than the certain pulse width, without changing a voltage or frequency of the input trigger pulse. The method is used to drive an injector of a diesel reductant delivery system to inject fluid into an exhaust flow path.

Abstract: A pulse generator circuit is disclosed that is optimized for printed, solution-processed thin film transistor processing. In certain embodiments, the circuit comprises dual thin film transistors that operate as a diode and resistor, respectively. Optionally, a third thin film transistor may be provided to operate as a pass transistor in response to an enable signal. The elements of the circuit are configured such that a rising pulse on an input node triggers an output pulse on an output node in the manner of a monostable multivibrator.

Abstract: There are provided a pulse width modulation (PWM) signal generating circuit and a motor driving circuit. The PWM signal generating circuit includes: a proportional-to-absolute temperature (PTAT) voltage generating unit generating a PTAT voltage in proportion to an absolute temperature; a reference wave signal generating unit generating a preset reference wave signal; and a PWM signal generating unit comparing the PTAT voltage and the reference wave signal with each other to generate a PWM signal, wherein the PTAT voltage generating unit adjusts the PTAT voltage according to a control signal.

Abstract: A pulse generation circuit includes storage elements disposed in a dispersed arrangement on a substrate and operating in response to a pulse signal, delay elements each proximate to a storage element receiving a clock signal and providing a delayed output signal, and a pulse generation logic circuit performing at least one logic operation on the clock signal and the plurality of delayed output signals to generate the pulse signal.

Abstract: A method is disclosed for controlling a semiconductor component which includes a voltage controlled gate. The method includes determining and storing, prior to use of the semiconductor component, reference values of a gate voltage to be given to the gate of the semiconductor component during a change of operating states. The method also includes providing a pulse width modulated voltage from a driver circuit to a resistor connected to the gate of the semiconductor component according to the stored reference values of the gate voltage when a change in operating states of the semiconductor component is desired.

Abstract: In an embodiment of a converter, a first oscillator provides switching signals for switching between charging and discharging of a capacitor, and a second oscillator is configured to add an offset voltage or a feedback-current-dependent voltage to a sawtooth waveform generated by the second oscillator switched in synchronism with the first oscillator.

Abstract: A frequency multiplier in accordance with some embodiments of the inventive concept may include a pulse generator receiving a differential clock signal from a delay locked loop having a plurality of delay cells to generate a pulse signal for generation of a multiplication clock signal. The pulse generator comprises an intermediate pulse signal generation unit receiving the differential clock signal to generate intermediate pulse signals; and an overlap correction unit correcting an overlap between the intermediate pulse signals to generate correction pulse signals.

Abstract: The described embodiments provide a configurable clock circuit. The clock circuit includes a control and enable circuit and a clock distribution circuit. During operation, when a signal on an enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a clock mode, the control and enable circuit generates an enable signal on a control output to enable a signal on a clock input to propagate through the clock distribution circuit to the clock output. Alternatively, when a signal on the enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a pulse mode, the control and enable circuit generates a pulsed control signal on the control output to control a length of a pulse generated from the clock input on a clock output by the clock distribution circuit.

Abstract: An active infrared induction instrument powered by a dry battery capable of reducing power consumption through the adjustment of the emitter pulse width. The infrared emitted LED emits infrared signals, which, after being reflected by an object, are received by the infrared photodiode. The infrared signals received the infrared signals received by the infrared photodiode then enter an integrated circuit chip through a comparator. The pulse widths of the infrared emission pulse signals are dynamically adjusted after the width of the pulse series is received by the discrimination chip, thus reducing the emission power consumption to save energy.

Abstract: A clock system includes a local clock buffer adapted to receive a variable global clock signal. The local clock buffer produces a first local clock signal from the variable global clock signal. The clock system includes a pulse width logic control circuit in operable communication with the local clock buffer. The pulse width logic control circuit may be adapted to limit the first local clock signal pulse width to be less than the variable global clock signal pulse width during a slow mode. The pulse width logic control circuit may be adapted to expand the first local clock signal pulse width to be greater than the variable global clock signal pulse width during a fast mode. The limited and expanded first local clock signals may signal a local evaluation circuit to address a memory line.

Abstract: A method and apparatus for controlling the frequency of a clock signal using a clock-gating circuit is disclosed. In one embodiment, a root clock signal and an enable signal are provided to a clock-gating circuit. The clock-gating circuit is configured to provide an operational clock signal (based on the root clock signal) when the enable signal is asserted. The operational clock signal is inhibited when the enable signal is de-asserted. The frequency of the operational clock signal can be output at a reduced frequency (relative to the root clock signal) by asserting the enable signal for one of every N clock cycles. Furthermore, the frequency of the operational clock signal can be dynamically changed by changing the rate of asserting the enable signal relative to the root clock signal, without suspending operation of a functional unit receiving the operational clock signal.

Abstract: In one embodiment, a method includes generating a first signal based on a clock signal and generating a second signal based on a programmable delayed clock signal. The method then generates a reset signal based on the first signal and the second signal. The clock signal is delayed using an inverter chain to generate a delayed version of the clock signal. An output signal is generated based on the delayed version of the clock signal and the reset signal. When a pulse width of the output signal is greater than a data duration determined from the clock signal, the pulse width of the output signal is reset to the pulse width of the data duration.

Abstract: A circuit includes a duty cycle calibration circuit, a duty cycle detection circuit, and a feedback control circuit. The duty cycle calibration circuit is operable to generate a first clock signal based on a second clock signal using an inverter and a first transistor. The first transistor is coupled in parallel with a second transistor in the inverter. The duty cycle detection circuit is operable to generate a voltage signal that varies based on changes in a duty cycle of the first clock signal. The feedback control circuit is operable to generate a control signal based on the voltage signal. The duty cycle calibration circuit is operable to control the duty cycle of the first clock signal based on the control signal controlling a current through the first transistor.

Abstract: In various embodiments, systems and methods for generating high-precision pulse-width modulation include a delay-locked loop comprising multiple delay units having time-variable delays, control logic for selecting a subset S of the multiple delay units to thereby generate a time-invariant shift amount having a precision finer than that of a system clock and circuitry for applying the shift amount to rising and falling edges of a pulse-width modulation waveform to thereby generate a high-precision pulse-width modulation waveform.

Abstract: A duty cycle controlling circuit for adjusting duty cycle of a target clock signal to a desired value, comprises: a first duty cycle adjusting cell, for receiving a first duty cycle control signal to adjust duty cycle of an input clock signal to generate a first output clock signal as the target clock signal; and a duty cycle detecting module, for generating the first duty cycle control signal according to the first output clock signal.

Abstract: A PWM-signal-output circuit includes a first output unit to output a PWM signal with a first duty cycle, in a first period in which a motor starts rotating, a second output unit to output the PWM signal whose duty cycle increases toward a second duty cycle and decreases from the second duty cycle in a period from a logic level change in speed signal until its subsequent logic level change, in a second period following the first, the speed signal having a period corresponding to a motor-rotation speed and a logic level changing alternately, and a third output unit to output the PWM signal whose duty cycle increases toward that of the input signal and thereafter decreases from that of the input signal in a period from a logic level change in the speed signal until its subsequent logic level change, after the second period elapses.

Abstract: A slew rate boost circuit for an output buffer and an output buffer circuit for a source driver having the same are provided. In an output buffer including a pull-up unit providing a buffer output signal in a first level by receiving a buffer input signal and performing pull-up operation and a pull-down unit providing a buffer output signal in a second level having opposite phase from the first level by receiving the buffer input signal and performing pull-down operation, the slew rate boost circuit includes a first comparator generating a first boost signal to boost pull-up operation of the pull-up unit of the output buffer by inputting a first input signal and a second input signal and a second comparator generating a second boost signal to boost pull-down operation of the pull-down unit of the output buffer by inputting the first input signal and the second input signal.

Abstract: A duty adjustment circuit is provided. The duty adjustment circuit is used to adjust a duty cycle of a first driving signal. The duty adjustment circuit includes a filter, a first comparator, and a first duty adjustor. The filter receives a comparison result signal and filters the comparison result signal to generate a duty information signal. The duty information signal indicates a duty cycle of the comparison result signal. The first comparator receives the duty information signal and determines whether a direct-current (DC) level of the duty information signal falls into a predefined voltage range to generate a first adjustment signal. The first duty adjustor receives the first adjustment signal and the first driving signal and adjusts the duty cycle of the first driving signal according to the first adjustment signal.

Abstract: One embodiment relates to an integrated circuit which includes a transmitter buffer circuit, a duty cycle distortion (DCD) detector, correction logic, and a duty cycle adjuster. The DCD detector is configured to selectively couple to the serial output of the transmitter buffer circuit. The correction logic is configured to generate control signals based on the output of the DCD detector. The duty cycle adjuster is configured to adjust a duty cycle of the serial input signal based on the control signals. Another embodiment relates to a method of correcting duty cycle distortion in a transmitter. Other embodiments and features are also disclosed.

Abstract: An integrated circuit device includes a clock delay circuit configured to receive a clock signal and a pulse signal and to produce an output signal therefrom. The clock delay circuit is configured to transition the output signal to a first state responsive to a first state of the clock signal and to transition the output signal to a second state responsive to a first state transition of the pulse signal. The integrated circuit device further includes a pulse generator circuit configured to receive the clock signal and the output signal and to produce the pulse signal therefrom. The pulse generator circuit is configured to generate the first state transition in the pulse signal responsive to a transition of the clock signal to a second state and to generate a second state transition in the pulse signal responsive to the transition of the output signal to the second state.

Abstract: Groups of phase shifted Pulse Width Modulation (PWM) signals are generated that maintain their duty-cycle and phase relationships as a function of the period of the PWM signal frequency. The multiphase PWM signals are generated in a ratio-metric fashion so as to greatly simplify and reduce the computational workload for a processor used in a PWM system. The groups of phase shifted PWM signals may also be synchronized with and automatically scaled to match external synchronization signals.

Abstract: This document discusses, among other things, a system and method for reducing electromagnetic interference of a switched signal. In an example, a switched input signal can be received at an input and a transition rate of an edge rate controlled, switched output signal can be controlled in response to the received switched input signal.

Abstract: Systems and methods for generating pulse clocks with programmable edges and pulse widths configured for varying requirements of different memory access operations. A pulse clock generation circuit includes a selective delay logic to provide a programmable rising edge delay of the pulse clock, a selective pulse width widening logic to provide a programmable pulse width of the pulse clock, and a built-in level shifter for shifting a voltage level of the pulse clock. A rising edge delay for a read operation is programmed to correspond to an expected read array access delay, and the pulse width for a write operation is programmed to be wider than the pulse width for a read operation.

Abstract: A delay circuit includes a pulse generation unit configured to generate a pulse signal, which is activated in response to an input signal and has a pulse width corresponding to delay information, and an output unit configured to activate a final output signal in response to a deactivation of the pulse signal.

Abstract: In one embodiment, an apparatus may include a clock generator to generate a format clock signal. The apparatus may also include a serializer to generate serial data based on a transmit clock signal and parallel input data. The apparatus may also include a signal generator to generate at least two differential signals based on the format clock signal and the serial data.

Abstract: Circuits and a method for correcting duty cycle distortions in an integrated circuit (IC) are disclosed. The IC includes a splitter circuit that is coupled to receive a clock signal. The clock signal is split into two different clock signals. One of the clock signals is an inverted version of the other. A delay circuit is coupled to each of the clock signals. Each of the delay circuits generates a delayed version of the corresponding clock signal. A corrector circuit is coupled to receive both the delayed versions of the clock signals. The corrector circuit generates a clock output signal with a corrected duty cycle.

Abstract: A pulse generator is provided. The pulse generator includes: a time delayed pulse generation unit including a plurality of delay cells for receiving a first pulse having a first pulse width and outputting pulses delayed by a particular time delay value on the basis of one of a rising edge and a falling edge of the first pulse; an edge combiner configured to receive the plurality of time delayed pulses from the time delayed pulse generation unit and generate second pulses having a second pulse width; and a channel selector configured to regulate the number of outputs of the second pulses generated by the edge combiner.

Abstract: A low-cost ultra-versatile pulse width modulation (PWM)-timer controller system is disclosed for use in the electric power management industry. Using different voltage/current buffer devices, the present system is capable of performing a variety of control applications, including for example as a pulse width modulation controller, power factor correction circuit, silicon controlled rectifier or thyristor, zero-voltage drive circuit, AC/DC boost converter, battery charger, motor RPM controller, timer or clock, light intensity controller, temperature range controller, pressure controller, sensing/monitoring/warning system, or analog logic circuit.

Abstract: An controller for use in a power supply includes a variable oscillator and a digital-to-analog converter (DAC). The variable oscillator generates a switching signal having an on-time and a switching period to control a first switch to regulate an output of the power supply. The DAC provides the variable oscillator with a first analog signal and a second analog signal, where the on-time of the switching signal is responsive to the first analog signal and where the switching period is responsive to the second analog signal. The DAC includes a current source and a second switch that is configured to couple the current source to provide current to the first analog signal in response to a binary digit received by the DAC, and to couple the current source to provide current to the second analog signal in response to a complement of the binary digit.

Abstract: A pulse width modulation circuit of the present invention changes a voltage of a charging circuit based on an input signal voltage and in synchronization with a first switching signal; changes, during a predetermined second period following a first period during which the voltage of the charging unit is changed, the voltage of the charging unit in an opposite direction to a direction in which the voltage is changed during the first period, based on a constant bias current; detects time starting from when the second period starts to when the voltage of the charging unit reaches a predetermined reference voltage; and generates, based on the detected time which is repeatedly output each time the first switching signal is output, a pulse signal having a pulse width of the time.

Abstract: Duty-cycle correction circuits, clock distribution networks, and methods for correcting duty-cycle distortion are disclosed, including methods and apparatus for correcting duty-cycle distortion of differential output clock signals provided from a clock distribution network. In one such method, a single-ended clock signal is generated from differential input clock signals for distribution over a clock distribution network and from which the differential output clock signals are generated. A delay of a model delay path is matched to a propagation delay of the clock distribution network, and the single ended clock signal is adjusted to compensate for duty-cycle distortion.

Abstract: A power integrated circuit includes, in part, a multitude of controllers, a multitude of pulse-width generators, a multitude of output stages and a configuration matrix. Each controller is adapted to be responsive to a feedback signal and a reference signal to generate a control signal carrying pulse width information. Each control signal causes a difference between an associated output voltage feedback signal and the reference signal to be less than a predefined value. Each pulse-width generator is associated with and responsive to a different one of the controllers to generate a pulse-width modulated signal in response. The configuration matrix selectively couples the plurality of pulse-width generators to the output stages.

Abstract: A system is provided for generating an output clock used for N.5 modulus division. An edge-slip circuit accepts a modulus count, a divisor select signal, and a clock signal having a frequency greater than a modulus count frequency. The edge-slip circuit also has an input to accept an output clock signal, and an output to supply a clock slip signal (NE). An exclusive-or (XOR) has an input to accept a buffered clock signal (NF) and the clock slip signal (NE). The XOR has an output to supply the output clock signal. The output clock signal has a frequency equal to a buffered clock signal frequency, with no skipped clock edges, when the clock slip signal does not change logic levels. Alternatively, the output clock signal frequency is equal to the buffered clock signal frequency, with a skipped clock edge, when the clock slip signal changes logic levels.

Abstract: A method and apparatus to drive a load using a pulse-width modulated (PWM) signal and spread a spectrum of the PWM signal across a plurality of frequencies while maintaining a constant duty cycle for the load.