Abstract: A pulse generator is provided that includes: a current source, a source follower whose output controls the gate of a FET and a differential stage whose input voltage consists of inverting square waves and its output voltage consists of extremely narrow pulses widths, for example, of 30 to 40 ps and amplitude of 1.5 Volts.

Abstract: The control accuracy equal with the case controlled according to a reference signal with a high clock frequency when the electric power is converted is obtained according to a reference signal with a low clock frequency. The quantity of signal S3 of the time that corresponds to the difference of EO in the output voltage to reference voltage EREF by circuit 12 of the generation of quantity of signal of time is generated synchronizing with reference timing signal S1. The phase generates the class of the phase-shift signal of n piece for which only [Cycle of S0/]/n is late one by one by phase-shift signal generation circuit 13, counter circuit 14, and digital addition circuit 15, these numbers are counted respectively, and the count value of n piece is added. The control signal S5 that corresponds to TON between when adding value ADD is input with decision circuit 16 of on time of the switch element and control signal generation circuit 17 and it turns it on is generated.

Abstract: Dead-time gaps are inserted into one of two output transistor control signals from a digital pulse width modulator by controlling the leading and trailing edges using the same phase-division and dithering signals employed by the digital pulse width modulator. Adders add the phase select signals from the digital pulse width modulator and the dithering signal to the leading and trailing edge control signals, with the output employed by multiplexers as select controls in selecting a phase of from the phase-shifted versions of the system clock with which to clock latches controlling the leading and trailing edges.

Abstract: A time period control unit controls a time length “TU” of each of unit terms “U” in a variable manner. A pulse-width modulating unit is arranged by a holding unit, a counting unit, and a waveform generating unit. The holding unit holds thereinto a plurality of data “XD” every unit term “U”, which are sequentially supplied, as data “XE.” The counting unit changes a count value “X” during each of the unit terms “U.” The waveform generating unit generates such a pulse-width modulating signal “S” that pulses “P” have been arranged every unit term “U”, while time points when a large/small relationship between the count value “C” and a numeral value of the data “XE” held by the holding unit is inverted are defined as edge portions of the pulses.

Abstract: In one embodiment, a PWM controller is configured to inhibit forming a drive signal responsively to an overload sense signal having a value that is no greater than a first value for a first time interval and to form a first duration of the first time interval responsively to the overload sense signal.

Abstract: In a semiconductor memory device, a reference delay section has a first delay value and delays a first signal by a reference delay value obtained from the first delay value and an adjustment value while changing the adjustment value, and fixes the adjustment value when the first signal and the delayed first signal meet a predetermined condition. A delay section has a second delay value and generates an output signal based on a summation of the fixed adjustment value and the second delay value, and a set multiplication value in response to a trigger signal such that the output signal in an active state for a period corresponding to the set multiplication value.

Abstract: A receive interface circuit includes a duty cycle adjustment circuit that adjusts the duty cycle of a reference clock signal based, at least in part, on a selected number of duty cycle adjustment units and a selected range of duty cycle adjustment. The duty cycle adjustment circuit may select as the reference clock signal one of a clock signal and at least a lower version of the clock signal in parallel with the duty cycle adjustment.

Abstract: A pulse width modulation circuit includes a first electric-charge accumulator; a second electric-charge accumulator; a first current generator which generates a first current corresponding to the amplitude of an input AC voltage; a second current generator which generates a second current with a constant value; a first current supply controller which supplies the first current to the first electric-charge accumulator; a second current supply controller which supplies the second current to the first electric-charge accumulator; a third current supply controller which supplies the first current to the second electric-charge accumulator; a fourth current supply controller which supplies the second current to the second electric-charge accumulator; and a current limiter which limits the first current to a third current with a predetermined current value, if the amplitude of the AC voltage in the negative side exceeds a predetermined level.

Abstract: In general, in one aspect, the disclosure describes an apparatus having a capacitor to receive an input signal and to block DC portion of the incoming signal. A buffer is used to receive the DC blocked incoming signal and output an outgoing signal. A low pass filter is used to convert duty cycle error in an outgoing signal to a DC offset and to provide the DC offset to the capacitor. The DC offset is used to bias the capacitor. The biasing of the capacitor can adjust the DC blocked incoming signal so as to reduce the duty cycle error in the outgoing signal.

Abstract: Pulse width modulation signals are generated by identifying an event table having a plurality of events, each event including a time to next event parameter. Each desired pulse width modulation signal is characterized by a first event designating a transition from a first state to a second state and a second event designating a transition from the second state back to the first state. An event pointer is set to select a current event and the event table is repeatedly cycled through by updating the output for at least each pulse width modulation signal associated with the current event having a designated state transition, detecting that a time period has lapsed corresponding to the time to next event parameter associated with the current event, incrementing the event pointer to point to a next event in the event table and conveying each pulse width modulation signal to a corresponding circuit.

Abstract: In one embodiment, a PWM controller is configured to form a drive signal that has an operating frequency that varies around a center by a percentage of the center frequency.

Abstract: A clock duty changing apparatus changes a duty ratio of an input clock signal with nearly 50% duty ratio to a target value being externally supplied and outputs the input clock signal thereinafter as an output signal. The apparatus includes a duty regulation circuit and a duty correction circuit. The duty regulation circuit includes a delay selection circuit and an operation circuit. The delay selection circuit generates a delay signal by delaying the input clock signal by delay time determined based on a first control signal and a second control signal. The first control signal is externally supplied to the apparatus. The second control signal is generated by the duty correction circuit so that mismatch between the duty ratio of the output clock signal and the target value is reduced. The operation circuit generates the output clock signal by logic operation using the delay signal and the input clock signal.

Abstract: The present invention discloses a load-dependent frequency jittering circuit, comprising: a load condition detection circuit for receiving a switching signal and generating an output according to a load condition; a number generator for receiving the output of the load condition detection circuit and generating a number; a digital to analog converter for converting the output of the number generator to an analog signal; and an oscillator for generating a jittered frequency according to the output of the digital to analog converter.

Abstract: A digital pulse-width control apparatus including an input module, a digital delay locked loop, a plurality of programmable delay circuits connected in series, and a pulse-width modulation module is provided. The present invention uses the input module to vary a clock signal to reduce the limitation of a duty cycle of the clock signal to the digital pulse-width control apparatus.

Abstract: After an output signal S4 is level-inverted, first and second shorting FETs 55, 56 as a level-inversion inhibiting circuit inhibit level-inversion so that the signal is maintained to the inverted state. Thereafter the inhibition of level-inversion is released, when the signal is subsequently level-inverted at a proper time according to a desired duty ratio of a PWM signal S1. Thus chattering can be prevented and thereby a PWM signal S1 of a stable duty ratio can be generated, even if the level of a reference signal S3 fluctuates due to a noise or the like during vehicle acceleration, for example.

Abstract: Circuits, methods and apparatus are provided to control the duty cycle of a signal. The rising and falling edges of a signal can be delayed independently to provide the selection or tuning of the duty cycle of the signal. Additionally, the delays can be used to reduce skew among both edges of signals being provided or transmitted by a data interface. The delays can be made to not cause a high-Z during a transition of the signal.

Abstract: A duty cycle correction amplification circuit is disclosed and comprises a first amplifier comprising dual first MOS differential input transistors gated respectively by first and second reference signals, and adapted to generate first and second preliminary signals, a second amplifier comprising dual second MOS differential input transistors respectively gated by first and second preliminary signals and adapted to generate first and second internal signals, and a duty cycle corrector adapted to correct a duty cycle associated with the first and second internal signals, wherein one of the first and second internal signals comprises an amplified output signal having a corrected duty cycle.

Abstract: An integrated circuit includes a circuit for adjusting a voltage drop. The circuit includes a reference voltage node, an output node and a driver circuit coupled between the reference voltage node and the output node. The driver circuit includes an impedance causing a current flow through the driver circuit when a reference voltage is applied to the reference voltage node. A current source is coupled to the driver circuit to impress an adjustment current based on a control current such that the current flow through the driver circuit is adjusted to yield a desired voltage drop across the driver circuit.

Abstract: A current multiplier/divider-configured, feed-forward compensation circuit for a pulse width modulator (PWM) controller for a buck-mode DC-DC converter is operative to achieve constant loop gain irrespective of the magnitude of the input voltage, obviates the need for parameter calculations/adjustments of circuit components to conform with the PWM frequency selected by the user, and is effectively immune to variations in temperature and manufacturing process.

Abstract: A circuit and technique for adjusting and accurately controlling clock duty cycles in integrated circuit devices in which only N-channel current regulating transistors are used in the voltage-controlled inverters and both the rising and falling edges can be adjusted by cascading two such inverters. The potential for cascading of these inverters allows for additional accuracy to be achieved.

Abstract: An analog, duty cycle replicating frequency converter extracts duty cycle information from an input, pulse width modulated signal and generates an output pulse width modulated signal of the same duty cycle at a different frequency without regard to the frequency of the input signal. It uses bipolar transistor based circuitry, adaptable to an application specific integrated circuit, to derive voltages representing the on-time and period durations of the input signal, convert these voltages to currents representing the logarithms thereof, generate a voltage representing the difference between the currents, exponentially convert the voltage to a current representing the duty cycle and control an oscillator to generate an output pulse width modulated signal at a predetermined frequency with the duty cycle of the input signal.

Abstract: A pulse width modulator for use in a digital amplifier, includes a pop noise reducer for reducing pop noise by controlling a width and a phase of a pulse of a PWM signal output from the pulse width modulator, wherein the pop noise reducer contains: a PWM pulse register for storing a width and a phase values of a pulse of the PWM signal; and a pulse generator for outputting the PWM signal according to the values stored in the PWM pulse register. The pulse width modulator reduces pop noise generated when power supply to a digital amplifier is started and interrupted.

Abstract: A circuit for generating a square wave signal (UN2) comprising a DC voltage source (UG), a driver stage (TS), which alternately connects a control node (SK) to ground (GND) or the DC voltage (UG), a diode (D1) and a first capacitor (C1), which are coupled in series between a first pole (P1) of the DC voltage source and the control node (SK). The circuit further comprises an output stage (AS) comprising a first transistor (TR1) and a second transistor (TR2), which are connected such that the output stage (AS) the transistors are alternately conductive. The transistors (TR1, TR2) are coupled in series between a connecting node (N1), formed between the diode (D1) and the first capacitor (C1), and the control node (SK). A connecting node (N2) between the first transistor (TR1) and the second transistor (TR2) forms an output terminal for emitting the square wave signal.

Abstract: Apparatuses, circuits, and methods to reduce duty cycle errors are disclosed. Embodiments generally comprise buffer circuits coupled with error detection circuits and correction feedback circuits that sense duty cycles errors in output signals from the buffer circuits, generate error signals, and couple the error signals back to the inputs to correct or reduce the duty cycle errors. The error circuits may comprise active low pass filters in various embodiments, while amplifiers generally comprise inverter buffers or other simple buffers which alter or affect the input signals to the buffer circuits in order to reduce the duty cycle errors. In many system and apparatus embodiments, the error circuits comprise a resistor-capacitor circuit coupled with an inverter buffer. The error detection circuits generally function as active low pass filters and generate error signals for the feedback circuits.

Abstract: An apparatus includes a first trigger, a second trigger, a pulse generator, and a control unit. The first trigger generates a first trigger signal and a first level signal; the second trigger generates a second trigger signal and a second level signal; the pulse generator generates a digital output signal according to the first and the second level signals; and the control unit outputs the first and the second control voltages according to the digital input signal and the digital output signal.

Abstract: A clock recovery circuit includes a crossover adjustment circuit operable to adjust a crossover point to adjust a corresponding duty cycle. The adjustment circuit comprises a feedback adjustment combining element which is implemented as summing elements and a crossover point control clock amplifier, an operational amplifier with a resistor in place of a low pass filter at an input of the operational amplifier and feedback driver. The summing element within the feedback adjustment combining element combines input clocks with feedback signals, the crossover point control clock amplifier includes adjustment driver, the two cross coupled PMOS along with the resistor connected between them, reshape input clocks, adjust cross over point and provide output clocks with DCD corrected. A modified Miller capacitor comprising a resistor in series with a capacitor across a drain and gate of a cascode transistor pair is utilized in an output stage to adjust corner frequencies.

Abstract: A digitized method for generating pulse width modulation (PWM) signals is disclosed. In the digitized method, multiphase PWM signals are generated by altering the reference levels so that fully on duty cycle or fully off duty cycle of each phase PWM signal can be achieved. Therefore, the digitized PWM signal generation method in the present invention can be applied to any application apparatus having boost/buck converter.

Abstract: Determining a slew rate of a signal from an integrated circuit under test by comparing the signal with a first reference voltage, comparing the signal with a second reference voltage different from the first reference voltage, generating an output pulse having a pulse width indicative of a slew rate of the signal, and integrating the output pulse over time to generate an output voltage proportional to the pulse width; wherein the output voltage is indicative of the slew rate of the signal produced by the integrated circuit.

Abstract: In one embodiment, a power supply controller is configured to use a plurality of ramp signals to generate a plurality of PWM control signals.

Abstract: An RC oscillator circuit is disclosed. The RC oscillator circuit includes a current generator configured to generate a charge current. The RC oscillator circuit also includes an integrator having an input and an output, the input being connected to the current generator. The RC oscillator circuit also includes a comparator having a first input, a second input, and an output, the first input being connected to the output of the integrator and the second input being configured to supply a reference threshold. The RC oscillator circuit also includes a clock pulse generator connected to the output of the comparator and a reference generator configured to generate the reference threshold based on a supply voltage of the RC oscillator circuit.

Abstract: A modulator control circuit including a linear control circuit, a non-linear control circuit, and a combiner. The linear control circuit has an input receiving a compensation signal indicative of an output parameter and an output providing a first control signal. The non-linear control circuit has an input receiving the compensation signal and an output providing a second control signal. The non-linear control circuit senses transients of the compensation signal not otherwise detected by the linear control circuit and asserts the second control signal indicative thereof. The combiner combines the first and second control signals to provide a pulse width modulation signal for controlling the output parameter, such as output voltage or the like.

Abstract: An electronic device selects one of a plurality of input signals for coupling to an output channel. Individual pulldowns provide a separate pathway for each input, and are coupled to a common node which: is pre-charged to a voltage less than a system voltage. Each pulldown is coupled to a select line for gating an associated input signal.

Abstract: A sawtooth wave generating apparatus includes a base frequency generating section and a frequency generating section for generating the frequency of a reference signal, a sawtooth wave forming section which forms a sawtooth wave based on the reference signal, a voltage comparator which compares the voltage value of the sawtooth wave formed by the sawtooth wave forming section with a predetermined voltage value, a phase comparator which compares the phase of the output signal from the voltage comparator with the phase of the reference signal, and a low-pass filter (LPF) which cuts out a high frequency component of the output signal from the phase comparator, and feeds back the resulting output signal to the sawtooth wave forming section.

Abstract: A local on-chip programmable pulsewidth and delay generating circuit includes a clock generation circuit configured to receive a global clock signal and output a local clock signal. The clock generation circuit includes a pulse shaping portion which adjusts a pulse width of the global clock signal in accordance with at least one of a trailing edge delay and a leading edge delay. The leading edge delay is generated by a leading edge delay circuit, and the trailing edge delay is generated by a trailing edge delay circuit configured to apply a delay to a trailing edge of a pulse. The trailing edge delay circuit includes a delay chain having programmable stages of delay elements, each stage being independently controlled using control bits decoded from address latches.

Abstract: A voltage regulator is described for microelectronic devices using dual edge pulse width modulated control signal. In one example a first digital duty cycle value is received from a voltage controller and a pulse width modulated waveform is generated in response to the first duty cycle value, the waveform comprising a plurality of pulses with a modulated width. The waveform is applied to a voltage generator to generate a supply of power at a voltage determined by the duty cycle of the waveform. A second digital duty cycle value is received from the controller, and the leading edge of a subsequent pulse of the waveform is advanced if the second digital duty cycle value is greater than the first digital duty cycle. The trailing edge of the subsequent pulse of the waveform is advanced if the second digital duty cycle value is less than the first digital duty cycle value.

Abstract: A pulse-width control loop (PWCL) for clock with any pulse-width ratio within a wide range is provided. A differential programmable charge pump is employed to stabilize the current source by complementary connection. The differential programmable charge pump has a pair of differential charge pumps and a current source module to adjust the ratio of charge to discharge, so as to accelerate the range of the adjustable pulse-width ratio of the output clock and increase the output resolution. Further, a ratioless input control stage is employed to simplify the circuit design and avoid static power consumption. Moreover, the control stage adjusts rising pulse width and dropping pulse width at one period, thereby accelerating the lock speed and the range of the adjustable pulse-width ratio (i.e., duty cycle) of the input clock.

Abstract: A delay locked loop includes a storage element coupled to a data bus and produces a data synchronization signal. A phase detector receives a data clock signal and the data synchronization signal and produces a delay control signal. A first delay circuit produces a signal which is delayed relative to the data clock signal according to the delay control signal. A second delay circuit receiving the delayed signal produces a control signal coupled to a control input of the storage element by delaying the delayed signal an amount which causes the control signal to have a predetermined duty cycle.

Abstract: In an exemplary embodiment of the present invention, a local clock buffer (LCB) fabricated in a semiconductor receives a global clock signal as input. The LCB implements a pulse width controller that is operationally coupled to the LCB and an output driver forming a ring oscillator. The output driver outputs a pulse width adjusted signal. The pulse width of the pulse width adjusted signal is adjustable by way of the pulse width controller and is related in frequency to the global clock signal. A second ring oscillator (also referred to as the nclk loop) can also be implemented to server as the global clock signal. The pulse width controller can be used to precisely adjust the pulse width of the pulse width adjusted signal. A pulse width multiplier can be implemented to allow direct observation and measurement of the pulse width of the pulse width adjusted signal.

Abstract: A hybrid digital pulse width modulator can have a delay line with digitally programmable delay cells. The digitally programmable delay cells can be adjusted by a digital correction signal from a delay matching circuit.

Abstract: A pulse width modulation circuit 1 of the present invention changes the voltage of a first integration circuit C1 during the first period T1 of the clock signal MCLK based on a current based on an audio signal eS, changes the voltage of the first integration circuit C1 based on a constant bias current in the opposite direction while changing the voltage of a second integration circuit C2 during the second period T2, and changes the voltage of the second integration circuit C2 based on the bias current during the third period T3. The amount of time from the start of the second period T2 until the voltage of the first integration circuit C1 reaches the reference voltage Vth is detected, and the amount of time from the start of the third period T3 until the voltage of the second integration circuit C2 reaches the reference voltage Vth is detected.

Abstract: The duty cycle of a signal is modified by passing the signal through a plurality of inverting stages. The inverting stages each have bias circuitry to influence the input switching threshold of inverters. Multiple duty cycle modification circuits produce non-overlapping local oscillator signals in a system.

Abstract: In one embodiment, a PWM controller is configured to form a control signal that has reduced noise. The control signal is used to adjust a frequency of a clock signal of the PWM controller.

Abstract: A method and system process a signal for PWM modulation. An amplitude control signal adjusts the amplitude of an input signal, and an offset is added to the amplitude-adjusted signal to produce an offset-adjusted signal. The offset is selected according to the amplitude adjustment applied to the input signal. The offset-adjusted signal is pulse-width modulated the to produce a pulse-width modulated signal, and the pulse-width modulated signal is filtered to reduce high frequency components thereof.

Abstract: There is disclosed a duty ratio adjustment for adjusting the duty ratio of an input clock signal. First and second one-shot pulse generation circuits respectively detect rising/tailing edges of an external input signal and output pulse signals of constant widths. Third and fourth one-shot pulse generation circuits respectively detect rising/tailing edges of an output signal from the delay circuit and output pulse signals. A selector circuit outputs the pulse signals that are output from the third and second one-shot pulse generation circuits as H edge/L edge generation clock signals, when the L width is broadened, and outputs the pulse signals that are output from the first and fourth one-shot pulse generation circuits as H edge/L edge generation clock signals, when the H width is broadened.

Abstract: A pulse generating circuit includes a plurality of delay elements cascaded so as to constitute a predetermined loop, wherein when a predetermined input pulse is supplied to a leading end of the series connection, an effective frequency multiplication is applied to signals which appear at a plurality of portions out of the node portions among the plurality of delay elements and the terminal end portion of the series connection by a logical circuit to obtain an output pulse having a higher frequency than the input pulse.

Abstract: A system and method for generating a pulse stream are disclosed. A ramp signal is generated. The ramp signal is compared with a Time of Transition signal to produce a result indicative of the comparison. Responsive to the result of the comparison, the pulse stream signal is output. The result of the comparison instructs the selector whether to maintain the current output pulse stream signal or replace the current output pulse stream signal with a Polarity signal.

Abstract: A pulse width modulation circuit includes a first delay-locked loop (DLL) circuit and a second DLL circuit. The first DLL is coupled to a first multiplexer and has a first set of delay stages, wherein the first DLL circuit is configured to receive an input clock signal and, through the first multiplexer, produce a first stage delay signal associated with the first set of delay stages, wherein the first stage delay signal leads the input clock signal by a first duration.

Abstract: An semiconductor device, containing logic blocks and high speed connections between the blocks, where the connections utilize current direction for logic representation rather than voltage level. Such high speed connections comprise differential transmitters which drive a pair of adjacent wires with differential current pulses that are received by a differential receiver which may be put in a low power state between transmissions.

Abstract: A power amplification circuit includes first and second clock signal generating portions operable to produce, respectively, first and second clock signals different in frequency from each other; first and second PWM signal generating portions operable to produce first and second PWM signals based on first and second input signals using the first and second clock signals, respectively; a first switching amplifier operable to perform a switching operation in response to the first PWM signal to subject the first PWM signal to power amplification to produce a first output signal and to supply the first output signal to a first circuit load; and a second switching amplifier operable to perform a switching operation in response to the second PWM signal to subject the second PWM signal to power amplification to produce a second output signal and to supply the second output signal to a second circuit load.

Abstract: A high voltage linear current sense integrated circuit includes a differential amplifier circuit that can amplify a differential signal in the hundreds of millivolts near the power supply. In addition, a constant current using opposing minus temperature coefficient MOSFETs is provided. Accordingly, an op-amp circuit is provided with an input offset voltage which is constant and insensitive to temperature changes. A circuit for generating a current reference on the high side of the current sense IC also is provided.