Abstract: Provided is a digital duty cycle corrector for a multi-phase clock application which includes a flip-flop receiving a signal having a first clock cycle as an input and generating a reference signal having a cycle twice the first clock cycle, a duty corrector generating a signal having a second clock cycle that is half the cycle of the reference signal, from the reference signal, a duty detector measuring an amount of a duty error of the second clock cycle signal and generating a digital code value to control a duty cycle of the second clock cycle signal becomes 50%, and a phase inverter inverting a phase of the second clock cycle signal by 180° such that a rising edge of the second clock cycle signal is always fixed constantly regardless of a duty cycle correction operation.

Abstract: A remote voltage regulator module (VRM) for high-current, low voltage applications. In one embodiment, an electronic system includes a VRM configured to provide a DC output voltage. The VRM is coupled to a load board via a first bus bar and a second bus bar. The VRM includes a first capacitance of a first amount, while the load board includes a second capacitance of a second amount. A loop between the VRM and the load board is formed by the first and second bus bars and first and second capacitances. The loop is characterized by a transfer function that is second order or less.

Abstract: Disclosed is waveform width adjusting circuit that comprises: a delay circuit having a prescribed delay time is provided in a signal propagation path and a delay adjusting circuit which applies an adjustment in such a manner that when a waveform width extending from either a positive-going transition or a negative-going transition of the signal waveform at an input terminal to the next negative-going transition or positive-going transition is greater than the delay time of the delay circuit, a signal having a reduced waveform width is output, and such that when the waveform width of the signal at the input terminal is less than or equal to the delay time, the waveform width is not reduced and the signal that is output has the waveform width of the original signal. Thus, the waveform width of a signal for which the waveform width is less than a limit is not reduced.

Abstract: A pulse width modulator (100) and method that facilitates high resolution pulse width modulation is provided. The pulse width modulator (100) creates a pulse width modulated signal having a duty cycle that is proportional to a controllable delay in the modulator. The pulse width modulator combines a first digitally controllable delay (102) with a delay adjustment (104) to provide the controllable delay. In one embodiment, a digital counter (202) is used to provide coarse delay, with the delay adjustment device (210) coupled to the digital counter (202) to provide the fine, high resolution, delay control. Together the digital counter (202) and delay adjustment device (210) provide high resolution pulse width modulation. In one particular implementation, the analog delay adjustment device (100) comprises a delay block (500) designed to provide delay adjustment that is selectively controllable by changing a capacitance in the device.

Abstract: A slew rate calibrating circuit and a slew rate calibrating method are provided which are capable of adjusting, with high accuracy, a slew rate of a signal to be output to a transmission path. A first clock is input and a delay time of a variable delay circuit is increased or decreased so that a phase of the first clock coincides with a phase of a first differential buffer output signal which rises when a voltage of a transmission path outgoing signal is at the same level as a first reference voltage or exceeds the first reference voltage. Then, a second clock is input and a slew rate of an output buffer is increased or decreased so that a phase of the second clock coincides with a phase of a second differential buffer output signal which rises when a voltage of a transmission path output signal is at the same level as a second reference voltage or exceeds the second reference voltage.

Abstract: A duty ratio adjusting circuit has a differential buffer (11) to produce a pulse signal (Dout) according to an input sine wave signal (Ain) and a reference voltage. The pulse signal is inverted and filtered to be supplied to a first analog buffer (14) as a direct voltage. The first analog buffer outputs voltage equal to the direct voltage. A second analog buffer (15) has the same structure as the first analog buffer and outputs voltage equal to the reference voltage. A differential amplifying circuit (16) produces an output voltage (SDout) as the reference voltage according to the difference between voltages output from the first and the second analog buffers. Capacitor (17, 19) connected to lines connecting between the first and the second analog buffers and the differential amplifying circuit.

Abstract: Enclosed is a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop circuit. The duty cycle correction device includes a mixer for mixing phases of the first and second clock signals, thereby outputting a first signal, a phase splitter receiving the first signal and outputting a third clock signal, a duty detection unit receiving the third and fourth clock signals to detect a difference between duty cycles of the third and fourth clock signals, a combination unit for outputting a second signal, a shift register for outputting a first control signal, a phase detection unit receiving the first and second clock signals and outputting a second control signal representing a difference between duty cycles of the first and second clock signals. The mixer adjusts a mixing ratio by using the first and second control signals.

Abstract: Enclosed is a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop (DLL) device by using a phase mixer. The duty cycle correction device comprises: a mixer for receiving a first clock signal and a second clock signal and outputting a first signal; a phase splitter for receiving the first signal and outputting a third clock signal by delaying the first signal and a fourth clock signal by delaying and inverting the first signal; a duty detection unit for receiving the third and fourth clock signals and detecting a difference between their duty cycles; a combination unit for outputting a second signal; and a shift register for outputting a control signal to adjust a mixing ratio of the first and second clock signals in response to the second signal.

Abstract: The present invention related to an apparatus and a method for increasing a voltage level of duty correction voltages to a predetermined level during a predetermined time in a delay locked loop. An apparatus, included in a delay locked loop, includes a control block for generating a control signal keeping a first logic state during the predetermined time in response to a reset signal resetting the delay locked loop; and a voltage supplier for supplying the duty correction voltage with a supply voltage during the predetermined time in the control signal, wherein the duty correction voltage is for correcting a duty cycle of a clock signal used in the delay locked loop.

Abstract: A PWM buffer circuit includes a duty cycle converting circuit and a frequency-fixed PWM signal generating circuit. The duty cycle converting circuit is used for receiving a first PWM signal and then generating a duty cycle reference voltage on the basis of the first PWM signal. The duty cycle reference voltage is a one-to-one mapping function of the first duty cycle. The frequency-fixed PWM signal generating circuit is used for receiving the duty cycle reference voltage and then outputting a second PWM signal with a fixed frequency. The second PWM signal has a second duty cycle, which is determined in accordance with the duty cycle reference voltage. In addition, the second duty cycle is a one-to-one mapping function of the duty cycle reference voltage.

Abstract: A method and apparatus for reducing the duty cycle distortion of a periodic signal in high speed devices. More specifically, there is provided a device having a switching point modulation circuit coupled to input logic and configured to modulate the periodic output signal from the input logic such that the periodic output signal is centered about a known voltage signal, such as a switching point voltage signal.

Abstract: A method and apparatus for reducing the duty cycle distortion of a periodic signal in high speed devices. More specifically, there is provided a device having a switching point modulation circuit coupled to input logic and configured to modulate the periodic output signal from the input logic such that the periodic output signal is centered about a known voltage signal, such as a switching point voltage signal.

Abstract: The present invention provides a pulse width modulation (PWM) circuit comprising an PWM control circuit for setting an output signal to low when a logical level of a oscillation signal at a first input terminal changes from low to high, for resetting the output level to low in response to an effective input signal at a second terminal, a charge and discharge means for charging a first node (node1) when the output stays in low, for discharging the stored charge of node1 when the output stays in high, a comparator (C1) for outputting an output signal to the second terminal according to the first node signal and a first reference signal (Vref0), a discharge current controlling means for the stored charge on the first node, wherein the discharge current controlling means comprises a bias circuit 2 for controlling the discharge current based on constant current.

Abstract: A method, system, and apparatus are disclosed that correct a differential clock signal. A clock correction circuit may determine a DC correction for a first clock signal of a differential clock signal and a DC correction for a second clock signal of a differential clock signal based upon a DC level of the differential clock signal. The clock correction circuit may adjust a DC level of the first clock signal based upon the DC correction for the first clock signal and a DC level of the second clock signal based upon the DC correction for the second clock signal to substantially maintain a duty cycle of the differential clock signal.

Abstract: In one embodiment, a clock pulse width control circuit, comprises a plurality of timer circuits to generate a corresponding plurality of delayed pulse signals from an input clock signal, a corresponding plurality of AND gates, each AND gate generating an output signal from a delayed pulse signal and the input clock signal, and a selection circuit to select one of the output signals.

Abstract: A semiconductor device with a blind scheme for boosting an internal voltage using an external supply voltage is disclosed. The semiconductor device includes a voltage detector for detecting a voltage level of the external supply voltage being applied to the semiconductor device, a pulse generator for being controlled by a logic level value output from the voltage detector and generating a pulse signal having a variable pulse width, an internal voltage generator for generating the internal voltage for driving an internal circuit of the semiconductor device, and a driving unit for providing the external supply voltage to an output terminal of the internal voltage generator that outputs the internal voltage in response to the pulse signal.

Abstract: Embodiments of the invention provide methods and apparatuses for restoring a duty cycle of a complementary output signal pair. In one embodiment, the output signal pair is brought in phase with a complementary input signal pair by delaying a complementary intermediate signal pair from which the output signal pair is generated. The intermediate signal pair is switched to a first logic state in response to detecting a crossing point between rising and falling signals of the output signal pair. The intermediate signal pair is switched to a second logic state in response to detecting a crossing point between rising and falling signals of the input signal pair.

Abstract: The invention relates to a method of establishing a PWM-modulated output signal representation (OS), providing a stream of parallelly determined intersection representations (PIR) on the basis of a stream of parallel reference signal representation (PRSR) and an input signal (IS), establishing a serial PWM output signal representation (OS) by transforming said stream of parallelly determined intersection representations (PIR) into a stream of serial intersection representations (SIR) by means of a relative time shift of at least one of said parallelly determined intersections (PIR). According to an embodiment of the invention, an advantageous way of providing intersection estimates has been obtained, as each or at least a number of intersection estimates between a reference signal and an input signal may be established partially while taking only the individual partial reference functions into consideration.

Abstract: The present invention provides for correcting excessive pulse widths using incremental delays. The pulse width is evaluated through a correction block and leak detector. An acceptable pulse passes through an interconnect directly to the clock output. Unacceptable pulses are sent through a block delay module that incorporates a series of delay sub-blocks that disconnect and reset in accordance with a pre-programmed total delay time. The conditioned clock pulse is resent through a node to the correction block and leak detector where it is reevaluated. If the pulse is acceptable, it is sent to the clock output. If the pulse is found unacceptable, it is recycled again. A high low clock pulse shuttle determines and alters the high or low state of the clock pulse to ensure a correct output to downstream dependent devices.

Abstract: A pulse generator comprises a CMOS inverter, a capacitive device and a resistive device, where the CMOS inverter has two terminals connected to a source voltage and a reference voltage, e.g., ground, respectively, the capacitor device and the resistive device are connected to the input end of CMOS inverter, and pulses are generated at the output end of the CMOS inverter. The capacitive device is charged by a boost signal and discharged through the resistive device, so as to manipulate a potential at the input end of the CMOS inverter to control the operations of the transistors included in the CMOS inverter, thereby changing the level of the output voltage of the CMOS inverter. The widths of the pulses can be adjustable by a control signal received by the resistive device.

Abstract: A semiconductor memory device includes: a memory cell array, in which electrically rewritable and non-volatile memory cells are arranged; a sense amplifier circuit configured to be coupled to the memory cell array; a data transfer circuit disposed between the sense amplifier circuit and data input/output ports; a control signal generation circuit configured to generate a plurality of control signals based on a reference clock signal externally supplied, the control signals serving for controlling data input and output of the sense amplifier circuit and data transferring timing in the data transfer circuit; and an internal clock signal generation circuit configured to generate an internal clock signal based on the reference clock signal for serving as the basis of the control signals, the internal clock signal having the same clock cycle as the reference clock signal and a constant duty ratio without regard to the duty ratio of the reference clock signal.

Abstract: The invention relates to a pulse width modulator circuit for generating a reference signal having a desired duty cycle comprising an adjustment unit including at least one storage register and a counter, the storage register being configured for storing values corresponding to the desired duty cycle at least approximately and which are set during a working cycle in the pulse width modulator circuit for generating a reference signal, and the counter setting a cycle count Y indicating how often a stored first value X is read during the working cycle A from the storage register, the value stored in the storage register being variable during the working cycle.

Abstract: Integrated circuit, system, method and machine readable media embodiments adjust a slew rate and/or a transmit pre-emphasis of an output signal at selected phases during a bit time. A timing circuit provides a plurality of delayed data signals in response to a clock signal. A plurality of adjustable impedance circuits, including a plurality of select circuits, output a plurality of selected delayed data signals to form the output signal having an adjusted slew rate. Delay elements in the timing circuit are also biased from a current of a lock loop circuit to further adjust slew rate of the output signal. Transmit pre-emphasis of the output signal is adjusted by selecting a polarity of a selected delayed data signal in each of the plurality of adjustable impedance circuits. Each adjustable impedance circuit also includes a predriver and driver for adjusting impedance in response to a signal indicating an impedance value.

Abstract: A pulse delay circuit induces lager jitter to faster input reference pulse trains than before. A buffer receives a reference pulse train and provides non-inverted and inverted pulses. Low pass filters (LPF) and comparators receive the non-inverted and inverted pulses from the buffer and provide pulses having delayed leading and trailing edges. Dividers divide the delayed pulses by 2 to produce the respective pulse trains having a half frequency. An XOR gate produces an exclusive OR of the delayed and divided pulse trains to provide a pulse train having delayed leading and/or trailing edges relative to the reference pulse train. If the delays by the LPFs and comparators are changed, the output pulses from the XOR gate have jitter.

Abstract: A double frequency signal generator to which a synchronization signal having a duty cycle of 1% to 999% is inputted. The synchronization signal is used for triggering of a switching component at positive and negative edges to generate a triangular-wave signal. An average of voltages of the triangular-wave signal is acquired and compared with the triangular-wave signal at a comparator to generate a square-wave having a duty cycle of 50%. Then, the square-wave signal is used for triggering at positive and negative edges to generate a double frequency signal. As such, the high cost issue and the limitation of a square-wave input signal occurred in the prior art may be efficiently overcome.

Abstract: A duty cycle correction circuit for use in a semiconductor device, which synchronizes with an external clock and corrects a duty cycle, is provided. The duty cycle correction circuit includes a modulator of an inverter structure having at least one or more transistors. The modulator receives a control signal through a source terminal and a bulk of any one of the transistors and corrects a duty cycle in response to an external clock signal. The duty cycle correction circuit also includes a driver that converts an output signal of the modulator into a full swing level and outputs the converted output signal of the modulator, and a feedback loop that generates the control signal in response to an output signal of the driver.

Abstract: Hot swappable pulse width modulation power supply circuits preferably realized in integrated circuit form. The hot swap circuits provide for de-bouncing, controlled charging of the input capacitor of the power supply circuit and soft-start of the pulse width modulator after charging the input capacitor. Other features include a low voltage lockout, and an output for coupling to a synchronous rectifier driver to synchronize synchronous rectifiers on the secondary side of a coupling transformer in isolated systems. The hot swap capability may be disabled through an enable pin, or not implemented by not connecting the integrated circuit in a manner to use the hot swap capability.

Abstract: Delay-locked loop integrated circuits include a duty cycle correction circuit. This duty cycle correction circuit generates at least one output clock signal having a substantially uniform duty cycle in response to at least one input clock signal having a non-uniform duty cycle. The duty cycle correction circuit is also responsive to a standby control signal that synchronizes timing of power-saving duty cycle update operations within the duty cycle correction circuit. These update operations reset the set point of the correction circuit.

Abstract: A memory device having a duty ratio corrector which can reduce power consumption by blocking current paths between output terminals and a ground terminal by applying input signals for turning off switching devices for generating an auxiliary voltage for correcting a duty ratio at an initial stage, and which can improve an operational speed by changing the auxiliary voltage from a predetermined voltage, not 0V, to a target voltage.

Abstract: A method for adjusting the relative phases of two signals includes receiving first and second signals, which may, for example, be derived from a differential clock signal. A duty cycle error between the first signal and the second signal is detected by comparing a phase component of the first signal with a phase component of the second signal. This duty cycle error can then be corrected by delaying the second signal by an amount based upon a result derived from the comparing.

Abstract: Provided are a duty cycle correction circuit and method for duty cycle correction in a delay locked loop using an inversion locking scheme.

Abstract: Duty cycle correcting circuits having a gain adjusting circuit that selects one of a plurality of gains of the duty cycle correcting circuit based on a frequency of an input signal. An output circuit outputs a duty cycle corrected output signal based on the input signal and the selected one of the plurality of gains. The input signal may be an input clock signal and the output signal may be a corrected clock signal. Methods are also provided.

Abstract: A method and an apparatus to provide time-based edge-rate compensation have been disclosed. In one embodiment, the apparatus includes a reference pad, a reference circuit coupled to the reference pad, the reference circuit being operable to charge and to discharge a reference voltage at the reference pad, and an edge-rate detection and measurement circuit coupled to the reference pad to detect and to measure an edge-rate of the reference voltage at the reference pad. Other embodiments have been claimed and described.

Abstract: In a wave-shaping circuit, a charging switching element in series with an inductor is switched, a capacitor is charged with a back electromotive force generated by the inductor, a discharging switching element in series with a discharge resistor is switched, and the charge in the capacitor is discharged. By controlling the timing at which the charging switching element and the discharging switching element are switched, the power supply voltage can be increased and it is possible to generate a charge voltage for which the slope of the envelope can be determined. As a result, an output voltage with a desired output voltage waveform can be obtained from the charge voltage. The wave-shaping circuit is a simple circuit that does not include a transformer is used to increase the voltage of a low-voltage power supply and to form an output voltage waveform from a DC waveform.

Abstract: A pulse on edge circuit includes a first pull up transistor having its gate terminal coupled to a delayed control signal and a second pull up transistor having its gate terminal coupled to an inverted delayed control signal. A first and second pull down transistors are coupled in series between the first pull up transistor and a low voltage bias, wherein the gates of the first and second pull down transistors are coupled to the delayed control signal and inverted control signal, respectively. A third and fourth pull down transistors are coupled in series between the second pull up transistor and the low voltage bias. The gates of the third and fourth pull down transistors are coupled to a control signal and the inverted delayed control signal, respectively.

Abstract: Provided is directed to a circuit of controlling a pulse width and a method of controlling the same, which can remove failure possible to be generated during operations of a DRAM or a DDR in a high frequency by guaranteeing read and write operations of a stabilized data and a precharging time of a local input/output line, in response to identically adjust widths of a pulse synchronized with a clock and a target pulse, by means of comprising: a pulse comparator for comparing a target pulse with a pulse synchronized with a clock; a counter pulse generation circuit for generating a counter pulse according to an output of the comparator; a pulse counter circuit for outputting a plurality of pulse counter signals, sequentially, according to the counter pulse; and a pulse delay circuit for controlling the pulse width synchronized with the clock according to the plurality of pulse counter signals.

Abstract: Some microprocessors are designed such that the microprocessor core clock has a duty cycle of approximately fifty percent. When a clock signal propagates across power domains the clock signal pulse shape will change. The rising edges and falling edges of the clock signal will become asymmetrical (e.g., the duty cycle is no longer fifty percent). According to embodiments of the present invention, a parallel divide function is applied to a clock signal having a frequency f and its complement. The resulting four signals (i.e., f/2, its complement, f/2 at ninety degrees out of phase from f/2 and its complement) are applied to an XOR gate that combines them to generate a clock signal that has a duty cycle of approximately fifty percent and a frequency f, which is the same as the input clock signal.

Abstract: Provided is directed to a circuit for controlling a pulse width which can be adjustable to a next generation standard DRAM such as a high speed DDR2 or DDR3 as well as a high speed graphic DRAM for supplying various CAS latencies by means of including: a mode register set for setting a plurality of CAS latencies according to an operation frequency by a command inputted from a chip set; and a pulse generation circuit for generating a pulse having a variable width by using a delay time according to the plurality of CAS latencies set in the mode register set.

Abstract: The present invention provides an inverter controller comprising a drive circuit that generates a plurality of switch drive signals for inverter applications. In some exemplary embodiments, the drive circuit operates by reversing the command level of an error signal. In other embodiments, the drive circuit operates by using a half period of a sawtooth signal. In still other embodiments, the drive circuit operates by using a double period opposite shifting pulses method. The present invention also provides a PWM signal generator circuit that generates periodic PWM switch drive signals symmetrical to the minimum or maximum of a sawtooth waveform.

Abstract: Certain exemplary embodiments comprise a system, comprising: an electrical isolator adapted to couple a processor of a programmable logic controller to a user load; a transistor adapted to provide switching of a control signal provided by the processor for the user load; a totem pole output coupling the electrical isolator and the transistor and adapted to switch a gate of the transistor; and a power supply adapted to provide a floating regulated DC voltage to the gate of the transistor.

Abstract: A duty cycle correction circuit comprises an averaging circuit configured to receive a first signal and a second signal and provide a third signal, a duty restoration circuit configured to receive the third signal and a fourth signal and provide a fifth signal having a duty cycle closer to 50% than the first signal, and a synchronous mirror delay circuit configured to receive the fifth signal and provide the second signal.

Abstract: A control circuit is described in which a single input terminal receives digital control signals and analog control signals. In accordance with the principles of the invention, the control circuit includes an automatic power down circuit to place the control circuit into a low power draw or “sleep” mode whenever predetermined conditions are present. The automatic power down circuit monitors the single input terminal and when no demand for motor operation occurs for a predetermined period of time, the automatic power down circuit operates to place the control circuit into the low power draw mode.

Abstract: A duty cycle detector comprising a first circuit configured to receive clock cycles including a first level and a second level. The first circuit is configured to obtain a first value based on the length of the first level and to obtain second and third values based on the length of the second level. The first value is compared to the second and the third values to determine a duty cycle range of the clock cycles.

Abstract: A clock duty ratio correction circuit corrects a duty ratio of internal clock signals at 1:1. The clock duty ratio correction circuit comprises a clock buffer unit, a charge pump unit, a comparison control unit, a voltage comparison unit, a counter and a D/A converter. The clock duty ratio correction circuit converts a differential internal clock signal into a voltage level corresponding to the pulse width of the differential internal clock signal, and compares the voltage level to generate a count signal. Additionally, the clock duty ratio correction circuit divides a reference voltage at a predetermined ratio in response to the count signal to generate a duty ratio correcting signal, and corrects the duty ratio of the differential internal clock signal by using the voltage level difference of the duty ratio correcting signal.

Abstract: To facilitate measurement of the jitter tolerance of circuitry such as serializer/deserializer (SERDES) circuitry, test circuitry is provided that can add jitter to a data signal. The jitter added is preferably controllable and variable with respect to such parameters as jitter frequency (i.e., how rapid is the jitter) and/or amplitude (i.e., how large or great is the amount of the jitter).

Abstract: A PWM method and circuit. A temporary PWM signal is generated at a first frequency. The temporary PWM signal includes analog duty cycle information adapted for the first frequency. At least a portion of the analog duty cycle information is converted to digital duty cycle information adapted for a second frequency. A final PWM signal having a carrier frequency of the second frequency is generated from the digital duty cycle information.

Abstract: A duty cycle correction circuit and a delay locked loop (DLL) including the duty cycle correction circuit, are capable of controlling their operation in order to correctly analyze the cause of generation of a duty cycle error when the duty cycle error is generated in the DLL. The duty cycle correction circuit selectively outputs to a DLL core duty cycle offset information for controlling a duty cycle of an internal clock signal synchronized to an external clock signal under the control of a switching control signal. The DLL corrects the duty cycle of a reference clock signal according to the duty cycle offset information, thereby outputting a reference clock signal having a 50% duty cycle.

Abstract: There is provided a Delay Locked Loop (DLL) including a duty cycle correction circuit capable of controlling a duty error, when the duty error is generated in the DLL. The duty cycle correction circuit controls amounts of electric charges accumulated in storage units, in response to switching control signals received from the external, and outputs duty rate control signals each corresponding to a difference between the amounts of electric charges accumulated in the storage units. Therefore, the DLL including the duty cycle correction circuit can correct a duty cycle of a reference clock signal, in response to the duty rate control signals, and can output a reference clock signal with a duty cycle of 50%.

Abstract: A pulse width of a pulse having a nominal pulse width is modulated in accordance with a digital value to be communicated. The number of clock cycles that the modulated pulse width exceeds the nominal pulse width is counted. Various embodiments use a counter to determine the extent that the modulated pulse exceeds the nominal pulse width. The counter is initialized to a value (P) upon detection of a first edge of the extended pulse. The counter is configured to rollover or is reset when the counter reaches a count of P+M, where M represents the nominal pulse width count. In various embodiments, P is zero. The counter is halted upon detection of a second edge of the extended pulse. The resulting count represents the digital data value.

Abstract: A low-power, synchronous pulse width modulator utilizes a first clock signal at a first frequency to generate a pulse-width modulated signal at the first frequency without requiring a second over sampling clock signal that has a substantially higher frequency by selecting taps from a phase shifting structure to synthesize the waveform.