Abstract: A semiconductor device including an edge synchronizer which outputs a synchronized strobe signal generated by synchronizing a transition time point of a strobe signal with clock edges of a main clock or a sub clock, a detector which outputs a phase determination signal indicating a phase difference between the main clock and the sub clock in response to the synchronized strobe signal, and a duty ratio corrector which adjusts a duty ratio of the main clock and the sub clock in response to the phase determination signal.

Abstract: A time limiter protects a light emitting diode coupled to an output of a current driver by preventing the light emitting diode from working overtime under a high current and from being overheated and burnt down, no matter whether a pulse width of an input pulse is larger or shorter than a delay time of the time limiter. The input pulse may be a periodic continuous input pulse, or a continuously-enabled pulse generated from a run-time error of software or hardware. The time limiter should be coupled with a discharging circuit for discharging the capacitor in the RC circuit while a periodic continuous input pulse was inputted, to keep the precise original pulse period and pulse width of the enabling signal to be outputted, and to prevent the time limiter from malfunctioning.

Abstract: A method and a device for controlling and removing narrow pulses in a clock waveform using a delay function are disclosed. A circuit device includes three circuits wherein the first circuit is capable of generating an edge trigger signal in response to a waveform of an input signal and a waveform of an output signal. While the second circuit facilitates removing a narrow pulse from the waveform of the input signal, the third circuit is capable of generating a delayed output waveform having pulses greater than a predefined minimal pulse width. In one embodiment, the first, second, and third circuits are an exclusive OR gate, a delay circuit, and a D flip-flop, respectively.

Abstract: In a method for generating a PWM-signal to drive the power transistors of a half-bridge of a converter with the aid of a digital circuit, a digital reference value is compared to the counter content of a digital counting ramp, and a logic state of the PWM-signal is dependent upon whether the reference value is greater than the counter content of the counting ramp. In this context, at least two counters count counter contents of the counting ramp following one another in alternation, and the logic state of the PWM-signal is dependent upon whether the reference value is greater than the counter contents of counting ramps of each of the at least two counters.

Abstract: A pulse width modulation (PWM) wave output circuit that efficiently and accurately outputs dual PWM waves includes two comparators, an OR circuit, and an AND circuit. A voltage generator supplies the comparators with ramp voltages having the same wave height and shifted phases. The comparator compares the ramp voltages with the reference voltage and provides the comparison results to the OR circuit and the AND circuit. The OR circuit outputs a first modulation wave, and the AND circuit generates a second modulation wave. Accordingly, modulation waves having different duties are output based on ramp voltage having different phases.

Abstract: A phase doubler driver circuit includes a first input for receiving a input PWM drive signal. First control logic generates a first output PWM drive signal and a second output PWM drive signal responsive to the input PWM drive signal. In a first mode of operation, alternating pulses of the input PWM drive are output as the first output PWM drive signal and the second PWM output drive signal respectively. In a second mode of operation, the input PWM drive signal is provided as the first output PWM drive signal when a second phase current associated with the second output PWM drive signal exceeds a first phase current associated with the first output PWM drive signal and the input PWM drive signal is provided as the second output PWM drive signal when the phase current associated with the first output PWM signal exceed the phase current associated with the second output PWM signal.

Abstract: A data conversion/output device includes a number of sensors, voltage-time conversion circuits that are arranged adjacent to respective sensors and change output levels upon the lapse of times corresponding to output voltage values from the sensors after a conversion operation start point in order to convert voltage outputs of the sensors into times. The device also includes sensed data generation circuits for outputting, as digital data, lapse times until the output levels of the voltage-time conversion circuits change after a conversion start point. The sensed data generation circuits include a counter for counting a clock signal. An operation start of the voltage-time conversion circuits and a start of count operation of the counter are staggered.

Abstract: A Duty Cycle Correction (DCC) circuit is provide in which pairs of field effect transistors (FETs) in known DCC circuit topologies are replaced with linear resistors coupled to switches of the DCC circuit such that when the switch is open, the input signal is routed through the linear resistors. The linear resistors are more tolerant of process, voltage and temperature (PVT) fluctuations than FETs and thus, the resulting DCC circuit provides a relatively smaller change in DCC correction range with PVT fluctuations than the known DCC circuit topology that employs FETs. The linear resistors may be provided in parallel with the switches and in series with a pair of FETs having relatively large resistance values. The linear resistors provide resistance that pulls-up or pulls-down the pulse width of the input signal so as to provide correction to the duty cycle of the input signal.

Abstract: A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first and second control vernier is selected from the plurality of verniers, the first control vernier is programmed to a first delay, and the second control vernier is programmed to a second delay. The first and second control verniers are triggered together to generate respective first and second delay signals. A difference pulse signal is generated with a duty cycle corresponding to a difference between the generated first delay signal and second delay signal. The duty cycle of the pulse signal is compared to a duty cycle of the reference pulse signal to generate a difference signal pulse.

Abstract: An apparatus and method of providing a pulse width modulated signal that is responsive to a current are disclosed. A circuit according to aspects of the present invention includes a capacitor to convert a first current to a first voltage on the capacitor during a first time duration and to discharge a second current from the capacitor to change the first voltage to a second voltage during a second time duration. A comparator is also included and is coupled to an output of the capacitor to compare a voltage on the capacitor to a reference voltage during the second time duration to change a pulse width of a periodic output signal in response to an input current.

Abstract: A duty cycle comparator is described for comparing the duty cycles of two digital signals. The duty cycle comparator comprises a first controllable current source, a second controllable current source and a charge accumulation device. The comparator provides an output signal that is representative of the difference between the duty cycles independent of the frequency of the two digital signals.

Abstract: A circuit and method of correcting the duty cycle of digital signals is disclosed. The duty cycle of an input digital signal is measured and compared to a desired duty cycle. The leading edge of the input digital signal is passed to an output. The circuit and method adjust the falling edges at the output to achieve the desired duty cycle. The falling edges occur in response to rising edges of a delayed version of the input digital signal.

Abstract: Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a logic gate (414). The output of logic gate (414) is used as a power amplifier input signal (PA_IN) for radio frequency power amplifier (416). Depending on the relative time delay of the CKV clock signal (408) and the CKV_DLY delayed clock signal (420), the timing and duty cycle of the logic gate (414) duty cycle can be controlled. The duty cycle or pulse-width variation affects the turn-on time of the power amplifier (416); thereby establishing the RF output amplitude.

Abstract: An improved method and apparatus for transmitting digital signals in a communications channel by compensating for distortions due to attenuation of high frequency components suffered by the digital signals. In a preferred embodiment, the digital signals are pulses and the compensation is performed at the transmitter without the need for an emphasis driver, by widening the pulses to compensate for the distortion in the channel that results in narrowing of the pulses incurred in the channel. The resulting pulse train is pre-compensated for the distortions caused by the communications channel. The amount of pre-compensation can be determined statically or dynamically.

Abstract: A pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.

Abstract: The present invention provides a direct current generator and a pulse generator thereof. The pulse generator includes a comparator to replace a central processing unit and a logic integrated circuit to save the costs and space required by the electronic components. The pulse generator generates pulses to control the activation of the direct current generator and then to control the output current of the direct current generator. The direct current generator generates current having pulses based on pulses signals from the pulse generator to drive a load.

Abstract: A pulse modulated converter comprising an input stage (1) for generating a first control signal (2) based on an input signal (3) and a first feedback signal (4), and a comparator (5) for generating a pulse width modulated signal (6) based on said first control signal and a reference signal (7), means for providing a hysteresis when generating the pulse width modulated signal (6), a power stage (8) for generating an amplified pulse width modulated signal (9), an output filter (10) for filtering said amplified pulse width modulated signal (9), so as to create an analog output signal (11). In said pulse modulated converter, the first feedback signal (4) is formed as a combination of a second feedback signal (12) and a third feedback signal (13). The second feedback signal (12) is derived from the amplified pulse width modulated signal (9) using a first predetermined transfer function (14).

Abstract: A system for controlling a slew rate of a signal, such as used in an imaging device, comprises a counter for measuring a duration that the signal drops from a maximum voltage to a predetermined reference voltage; a register for retaining a desired duration that the signal drops from the maximum voltage to the predetermined reference voltage; and a comparator for comparing the measured duration to the desired duration, the comparator being operative of a current source for the signal. An anti-oscillation circuit prevents the system from oscillating between two discrete durations.

Abstract: A PWM generator system provides improved duty cycle resolution using a sub-cycle generator for generating a sub-cycle with a period that is a small fraction of the maximum PWM period to be generated. An integral sub-cycle estimator is coupled to said sub-cycle generator for determining the integral number of said sub-cycles for on and off time of the PWM waveform. An additional sub-cycle estimator determines the additional fractional sub-cycle required to provide the on and off time. A timer coupled to the integral sub cycle estimator and the additional sub cycle estimator controls PWM output switching for the on and off time of the integral and additional fractional sub cycles.

Abstract: A delay locked loop includes a storage element coupled to a data bus and produces a data synchronization signal. A phase detector receives a data clock signal and the data synchronization signal and produces a delay control signal. A first delay circuit produces a signal which is delayed relative to the data clock signal according to the delay control signal. A second delay circuit receiving the delayed signal produces a control signal coupled to a control input of the storage element by delaying the delayed signal an amount which causes the control signal to have a predetermined duty cycle.

Abstract: A duty detection circuit includes an integration circuit for receiving an RCLK signal and an FCLK signal that are internal clock signals generated by a DLL circuit, and generating voltage levels in accordance with the duty ratio of these internal clock signals; an amplifier for amplifying the output of the integration circuit; a latch circuit for latching the output of the amplifier; a control circuit for controlling the operation timings of each component; a bias circuit for feeding a BIAS signal to the integration circuit; and a frequency monitor circuit unit for monitoring the frequency of the clock signal. The frequency monitor circuit unit is a circuit component used when the power source is turned on, during resetting, and when other initial settings are performed, and detects the actual frequency of the clock signal and adjusts the amount of charging or discharging of the capacitors C1 through C4 in the integration circuit according to this actual frequency.

Abstract: The present invention relates to a switch control device and a converter including the same. According to an exemplary embodiment of the present invention, the switch control device includes a PWM controller for forcing a power switch to turn on when the power switch is turned off during a predetermined period, a current sensor for determining whether a current flows through the power switch, and a conditional counter for determining that an input voltage is input to a power transmission element by using a sense result of the current sensor and a number of times that the PWM controller turns on the power switch by force.

Abstract: A generator of a pseudoperiodic logic signal of mean period Tmean includes: a reference clock of period Tref, a logic memory, changing state on receipt of a pulse, a first mechanism producing a normal pulse on completion of a base time interval Tsec=K×Tref, with K an integer, a second mechanism producing a shifted pulse on completion of a modified time interval T?sec=(K±1)×Tref, and a selector capable of selecting the mechanism that produces the pulse, in such a way as to regularly include a shifted pulse so as to correct the mean period, to generate a pseudoperiodic signal. Such a generator may find application, as an example, to driving a resonator for producing a plasma spark for radiofrequency ignition.

Abstract: After an output signal S4 is level-inverted, first and second shorting FETs 55, 56 as a level-inversion inhibiting circuit inhibit level-inversion so that the signal is maintained to the inverted state. Thereafter the inhibition of level-inversion is released, when the signal is subsequently level-inverted at a proper time according to a desired duty ratio of a PWM signal S1. Thus chattering can be prevented and thereby a PWM signal S1 of a stable duty ratio can be generated, even if the level of a reference signal S3 fluctuates due to a noise or the like during vehicle acceleration, for example.

Abstract: The present invention is related to a method for treating a digital signal within a protocol handler which is part of a module coupled to a multiplex bus. The method consists in detecting the duty cycle of the digital signal, and in modifying said digital signal so that the modified signal contains the same data, but has a duty cycle of approximately 50%.

Abstract: An active infrared induction instrument powered by a dry battery capable of reducing power consumption through the adjustment of the emitter pulse width. The infrared emitting LED emits infrared signals, which, after being reflected by an object, are received by the infrared photodiode. The infrared signals received by the infrared photodiode then enter an integrated circuit chip through a comparator. The pulse widths of the infrared emission pulse signals are dynamically adjusted after the width of the pulse series is received by the discrimination chip, thus reducing the emission power consumption to save energy.

Abstract: A frequency jitter generator and a frequency jitter PWM controller are provided for overcoming the shortcoming that a conventional PWM controller reduces the electromagnetic interference issue by means of varying the operating frequency of the PWM controller based on an input voltage, while resulting in the uncertainty of the range of frequency jitter and the difficulty circuit design due to the effect of the input voltage and the load. The frequency jitter generator and PWM controller adjust the range of frequency jitter by using a signal within a fixed voltage range. The invention not only gets rid of the effect of the input voltage and the loading, but also simplifies the circuit design by fixing the range of frequency jitter no greater than a predetermined percentage regardless of the operating frequency of the PWM controller.

Abstract: An apparatus and method of providing a pulse width modulated signal that is responsive to a current are disclosed. A circuit according to aspects of the present invention includes a capacitor to convert a first current to a first voltage on the capacitor during a first time duration and to discharge a second current from the capacitor to change the first voltage to a second voltage during a second time duration. A comparator is also included and is coupled to an output of the capacitor to compare a voltage on the capacitor to a reference voltage during the second time duration to change a pulse width of a periodic output signal in response to an input current.

Abstract: The present invention relates to a duty correction circuit that corrects a distorted duty of a clock signal using a delay unit and a delay controller, thereby reducing the layout area and current consumption.

Abstract: A phase recovery circuit for avoiding noise interfering with the clock signal generated from an oscillator is disclosed. The phase recovery circuit includes a noise detector, a phase detector, and a phase locker. The noise detector detects noise and accordingly generates a noise detecting signal. The phase detector is triggered by the noise detecting signal for detecting the phase of the clock signal and accordingly generating a phase detecting signal. The phase locker locks the phase of the clock signal to a predetermined phase within a predetermined period after the occurrence of the noise detecting signal, and after the predetermined period, the phase locker releases the clock signal. In this way, the phase of the clock signal is not affected by noise.

Abstract: The present invention discloses a double-edge pulse width modulation (PWM) controller based on the output current and output voltage which is modulated in real time by the output current and the output voltage. The controller uses an extra first adder to sum up the compensation signal and a triangular signal (or a saw-tooth signal); a second adder to sum up the output current signal to a bias value; a PWM comparator, with its non-inverting input receiving the output of said first adder, its inverting input receiving the output of said second adder and outputs the PWM signal.

Abstract: Provided is a pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting state of a fuse on which information on a change of process is programmed, and a pulse generator provided with a plurality of delay cells with predetermined time delay for selectively increasing or decreasing the number of the plurality of delay cells depending on the delay increase signal and the delay decrease signal to generate an internal clock with a pulse width corresponding to the number of the increased or decreased delay cells.

Abstract: A circuit for controlling a pulse width of a refresh signal is provided. The circuit includes a first pulse width controller for receiving a first refresh signal having a first enable period, and generating a second refresh signal having a second refresh signal, and a second pulse width controller for receiving the second refresh signal, and generating a third refresh signal having a third enable period.

Abstract: A clock modulation circuit includes a modulation block that receives a fixed clock generated from a reference clock and buffers the fixed clock so as to generate a modulated clock. A correction unit is provided in the modulation block to correct the duty ratio of the modulated clock.

Abstract: A duty-cycle generator including, in one embodiment, a duty-cycle adjustment circuit and a delay processor. The duty-cycle adjustment circuit is adapted to receive an input clock signal having an input duty cycle, generate first and second versions of the input clock signal having different amounts of delay, and combine the first and second versions of the input clock signal to generate an output clock signal having an output duty cycle different from the input duty cycle. The delay processor is adapted to generate at least one control signal for controlling operations of the duty-cycle adjustment circuit based on a comparison of a characteristic of the output clock signal with a corresponding characteristic of a target output clock signal.

Abstract: A programmable local clock buffer for integrated circuit devices which is capable of varying initial settings is provided. The illustrative embodiments allow a single type of local clock buffer (LCB) to be used throughout an integrated circuit design while still being able to provide differing initial offsets and pulse widths for different local circuitry portions of the integrated circuit design. Delay circuit paths are provided, which provide discreet delay values, within the LCB that can be chained together when the LCB is instantiated to set the initial offset and pulse width values. When an LCB is instantiated in the integrated circuit device design, various ones of the delay circuit paths are connected together with the existing circuit paths of the LCB, i.e. the circuit paths that provide the pre-established offset and pulse width values, in order to set the initial offset and pulse width values for the LCB.

Abstract: A clock duty cycle correction (DCC) circuit for correcting a clock duty cycle of an external clock includes a phase comparator for comparing a phase of a rising clock with that of a falling clock to thereby output comparing signal; a DCC controller for outputting a DCC enable signal and a weight selection signal in response to the comparing signal and a first and a second lock state signal; a DCC mixing block for blending the rising clock and the falling clock in response to the DCC enable signal and the weight selection signal to thereby generate a rising and a falling pre-clock signals; and a clock selector for selectively output the rising and the falling pre-clock signals in response to the weight selection signal.

Abstract: A digital signal input device has a first input terminal and a second input terminal, a charging circuit connected between the first input terminal and the second input terminal, and a digital signal detection unit that outputs a digital signal of a logical value corresponding to a level of a charging voltage to an internal circuit. A pulse control unit generates a pulse signal having a fixed period using designated pulse width and pulse period. A switching element is provided between the charging circuit and the first input terminal or the second input terminal, which controls a period of applying a DC voltage to the charging circuit using a pulse width of the pulse signal.

Abstract: A signal generating circuit is provided. The signal generating circuit may include a plurality of delay circuits coupled to provide a plurality of control signals, a weighted-sum circuit to receive the plurality of control signals and to provide an output analog signal, and a comparator circuit to compare the output analog signal with a voltage and to provide a pulse width modulated (PWM) signal based on the comparison.

Abstract: A duty cycle correction circuit comprises a frequency divider, a duty cycle detector and a delay circuit. The frequency divider receives a first clock signal and divides the frequency of the first clock signal to generate a second clock signal. The duty cycle detector receives the second clock signal and a correction clock signal and generates a control signal according to the second clock signal and the correction clock signal. The delay circuit receives the first clock signal and the control signal and adjusts a delay time of a falling edge of the first clock signal according to the control signal to generate the correction clock.

Abstract: A pin setting circuit and a clock driving circuit are disclosed. The clock pin setting circuit sets the clock pin of the clock driving circuit. The pin setting circuit includes the double one-shot circuit and the switch circuit. The double one-shot circuit includes the first one-shot circuit and the second one-shot circuit. The first one-shot circuit receives a clock signal and generates a first control signal according to the frequency of the clock signal. The second circuit outputs a second control signal according to the first control signal generated. The switch circuit sets the clock pin to the power end or the ground end according to the second control signal.

Abstract: A CMOS integrated circuit (12) for correction of the duty cycle of a clock signal has a correction amplifier (16) to which a clock signal (14) is applied. The output of correction amplifier (16) is connected to an output buffer (18) and to an input of a duty cycle detector (20), the output of which is fed back to a control input (VC) of correction amplifier (16), thus forming a control loop. The duty cycle detector (20) comprises a buffer amplifier (22), an RC low pass circuit and a second inverter (24). A deviation of the duty cycle of the clock signal is detected in the duty cycle detector 20 and used to correct the duty cycle in the correction amplifier 16.

Abstract: In one embodiment, an error amplifier of a power supply controller is configured to receive a current sense signal prior to the current sense signal undergoing amplification.

Abstract: A duty detector may include a first amplifier and/or an integrator. The first amplifier may be configured to receive a first signal and a complementary first signal, differential-amplify the first signal and the complementary first signal, and/or output the differential-amplified first signal to an output terminal and the differential-amplified complementary first signal to a complementary output terminal. The integrator may be connected to the output terminal and the complementary output terminal of the first amplifier, configured to integrate the differential-amplified first signal and the differential-amplified complementary first signal, and/or configured to output a duty detection signal.

Abstract: Integrated circuit, system, method and machine readable media embodiments adjust a slew rate and/or a transmit pre-emphasis of an output signal at selected phases during a bit time. A timing circuit provides a plurality of delayed data signals in response to a clock signal. A plurality of adjustable impedance circuits, including a plurality of select circuits, output a plurality of selected delayed data signals to form the output signal having an adjusted slew rate. Delay elements in the timing circuit are also biased from a current of a lock loop circuit to further adjust slew rate of the output signal. Transmit pre-emphasis of the output signal is adjusted by selecting a polarity of a selected delayed data signal in each of the plurality of adjustable impedance circuits. Each adjustable impedance circuit also includes a predriver and driver for adjusting impedance in response to a signal indicating an impedance value.

Abstract: Disclosed is waveform width adjusting circuit that comprises: a delay circuit having a prescribed delay time is provided in a signal propagation path and a delay adjusting circuit which applies an adjustment in such a manner that when a waveform width extending from either a positive-going transition or a negative-going transition of the signal waveform at an input terminal to the next negative-going transition or positive-going transition is greater than the delay time of the delay circuit, a signal having a reduced waveform width is output, and such that when the waveform width of the signal at the input terminal is less than or equal to the delay time, the waveform width is not reduced and the signal that is output has the waveform width of the original signal. Thus, the waveform width of a signal for which the waveform width is less than a limit is not reduced.

Abstract: A pulse width modulation controller comprises a disabling unit, a level sensor and an over current protector. These three devices are all coupled to a multi-function node for accomplishing a disable function, input level sensing, and over-current protection, respectively.

Abstract: A semiconductor device and method of generating clock signals where a phase lock loop (PLL), or a delay lock loop (DLL), comprises a duty cycle correction circuit (DCC) having a shared charge pump and a plurality of amplification parts. The plurality of amplification parts generate internal clock signals. The shared charge pump adjusts voltage level of control signal (VC) in response to the internal clock signals and provides the control signal VC to each of the amplification parts.

Abstract: A system and method for generating a pulse stream are disclosed. A ramp signal is generated. The ramp signal is compared with a Time of Transition signal to produce a result indicative of the comparison. Responsive to the result of the comparison, the pulse stream signal is output. The result of the comparison instructs the selector whether to maintain the current output pulse stream signal or replace the current output pulse stream signal with a Polarity signal.

Abstract: An internal clock generator includes a detector, an internal signal generator and a clock output unit. The detector detects a transition point of an external clock signal and outputting a detection signal. The internal signal generator generates an internal signal in response to the detection signal and a pulse width control signal. The clock output unit outputs an internal clock signal having a pulse width, which is set based on the internal signal. A transition point of an external clock signal is detected and an internal clock signal is generated based on the detection result. It is therefore possible to maintain the pulse width of the internal clock signal to a set value regardless of variation in the pulse width of the external clock signal.