Abstract: A single integrated circuit DC-to-DC conversion solution that can be used in conjunction with product designs requiring at least two different DC-to-DC conversion ratios, and in particular both divide-by-2 and divide-by-3 DC-to-DC buck conversion ratios or both multiply-by-2 and multiply-by-3 DC-to-DC boost conversion ratios. Embodiments are reconfigurable between a first Dickson converter configuration that includes at least two non-parallel capacitors (any of which may be off-chip) and associated controlled multi-phase switching to achieve a first conversion ratio, and a second Dickson converter configuration that includes a lesser equivalent number of capacitors than the first circuit configuration (which may be accomplished by parallelizing at least two non-parallel capacitors of the first configuration) and associated controlled multi-phase switching to achieve a second conversion ratio different from the first conversion ratio.

Abstract: A single stage voltage quadrupler circuit includes a first capacitive voltage boosting circuit responsive to a first clock signal and operable to boost a voltage at a first node in response to the first clock signal from a first voltage level to a second voltage level that is substantially two times the first voltage level. A pass transistor selectively passes the boosted voltage at the first node to a second node in response to a control signal generated by a bootstrapping capacitor circuit in response to the level shifted first clock signal. A second capacitive boosting circuit is operable to boost the voltage at the second node in response to a level shifted second clock signal that is the logical invert of the level shifted first clock signal to third voltage level that is substantially four times the first voltage level.

Abstract: An apparatus includes a voltage regulation module configured to provide an output voltage signal (Vout) and an auto-calibration module configured to provide a calibration current signal (Isink) corresponding to a voltage difference between a target voltage signal (Vtarget) and the output voltage signal (Vout). The voltage regulation module may adjust the output voltage in response to changes in the calibration current signal. In one embodiment, the voltage regulation module comprises an output voltage resistor pair of resistance R1 and R2, respectively, and the output voltage signal conforms to the equation Vout=Isink·R1+Vref·(1+R1/R2).

Abstract: Bias circuit for power amplifier. In some embodiments, a bias circuit for an amplifier can include an input node, an output node, a supply voltage node, and a ground node. The bias circuit can further include a first transistor and a second transistor, with each transistor having a base, a collector, and an emitter. The base, collector and emitter of the second transistor can be coupled to the output node, input node and ground node, respectively. The base and collector of the first transistor can be coupled to the input node and supply voltage node, respectively. The bias circuit can further include a voltage adjustment circuit implemented between the emitter of the first transistor and the output node, and be configured to adjust a voltage at the emitter of the first transistor to a voltage at the output node.

Abstract: A low voltage detection circuit includes a first detection block configured to detect a level of an external voltage according to a reference voltage, and output a pre-detection signal; and a second detection block configured to generate a low voltage detection signal of a beginning level regardless of a variation in a level of the pre-detection signal when the level of the pre-detection signal is detected as the beginning level.

Abstract: A reference voltage generator for an analog-to-digital converter (ADC) includes a current source coupled to a power supply, and a first transistor coupled between the current source and a first resistive circuit. The first resistive circuit is coupled to the first transistor. The reference voltage generator further includes a second transistor having a gate coupled to the current source and a gate of the first transistor, for providing a reference voltage to the ADC, an impedance circuit coupled to the second transistor, for selectively providing a variable impedance.

Abstract: A power output circuit includes a charge pump, a voltage regulator, a clock generator and a voltage detector. The charge pump is used for receiving a clock signal having an operating frequency and outputting an output voltage. The voltage regulator, coupled to the charge pump, is used for outputting a control voltage to the charge pump, to control the output voltage. The clock generator, coupled to the charge pump, is used for outputting the clock signal to the charge pump. The voltage detector, coupled to the clock generator and the voltage regulator, is used for detecting the control voltage and controlling the clock generator to adjust the operating frequency of the clock signal according to a magnitude of the control voltage.

Abstract: A bipolar output charge pump circuit having a network of switching paths for selectively connecting an input node and a reference node for connection to an input voltage, a first pair of output nodes, two pairs of flying capacitor nodes, and a controller for controlling the switching of the network of switching paths. The controller is operable to control the network of switching paths when in use with two flying capacitors connected to the two pairs of flying capacitor nodes, to provide a first mode and a second mode when in use with two flying capacitors connected to the flying capacitor nodes, where at least the first mode corresponds to a bipolar output voltage of +/?3VV, +/?VV/5 or +/?VV/6.

Abstract: An apparatus for supplying power to an illuminant can be configured for use for different illuminants, a configuration can be chosen by a resistor on a secondary side of the apparatus. A primary side has at least one switch and a control device. The control device is set up to bring about clocked switching of the at least one switch in an operating phase in order to take a measured variable captured during the operating phase on the primary side, the measured variable is dependent on the resistor, as a basis for identifying a configuration stipulated by the resistor. The control device is set up in order to control the apparatus in a further operating phase on the basis of the identified stipulated configuration. A method for controlling the apparatus is also provided.

Abstract: In one form, a reference circuit includes a measurement circuit and a determination circuit. The measurement circuit has an output for providing a ratio of a difference in base-to-emitter voltage (VBE) of a bipolar device at different current densities to a VBE of the bipolar device at a first current density. The determination circuit has an input coupled to the measurement circuit, and an output for providing a digital value of a parameter in response to the ratio. In another form, the reference circuit further includes a voltage generation circuit having an input coupled to the determination circuit, and an output, for modulating an analog voltage using the digital value to provide a reference voltage to the output, wherein the reference voltage is temperature compensated over a temperature range.

Abstract: A power supply apparatus comprises: a transformer that includes primary/secondary windings that are electromagnetically connected to each other with polarities opposite to each other, an output switch that activates/inactivates an electric-current route that extends from an application terminal for an input voltage to a ground terminal via the primary winding a rectifying-smoothing portion that generates an output voltage from an induced voltage, a feedback voltage generation portion that monitors a switch voltage appearing at a connection node between the primary winding and the output switch and generates a feedback voltage in accordance with the output voltage, a reference voltage generation portion that generates a reference voltage, a comparator that compares the feedback voltage and the reference voltage with each other to generate a comparison signal, and a switching control portion that generates an output switch control signal by means of an on-time control method in accordance with the comparison si

Abstract: A semiconductor substrate of a first conductivity type having a first region of a second conductivity type formed in a surface thereof; an insulating film on the semiconductor substrate; a primary wiring line connected to the first region and configured to receive a voltage from outside; a plurality of diodes connected in series on the insulating film and having a spiral shape generally centering around the first region in a plan view, the diodes having one end of the series thereof connected to the primary wiring line and serving as a cathode; a resistor voltage divider having one end connected to another end of the series of diodes; a first connection wiring line connected to another end of the resistor voltage divider; and a second connection wiring line connected to a midpoint between the another end of the series of diodes and the another end of the resistor voltage divider.

Abstract: A hybrid D/A converter is provided including first and second D/A converters. The first D/A converter receives a digital signal having an input voltage and converts a first most-significant-bit of the digital signal to be converted to an analog signal. The first D/A converter includes first capacitors, which are charged by the input voltage and reference voltages during a sampling phase of the digital signal. Charges of the first capacitors are shared during successive approximations of first bits of the digital input signal received by the hybrid D/A converter. The second D/A converter converts a first least-significant-bit of the digital input signal. The second D/A converter includes second capacitors, which are charged based on a common mode voltage during the sampling phase. The second D/A converter performs charge redistribution by connecting the second capacitors to receive the reference voltages during successive approximations of second bits of the digital signal.

Abstract: An analog-to-digital converter includes comparator modules and an encoder module. Each of the comparator modules is configured to compare a reference voltage with an input signal according to a first clock signal to generate a first comparison signal and a second comparison signal, and to generate a detection signal according to a second clock signal, the first comparison signal, and the second comparison signal. A delay duration is present between the first clock signal and the second clock signal. The encoder module is configured to generate a first bit of digital data according to the first comparison signals from the comparator modules, and to generate a second bit of the digital data according to the detection signals from the comparator modules and the first bit.

Abstract: The present disclosure relates to an inverter type power amplifier. An exemplary embodiment of the present disclosure provides an inverter type power amplifier including: a first transistor including a gate to which an AC type of input signal is applied through an input port, a first terminal connected a power source voltage, and a second terminal connected to an output port; a second transistor including a gate through which the input signal is applied thereto, a first terminal connected to a ground, and a second terminal connected to the output port; a feedback resistor including a first terminal connected to the input port and a second terminal connected to the output port; and an AC blocking block including a first terminal connected to the output port and a second terminal connected to a DC output port.

Abstract: Reference signal generators using thermistors are disclosed. An apparatus includes a first device having a first temperature coefficient and a thermistor having a second temperature coefficient having a sign opposite to that of the first temperature coefficient. A circuit maintains equivalence of a first signal and a second signal and offsets a first temperature variation of the first device using a second temperature variation of the thermistor to generate the second signal having a low temperature coefficient. The first device may be a bipolar transistor configured to generate a base-emitter voltage and coupled in series with the thermistor. The first signal may be a first voltage on a first node. The second signal may be a second voltage on a second node. The circuit may be configured to maintain effective equivalence of the first voltage and the second voltage. The apparatus may include a resistor coupled to the second node.

Abstract: A voltage reference circuit with temperature compensation includes a power supply, a first reference voltage supply, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a resistor connected to the second NMOS source and ground. The voltage reference circuit also includes a second reference voltage supply, a third PMOS transistor, a fourth PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor with a drain connected to the source of the fourth NMOS transistor, a source connected to the ground, and a gate connected to the first reference voltage output.

Abstract: A semiconductor apparatus includes a reference voltage generation unit configured to generate a reference voltage. The semiconductor apparatus also includes an internal voltage generation unit configured to generate an internal voltage which corresponds to a voltage level of the reference voltage. In addition, the semiconductor apparatus includes a noise generation unit configured to generate noise in the reference voltage according to noise of the internal voltage.

Abstract: A NVM apparatus and an operation method thereof are provided. The NVM apparatus includes a NVM cell, a programming voltage generator, a WL-voltage generator and a CSL-voltage generator. A control terminal, and a first and second terminals of the NVM cell are electrically connected to a word line, a bit line and a common source line, respectively. The programming voltage generator provides a programming voltage to the bit line and detects a current thereof. The WL-voltage generator provides a WL-voltage to the word line, where a switch of the WL-voltage is a word line high voltage to a word line low voltage. The CSL-voltage generator provides a CSL-voltage to the common source line. According to the current of the bit line, the WL-voltage generator dynamical adjusts the word line low voltage, or the CSL-voltage generator dynamically adjusts the CSL-voltage.

Abstract: A voltage division circuit, a circuit for controlling operation voltage and a storage device are provided. The voltage division circuit includes: a receiving transistor; a transistor group including m transistors connected in series; n type-one switches, each of which includes three terminals, the first is connected with a drain of a former one and a source of a latter one of two adjacent transistors in the transistor group, the second is connected with ground, the third is adapted for receiving a timing control signal; and n+1 type-two switches, each of which includes three terminals, the first is connected with a source of a transistor in the transistor group, the second is adapted for outputting a divided voltage, and the third is adapted for receiving the timing control signal. The voltage division circuit can save chip area, and work properly under a condition that the voltage to be divided is low.

Abstract: A signal processing circuit includes: a reference signal generating circuit that generates a reference signal of a ramp waveform of which a voltage value varies with the lapse of time by changing a current; and a signal processing unit including a plurality of processing sections that process the reference signal as a ramp wave and a potential of a supplied analog signal, wherein the reference signal processing circuit has a function of adjusting an offset of the reference signal by adjusting the current from the time of starting the generation of the reference signal or adjusting the level of the reference signal at least at the time of starting the generation of the reference signal.

Abstract: A regulated charge pump power supply is implemented with a QP regulation loop providing QP clocking to control pumping operation based on sensing output voltage using residual charge on a flying capacitor Cfly. Cfly is used not only in normal charge pumping operation as an active charge shuttle element, but also to determine/measure output voltage VOUT. Voltage sensing using measured residual charge on Cfly is accomplished by introducing a sample phase into the normal charge pumping operation—after the pump phase and before the charge phase. In the sample phase, VOUT is determined (sampled) based on the residual charge on Cfly corresponding to (Vsense=VOUT?VIN). During the sample phase, the Cfly bottom plate is connected to ground, and the Cfly top plate is sampled (such as with a sense capacitor), with the sample phase completed prior to initiating a charge phase (by connecting the Cfly top plate to VIN).

Abstract: Embodiments of the invention are generally directed to a single-ended configurable multi-mode driver. An embodiment of an apparatus includes an input to receive an input signal, an output to transmit a driven signal generated from the input signal on a communication channel, a mechanism for independently configuring a termination resistance of the driver apparatus, and a mechanism for independently configuring a voltage swing of the driven signal without modifying a supply voltage for the apparatus.

Abstract: An internal voltage generator includes an internal voltage control unit suitable for generate an enable signal based on a voltage level of an internal voltage, a clock control unit suitable for generate a control clock having a restricted toggling period based on the enable signal and a clock while controlling the toggling number of the control clock, and an internal voltage generation unit suitable for generate the internal voltage based on the control clock.

Abstract: Embodiments of the invention are generally directed to a single-ended configurable multi-mode driver. An embodiment of an apparatus includes an input to receive an input signal, an output to transmit a driven signal generated from the input signal on a communication channel, a mechanism for independently configuring a termination resistance of the driver apparatus, and a mechanism for independently configuring a voltage swing of the driven signal without modifying a supply voltage for the apparatus.

Abstract: A boosting circuit is provided which performs an appropriate boosting operation in accordance with load capacitance. In the boosting circuit, a slope control circuit is provided between a limiter circuit, which limits a high voltage obtained by a charge pump circuit to a desired boosted voltage VPP, and a discharge circuit, which makes the boosted voltage VPP drop quickly to a power supply voltage VCC after the completion of writing, to enable a boosting operation in an appropriate boosted-voltage reach time, by increasing the time taken to reach the boosted voltage VPP in the case where the load capacitance is low, while keeping the time taken to reach the boosted voltage VPP unchanged, irrespective of the presence/absence of the slope control circuit, in the case where the load capacitance is high as in the case of selecting the memory cells collectively.

Abstract: Circuits and methods to control current through a device biasing an output device in case the supply voltage is not higher than the output voltage are disclosed. The circuits and methods are applicable to e.g. LDOs, amplifiers, or buffers. A control loop detects if the supply voltage is not higher than the output voltage and regulates the drain-source voltage of the biasing device. The disclosure reduces power consumption in a driver stage in case the supply voltage is not higher than the output voltage.

Abstract: Among other things, one or more stacked semiconductor arrangements or techniques for applying voltage schemes to such stacked semiconductor arrangements is provided. A stacked semiconductor arrangement comprises one or more tiers, such as a first tier comprising a first semiconductor structure, a second tier comprising a second semiconductor structure, or other tiers. A first voltage domain is applied to the first tier, such as a first substrate voltage of 0 v and a first power voltage of 1.6 v. A second voltage domain is applied to the second tier, such as a second substrate voltage of 1.6 v and a second power voltage of 3.3 v. In this way, semiconductor structures having different operational voltages are separated into different tiers, such as to mitigate damage to a lower voltage integrated circuit from a relatively higher voltage for a higher voltage integrated circuit.

Abstract: Apparatus and methods for variable capacitor arrays are provided herein. In certain configurations, an apparatus includes a variable capacitor array and a bias voltage generation circuit. The variable capacitor array includes a plurality of metal oxide semiconductor (MOS) variable capacitor cells, which include one or more pairs of MOS capacitors implemented in anti-parallel and/or anti-series configurations. In certain implementations, the MOS variable capacitor cells are electrically connected in parallel with one another between a radio frequency (RF) input and an RF output of the variable capacitor array. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the MOS variable capacitor cells.

Abstract: A system for pre-charging a current minor includes a controller configured to provide a first current and an additional current to a current minor to rapidly charge a capacitance associated with the current minor based on a reference voltage or control signals. A power amplifier module includes at least one current minor and a controller. A capacitor is coupled to the current minor. The controller provides a bias current in an amount proportional to an input to a voltage-to-current converter. The controller receives a control signal that directs the controller to apply one of a pre-charge voltage and a nominal voltage to the voltage-to-current converter.

Abstract: An apparatus comprises a first signal input, a first transistor, a first line, a first circuit coupled to the first transistor through the first line, a second line coupled to the first line between the first transistor and the first circuit, a second transistor coupled to the first transistor through the second line, a second circuit coupled to the second transistor, the first circuit being a replica of the second circuit, a second signal input, and a third transistor coupled to the second signal input and the second circuit. The apparatus maintains a virtual voltage of the second circuit above a predetermined threshold by a voltage associated with the second line. The voltage associated with the second line is based on a difference between a first current associated with a portion of the first line and a second current associated with another portion of the first line.

Abstract: Adaptive control of operating and body bias voltages. In accordance with a first embodiment of the present invention, a desirable operating frequency for the microprocessor is determined. Information stored within and specific to the microprocessor is accessed. The information can comprise coefficients of a quadratic approximation of a frequency-voltage characteristic of the microprocessor for a set of body biasing conditions. An efficient voltage for operating the microprocessor at the desirable operating frequency is computed. The microprocessor is operated at the efficient voltage and the set of body biasing conditions.

Abstract: According to an embodiment of a method, a semiconductor device is operated in a reverse biased unipolar mode before operating the semiconductor device in an off-state in a forward biased mode. The semiconductor device includes at least one floating parasitic region disposed outside a cell region of the device.

Abstract: Embodiments described in the present disclosure relate to a method for providing power for an integrated system, including acts of: providing the system with power, ground and body bias voltages, the body bias voltages comprising a body bias voltage of p-channel MOS transistors, greater or lower than the supply voltage, and a body bias voltage of n-channel MOS transistors, lower or greater than the ground voltage, selecting by means of the system out of the voltages provided, depending on whether a processing unit of the system is in a period of activity or inactivity, voltages to be supplied to bias the bodies of the MOS transistors of the processing unit, and providing the bodies of the MOS transistors of the processing unit with the voltages selected.

Abstract: A wake up circuit includes a bias signal control block configured to receive a sleep signal and to generate a plurality of bias control signals. The wake up circuit further includes a bias supply block configured to receive each bias control signal of the plurality of bias control signals and to generate a header bias signal. The bias supply block includes a first bias stage configured to receive a first bias control signal of the plurality of bias control signals, and to control the header bias signal to be equal to a first voltage. The bias supply block further includes a second bias stage configured to receive a second bias control signal of the plurality of bias control signals, and to control the header bias signal to be equal to a second voltage different from the first voltage. The wake up circuit further includes a header configured to receive the header bias signal, and to selectively connect a supply voltage to a load based on the header bias signal.

Abstract: A charge pump device is disclosed. The charge pump device includes a driving stage, for generating a driving signal corresponding to a driving capability; a charge pump circuit, for generating an output voltage according to the driving signal; a comparing circuit, comprising a first comparator for comparing the output voltage and a first reference voltage to generate a first comparing result; an overload detection circuit, for generating a detection result according to at least one of the first comparing result and the output voltage; and a driving capability control circuit, coupled between the overload detection circuit and the driving stage for controlling the driving capability corresponding to the driving signal according to the detection result.

Abstract: When writing into an antifuse memory element finishes, a value of resistance of the memory element rapidly decreases; accordingly, an output voltage of a boosting circuit which produces a writing voltage rapidly decreases. By detecting a change in the output voltage of the boosting circuit to control a writing command, the writing operation can be stopped immediately after the memory element is shorted. Thus, unnecessary current consumption caused by continuing a writing operation on the shorted memory element can be suppressed.

Abstract: A semiconductor apparatus includes a substrate structure including a silicon substrate layer, a conductive through-substrate via extending through the silicon substrate layer. The apparatus further includes a semiconductor device located in the substrate structure and a conductive wall located between the through-substrate via and the semiconductor device. The conductive wall is in electrical contact with the silicon substrate layer.

Abstract: A circuit configuration and methods for controlling parameters of a bipolar junction transistor (BJT) fabricated on a substrate. A bias voltage is electrically coupled to the substrate and can be adjusted to alter the working parameters of a target BJT.

Abstract: This disclosure provides circuits and methods for reducing sub-threshold leakage currents discharging floating nodes. In one aspect, feedback from a floating node is provided to a feedback transistor configured to bias other nodes such that leakage through turned-off transistors is reduced. Additionally, leakage contributing to static power consumption may also be reduced.

Abstract: Apparatus and methods for variable capacitor arrays are provided herein. In certain configurations, an apparatus includes a variable capacitor array and a bias voltage generation circuit. The variable capacitor array includes a plurality of metal oxide semiconductor (MOS) variable capacitor cells, which include one or more pairs of MOS capacitors implemented in anti-parallel and/or anti-series configurations. In certain implementations, the MOS variable capacitor cells are electrically connected in parallel with one another between a radio frequency (RF) input and an RF output of the variable capacitor array. The bias voltage generation circuit generates bias voltages for biasing the MOS capacitors of the MOS variable capacitor cells.

Abstract: A circuit, comprising a semiconductor device with one or more field gate terminals for controlling the electric field in a drift region of the semiconductor device; and a feedback circuit configured to dynamically control a bias voltage or voltages applied to the field gate terminal or terminals, with different control voltages used for different semiconductor device characteristics in real-time in response to a time-varying signal at a further node in the circuit.

Abstract: A semiconductor device includes a power supply voltage level/slope detection unit configured to detect a level of a power supply voltage and a slope of a power supply voltage curve, and output a power supply voltage level/slope detection signal, a pumping voltage detection unit configured to detect a level of a pumping voltage based on a reference pumping level to output a pumping detection signal, an oscillation signal generation unit configured to generate an oscillation signal in response to the pumping detection signal and the power supply voltage level/slope detection signal, and a pumping unit configured to generate the pumping voltage by performing a charge pumping operation in response to the oscillation signal.

Abstract: A multi-terminal output with a common mode connection includes an output having a first terminal and a second terminal and having a common mode connection between the first terminal and the second terminal. A bulk connection of a transistor is coupled to the common mode connection. A first set of control signals and a second set of control signals are generated. Each of the first set of control signals has a first rail voltage level associated with a first power domain. The second set of control signals is generated from the first set of control signals. Each of the second set of control signals has a second rail voltage level that is associated with a second power domain. The second power domain is associated with a common mode voltage of outputs of an output driver.

Abstract: An internal voltage generation circuit of a semiconductor apparatus includes: an active driver configured to output an internal voltage to an output node; a standby driver configured to output the internal voltage to the output node; and a voltage stabilizer connected to the output node. The voltage stabilizer starts a voltage stabilization operation of supplying or receiving electric charges to or from the output node when an active enable signal is disabled, and stops the voltage stabilization operation in a predetermined time after to the active enable signal is enabled.

Abstract: A semiconductor integrated circuit according to an embodiment includes an oscillator that generates and outputs an oscillation signal in an active state and generates no oscillation signal in an inactive state. The semiconductor integrated circuit includes a negative charge pump that generates an output voltage that is a negative voltage in response to the oscillation signal and outputs the output voltage to an output pad. The semiconductor integrated circuit includes a negative voltage detecting circuit that detects the output voltage and controls the oscillator to be in the active state or inactive state so as to bring the output voltage close to a target voltage.

Abstract: A voltage generator includes a boosting circuit boosting a power voltage to generate first through fourth voltages, and a boosting controller controlling the boosting circuit. The boosting controller sets the third and fourth voltages to a voltage level lower than that of a ground voltage while the first and second voltages are generated, so that a plurality of voltages may be stably generated, i.e., without latch-up.

Abstract: A charge pump system includes a charge pump that receives its clock signals, generated by an oscillator circuit, though a clock buffer. The clock buffer is power-controlled to reduce power consumption and output voltage ripple. The buffer is formed of a series of inverter that are connected to the power supply level through a clamping element, such as a transistor whose gate is controlled by a regulation signal based on feedback from the pump's output.

Abstract: A charge pump system includes a charge pump that receives its clock signals, generated by an oscillator circuit, though a clock buffer. The clock buffer is power-controlled to reduce power consumption and output voltage ripple. The buffer is formed of a series of inverter that are connected to the power supply level through a clamping element, such as a transistor whose gate is controlled by a regulation signal based on feedback from the pump's output.

Abstract: A semiconductor element and a manufacturing method and an operating method of the same are provided. The semiconductor element includes a substrate, a first well, a first heavily doping region, at least a second heavily doping region, a gate layer, a third heavily doping region, and a fourth heavily doping region. The first well and the third heavily doping region are disposed on the substrate. The first and fourth heavily doping regions are disposed in the first well. The second heavily doping region is disposed in the first heavily doping region. The gate layer is disposed on the first well. The first, third, and fourth heavily doping regions having a first type doping are separated from one another. The first well and the second heavily doping region have a second type doping complementary to the first type doping.