Abstract: A semiconductor device includes a boosting circuit that boosts an internal power supply voltage in a boosting range according to an external power supply voltage, an external voltage-level comparison circuit that compares the external power supply voltage and a predetermined reference voltage, and a variable resistor circuit that includes a variable resistor connected to an output terminal of the boosting circuit. The variable resistor circuit controls a resistance value of the variable resistor based on a comparison result of the external voltage-level comparison circuit.

Abstract: In one embodiment, a method is provided for preventing reverse input current from flowing into a power source.

Abstract: Methods, devices, and systems are provided for a power generator system. The power generator system may include at least one control device including control logic. The at least one control device may be configured to receive at least one control signal and output an upper reference voltage and a lower reference voltage. The at least one control device may be further configured to vary a magnitude of at least one of the upper reference voltage and the lower reference voltage. The power generator system may also include a power generator operably coupled to the at least one control device and configured to receive the upper reference voltage and the lower reference voltage. The power generator may be further configured to output a voltage that is greater than or equal to the lower reference voltage and less than or equal to the upper reference voltage.

Abstract: Provided are an internal supply voltage generator capable of reducing latch-up and a semiconductor device having the same. The internal supply voltage generator generates at least one internal supply voltage, and includes a first booster circuit that generates a first voltage from a first reference voltage and an input voltage and outputs the first voltage via a first output terminal, a second booster circuit that generates a third voltage from a second voltage and the first voltage and outputs the third voltage via a second output terminal, and at least one switch that is disposed to correspond to at least one of the first output terminal and the second output terminal and adjusts at least one of the first voltage and the third voltage.

Abstract: A technique for increasing the charge storage capacity of a charge storage device without changing its inherent charge transfer function. The technique may be used to implement a charge domain signal processing circuits such as Analog to Digital Converters (ADCs) used in digital radio frequency signal receivers.

Abstract: Provided is a semiconductor integrated circuit apparatus capable of controlling the substrate voltage of a MOSFET so that the drain current for an arbitrary gate voltage value in a subthreshold region or a saturated region will be free from temperature dependence and process variation dependence, thereby enhancing the stable operation thereof. The semiconductor integrated circuit apparatus includes: an integrated circuit main body having a plurality of MOSFETs on a semiconductor substrate; a monitor unit for monitoring at least one of the drain currents of the plurality of MOSFETs; and a substrate voltage regulating unit for controlling the substrate voltage of the semiconductor substrate so as to keep constant the drain current.

Abstract: A system for pre-charging a current mirror includes a controller configured to provide a first current and an additional current to a current mirror to rapidly charge a capacitance associated with the current mirror based on a reference voltage or control signals. A power amplifier module includes at least one current mirror and a controller. A capacitor is coupled to the current mirror. The controller provides a bias current in an amount proportional to an input to a voltage-to-current converter. The controller receives a control signal that directs the controller to apply one of a pre-charge voltage and a nominal voltage to the voltage-to-current converter.

Abstract: A device includes, but is not limited to, a first transistor, a first current mirror circuit, a second transistor, and a first compensation circuit. The first transistor is controlled by a first control voltage. The first current mirror circuit is driven by the first transistor as a first current source. The second transistor is driven by the first current mirror circuit. The second transistor has a first output voltage that varies depending on the first control voltage. The first compensation circuit reduces variations of the first output voltage. The variations of the first output voltage are caused by variations in performance of the first and second transistors.

Abstract: A circuit includes a complementary current mode logic driver circuit and a dual feedback current mode logic bias circuit. The complementary current mode logic driver circuit provides a first output voltage and a second output voltage. The dual feedback current mode logic bias circuit includes a first feedback circuit and a second feedback circuit. The first feedback circuit provides a first bias voltage for the complementary current mode logic driver circuit in response to the first output voltage. The second feedback circuit provides a second bias voltage in response to the second output voltage.

Abstract: A method for compensating negative bias temperature instability (NBTI) effects on a given model of transistors includes monitoring the NBTI effects on the transistors over time, determining a change in a threshold voltage of the transistors over time based on the monitoring, determining a forward bias voltage based on the change in threshold voltage, and applying the forward bias voltage to the transistors over time. The method may further include storing the monitoring results in a lookup table, and adjusting the forward bias voltage based on the lookup table. The monitoring may include emulating the NBTI effects on a system comprising a plurality of semiconductor devices in which the transistors are used.

Abstract: Herein, a voltage sensing circuit, which is capable of controlling a pumping voltage to be stably generated in a low voltage environment, is provided. The voltage sensing circuit includes a current mirror having first and second terminals, a first switching element configured to control current on the first terminal of the current mirror by a reference voltage, a second switching element configured to control current from the second terminal of the current mirror in response to a pumping voltage, and a third switching element configured to control current sources of the first and second switching elements to receive a negative voltage.

Abstract: A semiconductor apparatus includes a constant voltage circuit that converts an input voltage and outputs a prescribed constant voltage. The constant voltage circuit includes an output transistor that receives an input of a control signal and outputs a current (from an input terminal to an output terminal) in accordance with the control signal. Also included is an error amplifier circuit that controls the output transistor to create a voltage in proportion to an output voltage outputted from the output terminal becomes a prescribed reference level. A direct current power source supplies direct current power to the constant voltage circuit. A voltage creating circuit creates and outputs a voltage higher than that of the direct current power.

Abstract: A boosting circuit includes first to fourth rectification elements, first to fourth MOS transistors, first to fourth capacitors, and a switch circuit. The switch circuit has a low level terminal connected to a first connection node between the first end of the third rectification element and the first end of the fourth rectification element, and a high level terminal connected to a second connection node between a second end of the third MOS transistor and a second end of the fourth MOS transistor. The switch circuit conducts changeover between a voltage at the low level terminal and a voltage at the high level terminal to output a resultant voltage to the output terminal.

Abstract: A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit consisting plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source and the body terminal of the PMOS transistors are coupled a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors.

Abstract: A power supply controller is provided for providing a drive current to a control terminal of a power transistor in three time intervals. The controller includes control circuits configured to control the drive current in multiple stages. During a first time interval, first drive current includes a current spike for turning on the power transistor in response to a start of the control signal pulse. During a second time interval, a second drive current includes a ramping current substantially proportional to a magnitude of a current through the power transistor. During a third time interval, current flow to the power transistor is at least partially turned off before an end of the control signal pulse.

Abstract: A fault tolerant driver circuit includes a data output driver that receives an enable input and that includes a transistor formed on an isolation well. A well bias circuit provides a first well bias to the isolation well. The well bias circuit includes voltage-controlled impedances that are controlled by a voltage of the data output line, the enable input and a supply voltage. The voltage-controlled impedances connect the first well bias alternatively to: a common conductor through a first impedance when the supply voltage is ON and the enable input is ON; and a second impedance when the supply voltage is on and enable is OFF.

Abstract: In a power supply apparatus for performing constant current driving of a light emitting diode which is a load circuit, a constant current circuit is disposed on a path for driving the load circuit. A charge pump circuit which is a voltage generating circuit outputs a driving voltage to the light emitting diode. A monitoring circuit monitors the voltage across the two ends of the constant current circuit. This monitoring circuit includes a voltage source which generates a threshold voltage that follows the fluctuation of the voltage at which the constant current circuit can operate stably, compares the voltage across the two ends of the constant current circuit and the threshold voltage generated by the voltage source, and outputs a comparison result Vs to a control unit. The control unit controls the charge pump circuit on the basis of the output of the monitoring circuit.

Abstract: Disclosed are a high voltage pumping circuit and a VPP pumping method using the same. The high voltage pumping circuit includes an initializing unit for initializing a high voltage in response to a first enable signal, a first pump for pumping the high voltage in response to the first enable signal, a second pump for pumping the high voltage in response to a second enable signal and a first mode signal, and a mode signal transmitting unit for generating a second mode signal in response to the second enable signal and the first mode signal. The driving of the initializing unit and the first pump is controlled in response to the first pump and the second mode signal.

Abstract: A circuit for generating negative voltage of a semiconductor memory apparatus includes a first detecting unit configured to generate a first detecting signal by detecting a first negative voltage level, a first negative voltage generating unit configured to generate the first negative voltage in response to the first detecting signal, a second detecting unit configured to generate a second detecting signal by detecting the second negative voltage level, a timing controlling unit configured to output the second detecting signal as an enable signal when a power up signal is enabled and the first detecting signal is disabled, and a second negative voltage generating unit configured to generate the second negative voltage in response to the enable signal.

Abstract: In many applications, “dying gasp” periods following power down are used. Conventional circuits supply energy for the “dying gasp” periods generally by use of large external capacitors that are bulky and expensive. Here, a dying gasp charge controller is employed that allows for the use of smaller capacitors at higher voltages, which maintains or exceeds the energy storage capacities of conventional circuits.

Abstract: Embodiments related to operating a high-side switch in a safety-related application are described and depicted.

Abstract: A voltage generation circuit includes a high voltage detector (HVD), a clock signal control unit (CSCU), an oscillator, a pumping clock control unit (PCCU), and a charge pump. The HVD compares a high voltage applied to a memory cell array with at least one reference voltage to provide at least one comparison signal. The CSCU provides a clock control signal for changing a frequency of a clock signal in response to the at least one comparison signal. The oscillator generates the clock signal having a frequency according to the clock control signal. The PCCU passes or intercepts the clock signal to provide a pumping clock signal, in response to a control signal. The charge pump consecutively performs charge pumping operations to provide the high voltage while the pumping clock signal is applied to the charge pump.

Abstract: In one embodiment, an apparatus for reducing leakage in an electronic circuit (e.g., a CMOS circuit) includes a power switch transistor configured to selectively couple or decouple a voltage to a logic portion of the electronic circuit. The power switch transistor receives a first voltage during an active mode of the electronic circuit and receives a second voltage during a sleep mode of the electronic circuit. The power switch transistor has a bulk region that is biased using the first voltage during sleep mode. The power switch transistor has a gate region that is biased using the first voltage during sleep mode.

Abstract: A constant voltage boost power supply according to an aspect of the invention includes a voltage-controlled variable frequency oscillator that produces and supplies a clock signal and changes an oscillating frequency of the supplied clock signal according to an input control voltage; a charge pump into which the clock signal is fed, the charge pump performing a pumping operation in synchronization with the clock signal to boost an input voltage and supply an output voltage in which the input voltage is boosted; a voltage dividing circuit that divides the output voltage of the charge pump to supply a monitor voltage; and a differential amplifier into which the monitor voltage and a reference voltage are fed, the differential amplifier amplifying a potential difference between the monitor voltage and the reference voltage to supply the control voltage.

Abstract: One embodiment is a gate drive circuitry for switching a semiconductor device having a non-isolated input, the gate drive circuitry having a first circuitry configured to turn-on the semiconductor device by imposing a current on a gate of the semiconductor device so as to forward bias an inherent parasitic diode of the semiconductor device. There is a second circuitry configured to turn-off the semiconductor device by imposing a current on the gate of the semiconductor device so as to reverse bias the parasitic diode of the semiconductor device wherein the first circuitry and the second circuitry are coupled to the semiconductor device respectively through a first switch and a second switch.

Abstract: The present invention is a semiconductor integrated circuit device including a target circuit, a voltage supply circuit that supplies the power supply voltage to the target circuit, a control circuit that controls an output voltage of the voltage supply circuit, and a target voltage prediction circuit that predicts a voltage value of the power supply voltage. The control circuit changes the output voltage of the voltage supply circuit by a predetermined voltage value. The target voltage prediction circuit detects a change amount of an operating frequency of the target circuit along with the change of the predetermined voltage value, and calculates a target voltage value based on a relation between the change amount of the operating frequency and the predetermined voltage value. The voltage supply circuit supplies a power supply voltage corresponding to the target voltage value to the target circuit.

Abstract: Circuit, system and method of current control circuits are disclosed. In one embodiment, a control circuit includes a first MOS transistor and a second MOS transistor. The first source/drains of the first and the second MOS transistors are coupled to an output of a power source. A second source/drain of the first MOS transistor is coupled to a first output node of the current control circuit. A second source/drain of the second MOS transistor is coupled to a second output node of the current control circuit. The control circuit further includes a means to block flow of current from the first output node of the current control circuit to the second output node of the current control circuit.

Abstract: A substrate biasing circuit may include a first pump control circuit that generates a first control signal in response to a first reference voltage and a voltage of a first substrate portion, and includes a first reference generator coupled between a temperature compensated voltage and a reference power supply voltage that varies the first reference voltage in response to the voltage of the first substrate voltage and the temperature compensated voltage. A first clamp circuit may generate a first clamp signal in response to a first limit voltage and the voltage of the first substrate portion, the first limit voltage being a scaled version of the temperature compensated voltage. A first charge pump may pump the first substrate portion in at least a first voltage direction in response to the first control signal, and is prevented from pumping in the first voltage direction in response to the first clamp signal.

Abstract: A light-emitting device driving circuit capable of reliably performing emission control on a light-emitting device of a low emission threshold (about 10 mA or less) and capable of correcting a distortion due to the Early effect of a transistor in the drive current supplied to the light emitting device. The light limiting device driving circuit includes a current control unit (101) which controls the value of a main current based on a control voltage, a bias current source (CC1) for subtracting a bias current from the main current, and a switching unit (103) which controls emission of light from the light-emitting device by switching, based on the drive signal, a current obtained by subtracting the bias current from the main current or a current based on the current obtained by the subtraction.

Abstract: Circuits and methods are provided for facilitating transitioning of a digital circuit from backgate biased standby mode to active mode. The digital circuit includes a semiconductor substrate, multiple n-channel transistors disposed at least partially in one or more p-type wells in the semiconductor substrate, multiple p-channel transistors disposed at least partially in one or more n-type wells in the semiconductor substrate, and a backgate control circuit. The backgate control circuit is electrically coupled to the p-type well(s) and to the n-type well(s) to facilitate transitioning of the multiple n-channel transistors and the multiple p-channel transistors from backgate biased standby mode to active mode by automatically shunting charge from the n-type well(s) to the p-type well(s) until a well voltage threshold is reached indicative of a completed transition of the transistors from backgate biased standby mode to active mode.

Abstract: A data clock control apparatus includes a bias voltage generator configured to receive a plurality of test mode signals and a plurality of fuse signals and to generate a bias voltage to secure a predetermined potential difference from an external driving power supply, and a clock signal controller configured to receive the bias voltage and to buffer an external clock signal and outputs a data output clock signal.

Abstract: Methods and apparatus to reduce voltage bounces and spike voltages in switching amplifiers are disclosed. An example method of removing a substrate current from a substrate disclosed herein comprises injecting the substrate current via turning on an active device, forming a low impedance path to ground via a substrate clamp based on the substrate current, and removing the substrate current from the substrate via the substrate clamp.

Abstract: A circuit for generating negative voltage includes a variable period oscillator configured to generate an oscillator signal enabled in response to a detection signal and to determine a period of the oscillator signal in response to a control signal, a pump configured to perform pumping operations in response to the oscillator signal and to generate a negative voltage by the pumping operations, a negative voltage detecting unit configured to detect the level of the negative voltage to generate the detection signal, and a gate-induced drain leakage current detecting unit configured to measure the amount of a gate-induced drain leakage current to generate the control signal.

Abstract: A charge pump regulator has a charge pump to establish a charge path and a discharge path alternately, so as to produce a regulated voltage on an output terminal. The charge pump has at least a current control element on the charge path or the discharge path to control the current flowing therethrough according to an output-dependent feedback signal.

Abstract: Switches with connected bulk for improved switching performance and bias resistors for even voltage distribution to improve reliability are described. In an exemplary design, a switch may include a plurality of transistors coupled in a stack and at least one resistor coupled to at least one intermediate node in the stack. The transistors may have (i) a first voltage applied to a first transistor in the stack and (ii) a second voltage that is lower than the first voltage applied to bulk nodes of the transistors. The resistor(s) may maintain matching bias conditions for the transistors when they are turned off. In one exemplary design, one resistor may be coupled between the source and drain of each transistor. In another exemplary design, one resistor may be coupled between each intermediate node and the first voltage. The resistor(s) may maintain the source of each transistor at the first voltage.

Abstract: A body-bias voltage controller includes: a plurality of transistors at least one of which is supplied with a body-bias voltage; a monitor circuit to detect voltage characteristics of the plurality of transistors and to output a indicator signal; and a body-bias voltage generator to generate the body-bias voltage based upon the indicator signal.

Abstract: In one or more embodiments described herein, there is provided an apparatus comprising a substrate, and a plurality of carbon nanotubes (semiconducting nano-elements) disposed and fixed with said substrate. The nanotubes are disposed and fixed on said substrate such that they define a carbon nanotube network substantially at the percolation threshold of the network. As the network is at the percolation threshold, this provides for one or more signal paths extending from an input region to an output region. The apparatus is configured to, upon receiving particular input signalling via the input region, provide particular predefined output signalling at the output via the one or more signal paths, the particular output signalling being predefined according to the one or more one signal paths.

Abstract: An internal voltage generation circuit includes a level detection unit configured to generate a detection voltage corresponding to a voltage level difference between a reference voltage with an internal voltage, an oscillation signal generation unit configured to generate an oscillation signal having a period corresponding to a voltage level of the detection voltage, and an internal voltage generation unit configured to generate the internal voltage in response to the oscillation signal.

Abstract: In one embodiment, a circuit for generating a reference voltage between a first output and a second output, has a first follower transistor that includes a first control node, a first follower node coupled to a first output, and a first supply node, and a second follower transistor that includes a second control node, a second follower node coupled to a second output and a second supply node. A first voltage drop circuit is coupled between a circuit supply node and the second supply node. The circuit is biased such that the voltage between the circuit supply node and the second supply node is greater than the voltage between the circuit supply node and the first supply node, and such that the voltage between the circuit supply node and the second control node is greater than the voltage between the circuit supply node and the first control node.

Abstract: A threshold personalization circuit for a reset or supervisor chip includes personalization fuses, which shift a resistor divider to provide a variety of selectable voltage thresholds. The personalization fuses may provide hundreds of millivolts of adjustment. The threshold personalization circuit further includes trim fuses to fine tune the threshold to within a few millivolts of the target threshold voltage. The threshold personalization circuit includes a test mode to cycle through to a particular personalization trim, such that at prelaser testing the personalized value is found (the fuse blow for personalization is emulated) and then the trim fuse amount can be based on the actual final personalized voltage. This results in very accurate threshold voltages for all personalized values.

Abstract: An integrated circuit comprising multiple independent power supply zones at substantially the same voltage level and a method for utilizing such power supply zones. An integrated circuit may comprise a first module and may, for example, comprise a second module. A first power supply bus may communicate first electrical power to the first module, where the first electrical power is characterized by a first set of power characteristics comprising a first voltage level. A second power supply bus may communicate second power to the second module, where the second power is characterized by a second set of power characteristics comprising a second voltage level that is substantially similar to the first voltage level. The second set of power characteristics may, for example, be substantially different than the first set of power characteristics. The second power supply bus may also, for example, communicate the second electrical power to the first module.

Abstract: A pumping voltage generating circuit in a semiconductor memory apparatus includes a voltage supplying unit configured to supply an external power supply voltage to a first node in response to a first transfer signal, a node control unit configured to couple the first node to a second node in response to a second transfer signal and to couple the second node to an output node in response to a third transfer signal, a first pumping unit configured to increase a voltage level on the first node through a pumping operation that is performed in response to a first oscillation signal and to control one of an amount of voltage increment and decrement on the first node in response to a first control signal, and a second pumping unit configured to increase a voltage level on the second node through a pumping operation that is performed in response to a second oscillation signal and to control one of an amount of voltage increment and decrement on the second node in response to a second control signal.

Abstract: Provided is a reference current generating circuit capable of maintaining a constant output level regardless of a temperature variation by the use of a reference resistor having a constant resistance regardless of the temperature variation. The reference current generating circuit includes a reference voltage circuit supplying a reference voltage having a constant level regardless of a temperature variation, and a reference resistor circuit comprising a resistor having a positive temperature coefficient and a resistor having a negative temperature coefficient that are connected in series, the reference resistor circuit having a constant total resistance regardless of the temperature variation. Herein, a reference current having a constant level regardless of the temperature variation is generated by the reference voltage and the resistance of the reference resistor circuit.

Abstract: An LED driving circuit can improve characteristics. A first current increasing circuit 10i4 is constituted of a first slow regulating unit 10i41 and a post-stage first supplying circuit 10i43 and, from a point in time of output switching of a first comparator 10i2, that is, when a set temperature exceeding a reference potential Va is attained, gradually increases a temperature compensated current IT1 (?I1) and thereby suppresses the lowering of emission output. Here, by gradually increasing the temperature compensated current IT1 by making use of charging/discharging functions of a capacitor, etc., that is, by increasing the temperature compensated current IT1 over a longer time than a pulse width that a photodetecting element, onto which light from an LED 11 is made incident, can respond within, pulse width distortion and jitter can be suppressed.

Abstract: A voltage regulation module which includes an adjustable voltage which reduces the positive supply voltage and increases the negative supply voltage during a lower power mode. The voltage regulation module includes a voltage generator which provides an N-type substrate bias voltage at the normal operating voltage level of the positive supply voltage and which provides a P-type substrate bias voltage at the normal operating voltage level of the negative supply voltage during the lower power mode. Thus, the supply voltage levels are adjusted rather than the substrate bias voltages during the lower power mode. The voltage generator may be implemented as a voltage regulator, or may be implemented as a bias generator or charge pump or the like.

Abstract: Methods, circuits and apparatus for biasing an amplifier to maintain consistent operational characteristics over variations in fabrication processes and operational temperature conditions are disclosed. A bias is determined by first comparing output voltages of replica circuits of the amplifier during an offset canceling phase. The output voltages are differently driven by an offset induced by a first reference current and the offset is canceled in response to the first comparing step. The output voltages are secondly compared during a calibration phase and a calibration bias current is adjusted in response to the second comparing step. The amplifier bias is determined based on the calibration bias current. The process is periodically repeated in response to operational variations.

Abstract: This invention includes a bias origination section configured to originate an original bias voltage; a comparison section configured to compare the original bias voltage and a comparison voltage, and output a comparison result; a resistive divider section composed by a resistance circuit including a variable resistor section having a resistor and a switch, and configured to generate the comparison voltage; a bias decision control section configured to determine bias decision data for controlling a resistance value of the variable resistor section so as to bring the comparison voltage close to the original bias voltage, based on a comparison result of the comparison section; and a storage section configured to hold the bias decision data and also output the comparison voltage as a bias voltage by controlling a resistance value of the variable resistor section based on the held bias decision data, thereby generating a low-noise bias with a small area.

Abstract: Provided is a load fluctuation compensation circuit for compensating a power source voltage supplied to an operation circuit, the load fluctuation compensation circuit including: a periodic signal changing section that receives a power source voltage from a power source shared with the operation circuit, and outputs a changed signal resulting from changing a supplied periodic signal according to the power source voltage; a phase comparator that compares a phase of the periodic signal with a phase of the changed signal outputted from the periodic signal changing section; an initializing section that generates a bias voltage supplied to the periodic signal changing section and adjusts a phase difference between the periodic signal and the changed signal to a preset value, based on the comparison result of the phase comparator; a controller that holds the bias voltage outputted from the initializing section when the phase difference between the periodic signal and the changed signal has become the preset value;

Abstract: A semiconductor integrated circuit apparatus includes an internal circuit having a MIS transistors on a semiconductor substrate and a substrate voltage control block that supplies a substrate voltage to the internal circuit and controls threshold voltages for the MIS transistors of the internal circuit. The apparatus also includes a leakage current detection MIS transistor and a leakage current detection circuit. The substrate voltage control block generates a substrate voltage based on comparison results of the comparator and applies the generated substrate voltage to the substrate of the leakage current detection MIS transistor and the substrate of the MIS transistors of the internal circuit. The substrate voltage control block includes a switch arranged between first and second input terminals of a comparator and a drain of the leakage current detection MIS transistor and a reference potential terminal, as well as an input data corrector that carries out substrate voltage adjustment.

Abstract: A semiconductor integrated circuit includes: a first flip-flop, a combined circuit and a second flip-flop that form a critical path; a first delay circuit and a third flip-flop that are provided in the post-stage of the combined circuit; a second delay circuit and a fourth flip-flop that are provided in the post-stage of the combined circuit; a first comparison circuit that compares the output of the second flip-flop with the output of the third flip-flop; a second comparison circuit that compares the output of the second flip-flop with the output of the fourth flip-flop: and a control circuit that controls a source voltage supplied to the combined circuit in accordance with the outputs of the comparison circuits. A delay time by the first delay circuit is different from a delay time by the second delay circuit.