Abstract: Disclosed is apparatus for operating with an RC filter (26, 26A), and a corresponding method. The apparatus includes circuitry (32) for use in measuring an actual value of at least one filter component and a controller (34), coupled to the measurement circuitry, for determining at least one adaptive filter (36, 46) coefficient using the measured actual value to so as to compensate for a deviation of at least one filter component value from an ideal value. Where the filter is embodied as an RC network, the circuitry measures an actual value of both a resistor and a capacitor, and the controller uses the measured actual value of the capacitor when determining the value of a resistor.

Abstract: A high pass filter comprising a combination of capacitors and insulated gate field effect transistors (IGFETs) used as effective resistors provides a low break frequency, while providing improved linearity and a stable break frequency over a relatively wide range of input voltages. The high pass filter can be realized with a small physical size. In one particular embodiment, the small physical size allows the capacitors and the IGFET devices to be integrated together onto a common substrate.

Abstract: A digital tuning circuit which generates a digital code representative of a difference of signals generated by a mirror trans-conductor circuit (having electrical characteristics similar to a trans-conductor circuit in a filter) and a reference circuit. The digital code is used to adjust the trans-conductance of both the mirror trans-conductor circuit and the filter. Some of the most/more significant bits may be used to selectively activate the respective trans-conductor elements contained in the mirror trans-conductor circuit and the filter. The remaining bits may be used to fine-tune the trans-conductance of the trans-conductor elements and the filter.

Abstract: A variable time constant circuit includes an inverting amplifier which has an amplifier input terminal and an amplifier output terminal connected to a signal output terminal and inverts a signal inputted to the amplifier input terminal, a first and a second resistor which are connected in series between the signal input terminal and the amplifier input terminal, a capacitor connected between the amplifier input terminal and the amplifier output terminal, a field effect transistor including a gate terminal connected to a junction point of the first and second resistors, a source terminal kept at a constant potential, and a drain terminal connected to the amplifier input terminal, the transistor flowing a current through the drain terminal according to a voltage between the gate terminal and the source terminal, and a control circuit which controls a voltage-current conversion ratio of the transistor according to a time constant control signal.

Abstract: A filter module for reducing a DC offset voltage in a radio frequency communication channel is described. A first capacitor is coupled between a first differential input node and a first differential output node. A second capacitor is coupled between a second differential input node and a second differential output node. An active variable resistor is coupled between the first differential output node and the second differential output node. The active variable resistor receives a control signal. The control signal adjusts the value of the active variable resistor, which adjusts the frequency response of the filter module. The rate at which the filter module reduces DC offset voltages is thereby adjusted. The filter module is also adaptable to single-ended applications.

Abstract: A method and an apparatus for tuning a filter is provided wherein the filter has at least one adjustable element for adjusting at least one performance parameter of the filter like for example a cut-off frequency, wherein a pseudo-random test sequence is applied to the filter, wherein the cross-correlation function of the test sequence and the filtered test sequence is calculated, and wherein the at least one adjustable parameter is adjusted until the cross-correlation function at at least one point basically coincides with a corresponding point of a nominal cross-correlation function for the filter.

Abstract: A signal processing system (100) comprises an input terminal (102), and a main path having a main filter input gain unit (126) coupled to said input terminal (102), a main filter (132) and an output gain unit (138). An auxiliary path includes an auxiliary filter input gain unit (106) coupled to the input terminal (102), an auxiliary filter (112) and an auxiliary filter output gain unit (118). An adder (144) is coupled to the output gain units (118, 138) for generating an output signal to an output terminal (148). The gains of the gain units are adjusted by a control unit (18) responsive to a detecting signal from a detector (160).

Abstract: A method and apparatus is described that filters an electrical signal. The filtering uses a capacitor multiplier circuit where the capacitor multiplier circuit uses at least one amplifier circuit and at least one capacitor. A filtered electrical signal results from a direct connection from an output of the at least one amplifier circuit.

Abstract: An active filtering method and apparatus for controlling a current generator that sources/sinks an APF current for compensating polluting harmonics on a power line connecting a power source and a load. A feedback loop regulates the APF current by sensing the current output of the current generator and the current flowing through the load. The feedback loop controls the current generator to force the APF current to track a current command signal to effectively limit the APF current to a safe value within the limitations of a particular design.

Abstract: A resistor capacitor (RC) tracking loop includes a parasitic insensitive integrator (211) charged by a buffer (207) with offset compensation. The integrator (211) operates to provide an accurate ramped voltage proportional to a measured RC time constant. A single comparator (213) is used for sensing the voltage ramp rate by detecting two multiplexed reference voltages (VREFLO VREFHI). A timer within controller (201) is triggered by the VREFLO crossing at comparator (213). The timer counts the number of precision reference clock periods (FREF) that occur between the VREFLO and VREFHI crossings and adjusts an accumulator within controller (201) to a value (M). This value (M) is directly used to adjust a resistor and/or capacitor array used in a continuous time filter whose bandwidth and corner frequency can be precisely tuned.

Abstract: A tunable filter circuit includes a first differential pair biased by a first current, a second differential pair biased by a second current, a first capacitor and a second capacitor. The tunable filter circuit of the present invention can be configured as a bandpass filter or a bandstop filter by connecting the input voltage signal to different input nodes of the tunable filter circuit. The tunable filter circuit can be tuned by adjusting the values of the first current and the second current. In an alternate embodiment, frequency tuning is achieved either by switching capacitive loads or changing resistive impedances introduced at the emitter of the differential pairs, which also extends the input voltage range of the filter. This emitter resistance is implemented using MOS switches whose on-resistance can be controlled for a precise tuning within a large frequency range.

Abstract: A filter for processing frequency signals, preferably received, particularly digital television signals is described, which filter comprises a Chebyshev filter (11, 12), a subsequent all-pass filter (13) and a control device (14 to 20) for controlling the Chebyshev filter (11, 12) and the all-pass filter (13).

Abstract: A phase locked loop (PLL) comprising an input, an output, a charge generator, a low pass filter 3, an oscillator 4 and a frequency divider 5. The frequency divider 5 has an input coupled to the output of the PLL and an output coupled to an input of the charge generator. The frequency at the output of the frequency divider 5 is equal to the frequency at the input of the frequency divider divided by a selectable divider ratio N. The PLL has a damping factor z and a bandwidth to compare frequency ratio ?3/?ref. The low pass filter 3 has a first capacitor for integrating the charge produced by the charge generator. The capacitance of that first capacitor is arranged to be proportional to the divider ratio N so that the damping factor z and the bandwidth to compare frequency ratio ?3/?ref are substantially independent of the divider ratio N.

Abstract: The invention relates to an integrated circuit arrangement with an active filter comprising transconductance stages, each being adjustable by means of a bias current to be supplied, and comprising a tuning device for tuning the filter, which tuning device adjusts the bias currents of the transconductance stages, wherein the tuning device adjusts the bias current of a first transconductance stage, for the purpose of achieving a desired characteristic of this transconductance stage, and adjusts the bias current of at least one further transconductance stage such that the transconductance of this further transconductance stage deviates from the transconductance of the first transconductance stage by a certain value.

Abstract: A frequency response adjuster for a frequency responsive circuit, and a method for tuning a frequency response of a circuit, are disclosed. The adjuster may include a time constant sensor, wherein a charging state of the frequency responsive circuit may be measured by, and output from, the time constant sensor as a first voltage, a converter that samples the first voltage and outputs a second voltage resultant from a conversion of the first voltage by the converter, an array of trimming components, and a selector that utilizes the second voltage to select at least one trimming component from the array of trimming components. The method includes the steps of sensing a time constant of the circuit, outputting the sensing as a first voltage, sampling the first voltage over a fixed interval, converting the sampled first voltage to a second voltage, and selecting, utilizing the second voltage, at least one trimming component from an array of trimming components.

Abstract: The present invention provides a reconfigurable filter having a bandwidth and frequency offset that are independently configured, thereby allowing the filter to realize any filter pole. In general, the filter includes a filtering stage and a reverse gain stage. The filtering stage has a bandwidth configured by a bandwidth control signal from control logic and a frequency offset configured by an offset control signal. The reverse gain stage provides the offset control signal to the filtering stage based a reverse gain control signal from the control logic and the output signal. Based on the bandwidth control signal and the reverse gain control signal, the bandwidth of the filter is configured independently from the frequency offset of the filter and the frequency offset is configured independently from the bandwidth.

Abstract: A system for estimating the bandwidth of a baseband filter that produces a phase shift on arriving analog signals is disclosed. The system comprises means for generating a digital reference clock signal and means for converting the digital reference clock signal into an analog reference clock signal to be input to the baseband filter. Phase comparison means are coupled to the baseband filter for comparing the digital reference clock signal to the analog reference clock signal phase shifted through the baseband filter. A digital pulsed signal that is representative of the phase shift is generated, and digital circuit means connected to the phase comparison means convert the digital pulsed signal into a digital value, the digital value being proportional to the phase shift of the baseband filter.

Abstract: An adaptive speech filter (10) for conditioning speech signals to increase signal to noise ratio in a relatively noisy environment. The adaptive speech filter (10) has a preamp circuit (12), a high pass adaptive filter circuit (14), an output buffer circuit (16), a peak detector amplifier/filter circuit (18), a peak detector circuit (20) and a voltage regulator circuit (22), embodied in an application specific integrated circuit (24). The adaptive speech filter (10) is intended for input to telephones, radios, and the like.

Abstract: The method includes an adjustment phase in which a filtering device is operated as an oscillator, the frequency of oscillation of the filtering device is determined, and the characteristics of the filtering device are corrected with respect to the determined oscillation frequency and to a pre-established relation between the frequency of oscillation and the theoretical cutoff frequency, in such a way as to confer upon the filtering device a cutoff frequency equal to the theoretical cutoff frequency to within a tolerance. After the adjustment phase, a working phase takes place in which the filtering device carries out its filtering function.

Abstract: A voltage controlled band-pass filter is in a phase locked loop. The output from a phase detector is applied through a loop filter as the control voltage. The phase detector output is proportional to the difference in phase between first and second signals input to the phase detector. The first signal is fed directly from a local oscillator to the phase detector. The second signal is fed from the local oscillator to the phase detector through the voltage controlled band-pass filter.

Abstract: A transconductance-capacitance filter having a plurality of transconductors, that operates in a normal operation mode and a testing/tuning operation mode. During the normal operation mode, the transconductors operate as having normal transconductances. During the testing/tuning operation mode, the transconductances are scaled by a same amount, so that frequencies of the test signals provided are lower than in the normal operation mode, and so that transfer characteristics of the filter can be easily verified.

Abstract: A time constant-based calibration circuit for tuning active filter circuitry. A time constant, e.g., corresponding to that of the active filter circuitry, within the calibration circuit is monitored and maintained at a desired value using successive approximation, with continuous calibration of the time constant performed using digital circuitry and a digital feedback signal to control the time constant.

Abstract: A discrete-time analog filter, where a filter tap of the filter comprises a voltage-to-current converter, an active current mirror, and a current multiplier to provide a current signal indicative of a weighted sampled voltage signal. The current signals from the filter taps are summed by one or more active cascode differential latches to provide an output logic signal indicative of the filtered output. The discrete-time analog filter finds applications in channel equalization, and is suitable for high data rates and low voltage applications. The voltage and current signals may be differential. The voltage-to-current converter may include a common-mode high-pass filter to reject common-mode voltage variations.

Abstract: A filter (3) is described, which filter is provided with field effect (FET) capacitors (M1-32; M′1-32) arranged for controlling their respective capacity values, each such FET capacitor (M1-32; M′1-32) having a source (S) and a drain (D). The source (S) and the drain (D) of each FET capacitor (M1-32; M′1-32) are coupled to one another. The filter acting as an impedance transformer is a passive low power consuming and tunable filter, such as for a radio frequency (RF) receiver. It occupies only a very small area, while integrated on chip.

Abstract: A fast-setting DC offset removal circuit with continuous cutoff frequency switching is disclosed. In the preferred embodiment, the circuit is implemented using a pair of RC filters for receiving a differential signal pair and a continuous, variable resistance control circuit. The control circuit can be current-controlled or voltage controlled to provide fast settling of the received signal and the removal of the DC offset components. Additionally, by using a current-controlled control circuit, the cutoff frequency of the RC filter can be ramped from high to low in a continuous manner, thereby minimizing the generation of DC offsets.

Abstract: A first operational amplifier receives a reference voltage at one input terminal, a first transistor is connected between a first power source line and the first operational amplifier, a second transistor is connected between the first power source line and the first operational amplifier, a resistor is connected between the first transistor and a second power source line, a first switch is connected to the second transistor, a variable capacitor connected between the first switch and the second power source line, a second switch is connected the variable capacitor and the second power source line, a second operational amplifier is connected to the variable capacitor and the reference voltage, a third switch is connected to the second transistor, a load is connected between the third switch and the second power source line, and a control circuit is connected to the first to third switches.

Abstract: A controllable apparatus for providing a compensated RF signal including an input port for coupling with an RF signal source, such as a multifrequency CATV signal, and an output port for coupling to an associated electronic device. The controllable apparatus generates new second and third order products from the multifrequency RF signal which are the same magnitude, but opposite in phase to the nonlinear products generated by the electronic device. Since both the original multifrequency RF input signal and the new generated products from the distortion control circuit are coupled to the electronic device, the nonlinear products from the distortion control circuit and the electronic device will be canceled and the output of the electronic device will comprise only the multifrequency RF signal. The controllable apparatus includes an RF circuit path and a controllable nonlinear compensator transversely connected to the RF circuit path. A control bias input allows selective control of the nonlinear compensator.

Abstract: An adjustable filter, particularly for use as an antialiasing filter in digital telecommunications networks, includes adjustable capacitors which determine frequency response for the purpose of accurate alignment with a particular cut-off frequency. The active filter includes, in line with the invention, a control device with a measuring device for ascertaining the actual cut-off frequency of the filter. On the basis of the ascertained actual cut-off frequency of the filter and the information about the nominal cut-off frequency which is to be set, an adjustment parameter for the adjustable capacitor is selected from a memory arrangement. This adjustment parameter is used to adjust the adjustable capacitor such that the desired nominal cut-off frequency is obtained and, at the same time, the alignment is performed to achieve the nominal cut-off frequency with sufficient accuracy.

Abstract: A digital tuning circuit which generates a digital code representative of a difference of signals generated by a mirror trans-conductor circuit (having electrical characteristics similar to a trans-conductor circuit in a filter) and a reference circuit. The digital code is used to adjust the trans-conductance of both the mirror trans-conductor circuit and the filter. Some of the most/more significant bits may be used to selectively activate the respective trans-conductor elements contained in the mirror trans-conductor circuit and the filter. The remaining bits may be used to fine-tune the trans-conductance of the trans-conductor elements and the filter.

Abstract: The adaptive filter can be realized with a very low circuitry outlay, as a result of which the adaptive filter for the first time becomes practical for many applications. In particular, the area required by the filter is small since the large time constants that are necessary for many applications can be realized in a simple manner by the control circuit. The adaptive filter is suitable in particular for “mixed signal ASICS”, in which the required preconditions for the control circuit are already present, so that the control circuit can be realized just by means of corresponding wiring.

Abstract: A programmable capacitor array including a plurality of user-selectable, numerically weighted capacitors, each of which includes at least one fixed capacitor and one manufacturer-controlled trim capacitor, advantageously provides a variety of selectable capacitance values for a programmable analog integrated circuit. When coupled to a memory, for example a static memory, switches can be controlled that determine whether a particular fixed capacitor (user-selectable) or trim capacitor (manufacturer-selectable) is electrically coupled into the circuit. User access to those portions of memory controlling switches associated with the trim capacitors can be restricted via an I/O interface and security command. Such programmable capacitor arrays allow efficient implementation of user-programmable filter circuits where the user can conveniently program or reprogram a variety of filter parameters.

Abstract: A composite loop compensation circuit and method for a low drop-out regulator configured to facilitate stable operation at very low output load currents is provided. An exemplary low drop-out regulator includes an error amplifier, a pass device, and a composite loop compensation circuit. The compensation loop compensation circuit includes a plurality of segmented sense devices, a plurality of switches and a biasing component. The plurality of segmented sense devices are configured to sense an output load current, i.e., the current from the output terminal of the pass device. The plurality of switches are coupled between the plurality of segmented sense devices and a biasing component. Composite loop compensation circuit is configured to adjust the dominant first pole of the composite feedback loop based on the output load current through biasing of the active resistor component.

Abstract: An output stage compensation circuit and method for a low drop-out regulator configured to facilitate stable operation while providing output voltage and current to downstream circuit devices is provided. An exemplary low drop-out regulator is configured with an output stage compensation circuit including one or more segmented sense devices configured to drive one or more fixed current sources. Each segmented sense device is configured to compensate a suitable range of output current and to multiply the effect of associated compensation capacitors. The one or more segmented sense devices are configured to provide pole-zero compensation based on output current. Further, the current range of each segment can be overlapped. As a result, the stability of the low drop-out regulator is not dependent upon the output current requirements or the capacitance requirements of the downstream circuit.

Abstract: An automatically adjusting gain/bandwidth loop filter suitable for a digital phase lock loop or a digital adaptive carrier recovery loop with variable loop gain/bandwidth for rapid acquisition and lower steady-state jitter is provided. The automatically adjusting gain/bandwidth loop filter comprises a variable gain/bandwidth loop filter, a tracking status detector and a gain/bandwidth control state machine. The tracking status detector observes the frequency error which is the output of the frequency tracking (integral) branch of the variable gain/bandwidth loop filter, then it outputs a tracking state of the carrier recovery loop. The loop gain/bandwidth is then adjusted by the gain/bandwidth control state machine in response of the tracking state to improve the pull-in time and steady-state carrier frequency jitter.

Abstract: The invention relates to trimming of analogue filters (201) in integrated circuits by means of an automatic adjusting circuit. A local oscillator (202) in the automatic adjusting circuit provides a periodic reference signal (R) to an adjustable phase shifter (203), which on basis thereof, produces a periodic phase shifted signal (R*). A phase detector (204) receives both the periodic reference signal (R) and the phase shifted period signal (R*) and produces a test signal (T) in response to a phase difference between the periodic reference signal (R) and the periodic phase shifted signal (R8). A lowpass filter (205) receives the test signal (T) and generates a level signal (TDC) relative a reference level, e.g. representing a zero voltage. A digital signal processor (207) produces a primary control signal (CS), having a serial format, on basis of the observation signal (M). A serial-to-parallel converter (208) converts the primary control signal (CS) into a control signal (CP) having a parallel signal format.

Abstract: A transconductance-capacitance filter having a plurality of transconductors, that operates in a normal operation mode and a testing/tuning operation mode. During the normal operation mode, the transconductors operate as having normal transconductances. During the testing/tuning operation mode, the transconductances are scaled by a same amount, so that frequencies of the test signals provided are lower than in the normal operation mode, and so that transfer characteristics of the filter can be easily verified.

Abstract: An at least second-order active filter circuit includes an operational amplifier (Op) whose frequency response, in conjunction with an RC network (R1, R2, C1, C2), serves to set a predetermined low-pass characteristic. The frequency response of the operational amplifier (Op) forms an integral part of this low-pass characteristic.

Abstract: An integrated circuit for receiving a clock signal is described and has a clock input and a receiver circuit. A clock signal can be applied to the clock input. A filter circuit is provided, whose input is connected to the clock input for the purpose of filtering out a frequency and/or a frequency range of the clock signal. An output of the filter circuit, which output produces the filtered clock signal, is connected to the receiver circuit for the purpose of transferring the filtered clock signal to the integrated circuit for processing.

Abstract: A semiconductor integrated circuit includes a filter and a time-constant detecting circuit. The filter includes resistance elements; capacitance elements, each of which consists of a capacitance-value switching circuit that can vary the capacitance of the capacitance elements and operational amplifiers. The time-constant detecting circuit detects the time constant of the capacitance element and resistance element, which are formed independently of the capacitance elements and resistance elements of the filter. The semiconductor integrated circuit varies the capacitance of the capacitance element in response to the detected time constant to prevent a reduction in the yield by adjusting the cut-off frequency of the filter in spite of variations in manufacturing the resistance elements and capacitance elements of the filter.

Abstract: An analog or continuous tuning loop which generates an analog signal representative of a difference of signals generated by a mirror trans-conductor circuit (having electrical characteristics similar to other such trans-conductor circuits used in a filter) and a reference circuit. The analog signal is used to adjust the trans-conductance such that the current generated by the trans-conductance circuit equals a reference current generated by the reference circuit. A filter using such trans-conductor circuits may be designed to be tuned to a desired cut-off frequency when the desired trans-conductance is achieved. An additional digital circuit generates a few digital bits, which may be used to selectively activate the respective trans-conductor elements contained in the mirror trans-conductor circuit and the filter.

Abstract: A digital filter for forming a feedback path including a delay unit, applying a filter operation to an input signal, giving a frequency characteristic having a predetermined time constant, and generating an output signal, is provided with: a selector having a multiplier for implementing time constants in at least two stages, and selecting the connection of the multiplier corresponding to a preset time constant to perform time constant switching; a timing generator for determining the timing when the time constant switching is performed by the selector; and a correction device for correcting the output of the delay unit to suppress variations in the output signal in the determined timing.

Abstract: Methods and systems for tuning an RC continuous-time filter are disclosed. In this regard a representative system for tuning an RC continuous-time filter includes a coarse-tuned resistive element coupled to an input of the filter for varying the cut-off frequency of the filter based upon process variations. The system also includes a MOSFET transistor coupled to the resistive element. The MOSFET transistor provides a resistance dependent upon a voltage offset provided to the gate of the transistor, wherein the resistance of the transistor offsets an adjustment in the resistance of the resistive element caused by temperature variations. The system also includes a voltage offset generator configured to provide the voltage offset to the transistor.

Abstract: An integrated circuit (ICT) comprising a filter (50). The filter comprises an input (&ugr;in+) for receiving an input signal and an output (56) for producing an output signal having a frequency cutoff point. The filter further comprises at least one resistor network (RN1) coupled between the input and the output. The resistor network comprises a first non-switched resistance (R1.1) and a first resistance series connection connected in parallel with the first non-switched resistance. The first resistance series connection comprises a switched resistance (R1.2) connected in series with a source/drain path of a switching transistor (TRR1.2), the switching transistor having a gate for receiving a control signal. The frequency cutoff point is adjustable in response to the control signal. Additionally, the switched resistance has a first resistance and the switching transistor has an on-resistance. Further, the on-resistance is at least 20 percent of the total of the first resistance and the on-resistance.

Abstract: A subordinate low pass filter 21 having characteristics similar to those of a main low pass filter 11 is provided. A signal of a frequency corresponding to a cut-off frequency is supplied from a signal generating circuit 22 to the subordinate LPF 21. A phase difference detecting circuit 23 detects a phase shift amount which is caused when the signal of the cut-off frequency is supplied to the subordinate LPF 21. An error detecting circuit 24 compares a value corresponding to the phase shift amount caused in the subordinate LPF 21 when the signal of the cut-off frequency is supplied with a reference value corresponding to the phase shift amount to be caused in the subordinate LPF 21 at the time of the cut-off frequency on phase characteristics. A comparison output is used as a control signal and the subordinate LPF 21 and main LPF 11 are controlled to have a desired cut-off frequency.

Abstract: A variable frequency filter circuit, provided with a low pass filter constituted of a gm amplifier, is a low pass filter circuit in which a micro controller controls a current value converting circuit so as to adjust a reference current of the low pass filter in order to adjust a cut-off frequency. When the variable frequency filter circuit is in an adjusting mode, the variable frequency filter circuit detects a shift in a cut-off frequency of the low pass filter for filtering an actual signal. As to a dynamic change in a power supply voltage, ambient temperature or the like, which cannot be detected in real time, a value of the shift can be worked out in advance and with accuracy via simulation. Therefore, the shift is compensated in accordance with the value stored in a data memory. This requires no need of an arrangement to have a separate reference filter for detecting a shift for compensation of the shift, thereby eliminating an influence the arrangement.

Abstract: A T-network containing three impedances is provided between two terminating ends connected to a non-fixed voltage level. Two impedances are connected in series between the two terminating ends. A third impedance is connected between the junction of the first two impedances and a fixed voltage. Switches may be used to trim the third impedance, thus obtaining a desired voltage between the two terminating ends. A terminal of any switches used for trimming can be connected to the fixed voltage node, thereby ensuring that the impedance introduced by the switches does not change substantially during different operating situations.

Abstract: A programmable phase locked-loop (PLL) active filter circuit is provided which includes networks of cooperating bandwidth tuning components to select bandwidth ranges. The values and arrangement of the network of selectable series input (R1) resistors are chosen to be useful in both low band and high band settings. Likewise, the opamp network of feedback resistors (R2) and capacitors (C1) values are chosen to be useful in both low band and high band applications, automatically pairing with the R1 selection in response to a bandwidth range selection. These tuning components, internal to an integrated circuit, can be used for a plurality of wideband loops. External components can be used to supplement the internal components for low and high bandwidth applications.

Abstract: A circuit comprises an active filter with linear elements and a tuning circuit with linear elements of the same type as the filter circuit. A backward counter generates a count value that represents a time constant of the tuning circuit. The initial value of the backward counter contains information concerning the relationship between the time constant of the filter circuit and the tuning circuit. A decoder creates a digital code responsive to the count value which is used to switch an array of linear elements in order to tune the time constant of the filter to approximately a desired design value.

Abstract: A filter-equipped semiconductor integrated circuit includes a filter and a time-constant detecting circuit. The filter includes resistance elements; capacitance elements, each of which consists of a capacitance-value switching circuit that can vary the capacitance value of the capacitance element; and operational amplifiers. The time-constant detecting circuit detects the time constant of the capacitance element and resistance element, which are formed independently of the capacitance elements and resistance elements of the filter. The filter-equipped semiconductor integrated circuit varies the capacitance value of the capacitance element in response to the detected time constant so as to prevent the reduction in the yield by adjusting the cut-off frequency of the filter in spite of the manufacturing variations in the resistance elements and capacitance elements of the filter.

Abstract: A variable time constant integrator includes an amplifier configured to generate an output signal, a capacitor coupled to provide feedback to the amplifier, and a variable gain element coupled to the output of the amplifier and to the capacitor. The variable gain element is configured to provide the product of a gain and the output signal to the capacitor. The variable gain element is also configured to receive an indication of a new value of the gain and to responsively set the gain equal to the new value of the gain. Adjusting the gain of the variable gain element adjusts the integrator's time constant.